1 /* $NetBSD: tegra_pcie.c,v 1.29 2020/01/07 10:20:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.29 2020/01/07 10:20:07 skrll Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/extent.h> 37 #include <sys/intr.h> 38 #include <sys/kmem.h> 39 #include <sys/kernel.h> 40 #include <sys/lwp.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 45 #include <machine/cpu.h> 46 47 #include <arm/cpufunc.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <arm/nvidia/tegra_reg.h> 54 #include <arm/nvidia/tegra_pciereg.h> 55 #include <arm/nvidia/tegra_pmcreg.h> 56 #include <arm/nvidia/tegra_var.h> 57 58 #include <dev/fdt/fdtvar.h> 59 60 /* Interrupt handle flags */ 61 #define IH_MPSAFE 0x80000000 62 63 static int tegra_pcie_match(device_t, cfdata_t, void *); 64 static void tegra_pcie_attach(device_t, device_t, void *); 65 66 #define TEGRA_PCIE_NBUS 256 67 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 68 69 struct tegra_pcie_ih { 70 int (*ih_callback)(void *); 71 void *ih_arg; 72 int ih_ipl; 73 int ih_mpsafe; 74 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 75 }; 76 77 struct tegra_pcie_softc { 78 device_t sc_dev; 79 bus_dma_tag_t sc_dmat; 80 bus_space_tag_t sc_bst; 81 bus_space_handle_t sc_bsh_afi; 82 bus_space_handle_t sc_bsh_pads; 83 bus_space_handle_t sc_bsh_rpconf; 84 int sc_phandle; 85 86 struct arm32_pci_chipset sc_pc; 87 88 void *sc_ih; 89 90 kmutex_t sc_lock; 91 92 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 93 u_int sc_intrgen; 94 95 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 96 }; 97 98 static int tegra_pcie_intr(void *); 99 static void tegra_pcie_init(pci_chipset_tag_t, void *); 100 static void tegra_pcie_enable(struct tegra_pcie_softc *); 101 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 102 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 103 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 104 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 105 uint, uint); 106 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 107 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 108 109 static void tegra_pcie_attach_hook(device_t, device_t, 110 struct pcibus_attach_args *); 111 static int tegra_pcie_bus_maxdevs(void *, int); 112 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 113 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 114 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 115 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 116 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 117 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 118 119 static int tegra_pcie_intr_map(const struct pci_attach_args *, 120 pci_intr_handle_t *); 121 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 122 char *, size_t); 123 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 124 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 125 uint64_t); 126 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 127 int, int (*)(void *), void *, 128 const char *); 129 static void tegra_pcie_intr_disestablish(void *, void *); 130 131 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 132 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 133 134 static int 135 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 136 { 137 const char * const compatible[] = { 138 "nvidia,tegra210-pcie", 139 "nvidia,tegra124-pcie", 140 NULL 141 }; 142 struct fdt_attach_args * const faa = aux; 143 144 return of_match_compatible(faa->faa_phandle, compatible); 145 } 146 147 static void 148 tegra_pcie_attach(device_t parent, device_t self, void *aux) 149 { 150 struct tegra_pcie_softc * const sc = device_private(self); 151 struct fdt_attach_args * const faa = aux; 152 struct extent *ioext, *memext, *pmemext; 153 struct pcibus_attach_args pba; 154 bus_addr_t afi_addr, cs_addr, pads_addr; 155 bus_size_t afi_size, cs_size, pads_size; 156 char intrstr[128]; 157 int error; 158 159 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 160 aprint_error(": couldn't get afi registers\n"); 161 return; 162 } 163 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 164 aprint_error(": couldn't get pads registers\n"); 165 return; 166 } 167 #if notyet 168 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 169 aprint_error(": couldn't get cs registers\n"); 170 return; 171 } 172 #else 173 cs_addr = TEGRA_PCIE_RPCONF_BASE; 174 cs_size = TEGRA_PCIE_RPCONF_SIZE; 175 #endif 176 177 sc->sc_dev = self; 178 sc->sc_dmat = faa->faa_dmat; 179 sc->sc_bst = faa->faa_bst; 180 sc->sc_phandle = faa->faa_phandle; 181 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 182 &sc->sc_bsh_afi); 183 if (error) { 184 aprint_error(": couldn't map afi registers: %d\n", error); 185 return; 186 } 187 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 188 &sc->sc_bsh_pads); 189 if (error) { 190 aprint_error(": couldn't map pads registers: %d\n", error); 191 return; 192 } 193 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 194 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh_rpconf); 195 if (error) { 196 aprint_error(": couldn't map cs registers: %d\n", error); 197 return; 198 } 199 200 tegra_pcie_conf_map_buses(sc); 201 202 TAILQ_INIT(&sc->sc_intrs); 203 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 204 205 aprint_naive("\n"); 206 aprint_normal(": PCIE\n"); 207 208 tegra_pmc_power(PMC_PARTID_PCX, true); 209 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 210 211 tegra_pcie_enable_clocks(sc); 212 213 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 214 aprint_error_dev(self, "failed to decode interrupt\n"); 215 return; 216 } 217 218 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 219 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 220 if (sc->sc_ih == NULL) { 221 aprint_error_dev(self, "failed to establish interrupt on %s\n", 222 intrstr); 223 return; 224 } 225 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 226 227 tegra_pcie_setup(sc); 228 229 tegra_pcie_init(&sc->sc_pc, sc); 230 231 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 232 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 233 NULL, 0, EX_NOWAIT); 234 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 235 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 236 NULL, 0, EX_NOWAIT); 237 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 238 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 239 NULL, 0, EX_NOWAIT); 240 241 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 242 arm_dcache_align); 243 244 extent_destroy(ioext); 245 extent_destroy(memext); 246 extent_destroy(pmemext); 247 248 if (error) { 249 aprint_error_dev(self, "configuration failed (%d)\n", 250 error); 251 return; 252 } 253 254 tegra_pcie_enable(sc); 255 256 tegra_pcie_enable_ports(sc); 257 258 memset(&pba, 0, sizeof(pba)); 259 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 260 PCI_FLAGS_MRM_OKAY | 261 PCI_FLAGS_MWI_OKAY | 262 PCI_FLAGS_MEM_OKAY | 263 PCI_FLAGS_IO_OKAY; 264 pba.pba_iot = sc->sc_bst; 265 pba.pba_memt = sc->sc_bst; 266 pba.pba_dmat = sc->sc_dmat; 267 pba.pba_pc = &sc->sc_pc; 268 pba.pba_bus = 0; 269 270 config_found_ia(self, "pcibus", &pba, pcibusprint); 271 } 272 273 static int 274 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 275 { 276 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 277 AFI_MSG_REG); 278 struct tegra_pcie_ih *pcie_ih; 279 int rv = 0; 280 281 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 282 mutex_enter(&sc->sc_lock); 283 const u_int lastgen = sc->sc_intrgen; 284 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 285 int (*callback)(void *) = pcie_ih->ih_callback; 286 void *arg = pcie_ih->ih_arg; 287 const int mpsafe = pcie_ih->ih_mpsafe; 288 mutex_exit(&sc->sc_lock); 289 290 if (!mpsafe) 291 KERNEL_LOCK(1, curlwp); 292 rv += callback(arg); 293 if (!mpsafe) 294 KERNEL_UNLOCK_ONE(curlwp); 295 296 mutex_enter(&sc->sc_lock); 297 if (lastgen != sc->sc_intrgen) 298 break; 299 } 300 mutex_exit(&sc->sc_lock); 301 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 302 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 303 msg); 304 } else { 305 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 306 rv = 1; 307 } 308 309 return rv; 310 } 311 312 static int 313 tegra_pcie_intr(void *priv) 314 { 315 struct tegra_pcie_softc *sc = priv; 316 int rv; 317 318 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 319 AFI_INTR_CODE_REG); 320 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 321 AFI_INTR_SIGNATURE_REG); 322 323 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 324 case AFI_INTR_CODE_SM_MSG: 325 rv = tegra_pcie_legacy_intr(sc); 326 break; 327 default: 328 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 329 code, sig); 330 rv = 1; 331 break; 332 } 333 334 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 335 336 return rv; 337 } 338 339 static void 340 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 341 { 342 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 343 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 344 struct fdtbus_reset *rst; 345 struct clk *clk; 346 int n; 347 348 for (n = 0; n < __arraycount(clock_names); n++) { 349 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 350 if (clk == NULL || clk_enable(clk) != 0) 351 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 352 clock_names[n]); 353 } 354 355 for (n = 0; n < __arraycount(reset_names); n++) { 356 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 357 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 358 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 359 reset_names[n]); 360 } 361 } 362 363 #if 0 364 static void 365 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 366 { 367 uint32_t val; 368 369 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 370 val &= ~AFI_PEXn_CTRL_RST_L; 371 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 372 373 delay(2000); 374 375 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 376 val |= AFI_PEXn_CTRL_RST_L; 377 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 378 } 379 #endif 380 381 static void 382 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 383 { 384 struct fdtbus_phy *phy; 385 const u_int *data; 386 int child, len, n; 387 uint32_t val; 388 389 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 390 if (!fdtbus_status_okay(child)) 391 continue; 392 393 /* Enable PHYs */ 394 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 395 if (fdtbus_phy_enable(phy, true) != 0) 396 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 397 fdtbus_get_string(child, "name"), n); 398 399 data = fdtbus_get_prop(child, "reg", &len); 400 if (data == NULL || len < 4) 401 continue; 402 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 403 404 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 405 val |= AFI_PEXn_CTRL_CLKREQ_EN; 406 val |= AFI_PEXn_CTRL_REFCLK_EN; 407 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 408 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 409 410 #if 0 411 tegra_pcie_reset_port(sc, index); 412 #endif 413 414 } 415 } 416 417 static void 418 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 419 { 420 uint32_t val, cfg, lanes; 421 int child, len; 422 const u_int *data; 423 size_t i; 424 425 /* Enable PLLE control */ 426 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 427 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 428 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 429 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 430 431 /* Disable PEX clock bias pad power down */ 432 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 433 434 /* Configure PCIE mode and enable ports */ 435 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 436 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 437 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 438 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 439 440 lanes = 0; 441 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 442 if (!fdtbus_status_okay(child)) 443 continue; 444 data = fdtbus_get_prop(child, "reg", &len); 445 if (data == NULL || len < 4) 446 continue; 447 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 448 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 449 continue; 450 lanes |= (val << (index << 3)); 451 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 452 } 453 454 switch (lanes) { 455 case 0x0104: 456 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 457 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 458 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 459 break; 460 case 0x0102: 461 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 462 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 463 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 464 break; 465 } 466 467 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 468 469 /* Configure refclk pad */ 470 const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL }; 471 if (of_match_compatible(sc->sc_phandle, tegra124_compat)) 472 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 473 0x44ac44ac); 474 const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL }; 475 if (of_match_compatible(sc->sc_phandle, tegra210_compat)) 476 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 477 0x90b890b8); 478 479 /* 480 * Map PCI address spaces into ARM address space via 481 * HyperTransport-like "FPCI". 482 */ 483 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 484 /* 485 * === BEWARE === 486 * 487 * We depend on our TEGRA_PCIE_IO window overlaping the 488 * TEGRA_PCIE_A1 window to allow us to use the same 489 * bus_space_tag for both PCI IO and Memory spaces. 490 * 491 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 492 * mapping for 0x0000000-0x1ffffff of PCI IO space. 493 */ 494 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 495 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 496 497 /* HyperTransport Technology Type 1 Address Format */ 498 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 499 0xfdff000000 >> 8 | 0, }, 500 501 /* 1:1 MMIO mapping */ 502 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 503 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 504 505 /* Extended HyperTransport Technology Type 1 Address Format */ 506 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 507 0xfe10000000 >> 8 | 0, }, 508 509 /* 1:1 prefetchable MMIO mapping */ 510 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 511 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 512 }; 513 514 for (i = 0; i < AFI_AXI_NBAR; i++) { 515 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 516 AFI_AXI_BARi_SZ(i), 0); 517 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 518 AFI_AXI_BARi_START(i), 0); 519 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 520 AFI_FPCI_BARi(i), 0); 521 } 522 523 for (i = 0; i < __arraycount(pcie_init_table); i++) { 524 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 525 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 526 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 527 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 528 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 529 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 530 } 531 } 532 533 static void 534 tegra_pcie_enable(struct tegra_pcie_softc *sc) 535 { 536 /* disable MSI */ 537 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 538 AFI_MSI_BAR_SZ_REG, 0); 539 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 540 AFI_MSI_FPCI_BAR_ST_REG, 0); 541 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 542 AFI_MSI_AXI_BAR_ST_REG, 0); 543 544 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 545 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 546 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 547 AFI_AFI_INTR_ENABLE_REG, 0); 548 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 549 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 550 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 551 } 552 553 static void 554 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 555 uint frg) 556 { 557 bus_addr_t a; 558 559 KASSERT(bus >= 1); 560 KASSERT(bus < TEGRA_PCIE_NBUS); 561 KASSERT(frg < TEGRA_PCIE_ECFB); 562 563 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 564 device_printf(sc->sc_dev, "bus %u fragment %#x already " 565 "mapped\n", bus, frg); 566 return; 567 } 568 569 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 570 if (bus_space_map(sc->sc_bst, a, 1 << 16, 571 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, 572 &sc->sc_bsh_extc[bus-1][frg]) != 0) 573 device_printf(sc->sc_dev, "couldn't map PCIE " 574 "configuration for bus %u fragment %#x", bus, frg); 575 } 576 577 /* map non-non-extended configuration space for full bus range */ 578 static void 579 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 580 { 581 uint i; 582 583 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 584 tegra_pcie_conf_frag_map(sc, bus, i); 585 } 586 } 587 588 /* map non-extended configuration space for full bus range */ 589 static void 590 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 591 { 592 uint b; 593 594 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 595 tegra_pcie_conf_frag_map(sc, b, 0); 596 } 597 } 598 599 void 600 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 601 { 602 pc->pc_conf_v = priv; 603 pc->pc_attach_hook = tegra_pcie_attach_hook; 604 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 605 pc->pc_make_tag = tegra_pcie_make_tag; 606 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 607 pc->pc_conf_read = tegra_pcie_conf_read; 608 pc->pc_conf_write = tegra_pcie_conf_write; 609 pc->pc_conf_hook = tegra_pcie_conf_hook; 610 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 611 612 pc->pc_intr_v = priv; 613 pc->pc_intr_map = tegra_pcie_intr_map; 614 pc->pc_intr_string = tegra_pcie_intr_string; 615 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 616 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 617 pc->pc_intr_establish = tegra_pcie_intr_establish; 618 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 619 } 620 621 static void 622 tegra_pcie_attach_hook(device_t parent, device_t self, 623 struct pcibus_attach_args *pba) 624 { 625 const pci_chipset_tag_t pc = pba->pba_pc; 626 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 627 628 if (pba->pba_bus >= 1) { 629 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 630 } 631 } 632 633 static int 634 tegra_pcie_bus_maxdevs(void *v, int busno) 635 { 636 return busno == 0 ? 2 : 32; 637 } 638 639 static pcitag_t 640 tegra_pcie_make_tag(void *v, int b, int d, int f) 641 { 642 return (b << 16) | (d << 11) | (f << 8); 643 } 644 645 static void 646 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 647 { 648 if (bp) 649 *bp = (tag >> 16) & 0xff; 650 if (dp) 651 *dp = (tag >> 11) & 0x1f; 652 if (fp) 653 *fp = (tag >> 8) & 0x7; 654 } 655 656 static pcireg_t 657 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 658 { 659 struct tegra_pcie_softc *sc = v; 660 bus_space_handle_t bsh; 661 int b, d, f; 662 u_int reg; 663 664 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 665 return (pcireg_t) -1; 666 667 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 668 669 if (b >= TEGRA_PCIE_NBUS) 670 return (pcireg_t) -1; 671 672 if (b == 0) { 673 if (d >= 2 || f != 0) 674 return (pcireg_t) -1; 675 reg = d * 0x1000 + offset; 676 bsh = sc->sc_bsh_rpconf; 677 } else { 678 reg = (d << 11) | (f << 8) | (offset & 0xff); 679 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 680 if (bsh == 0) 681 return (pcireg_t) -1; 682 } 683 684 return bus_space_read_4(sc->sc_bst, bsh, reg); 685 } 686 687 static void 688 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 689 { 690 struct tegra_pcie_softc *sc = v; 691 bus_space_handle_t bsh; 692 int b, d, f; 693 u_int reg; 694 695 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 696 return; 697 698 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 699 700 if (b >= TEGRA_PCIE_NBUS) 701 return; 702 703 if (b == 0) { 704 if (d >= 2 || f != 0) 705 return; 706 reg = d * 0x1000 + offset; 707 bsh = sc->sc_bsh_rpconf; 708 } else { 709 reg = (d << 11) | (f << 8) | (offset & 0xff); 710 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 711 if (bsh == 0) 712 return; 713 } 714 715 bus_space_write_4(sc->sc_bst, bsh, reg, val); 716 } 717 718 static int 719 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 720 { 721 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 722 } 723 724 static void 725 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 726 int *ilinep) 727 { 728 *ilinep = 5; 729 } 730 731 static int 732 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 733 { 734 if (pa->pa_intrpin == 0) 735 return EINVAL; 736 *ih = pa->pa_intrpin; 737 return 0; 738 } 739 740 static const char * 741 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 742 { 743 struct tegra_pcie_softc *sc = v; 744 745 if (ih == PCI_INTERRUPT_PIN_NONE) 746 return NULL; 747 748 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 749 return NULL; 750 751 return buf; 752 } 753 754 const struct evcnt * 755 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 756 { 757 return NULL; 758 } 759 760 static int 761 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 762 { 763 switch (attr) { 764 case PCI_INTR_MPSAFE: 765 if (data) 766 *ih |= IH_MPSAFE; 767 else 768 *ih &= ~IH_MPSAFE; 769 return 0; 770 default: 771 return ENODEV; 772 } 773 } 774 775 static void * 776 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 777 int (*callback)(void *), void *arg, const char *xname) 778 { 779 struct tegra_pcie_softc *sc = v; 780 struct tegra_pcie_ih *pcie_ih; 781 782 if (ih == 0) 783 return NULL; 784 785 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 786 pcie_ih->ih_callback = callback; 787 pcie_ih->ih_arg = arg; 788 pcie_ih->ih_ipl = ipl; 789 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 790 791 mutex_enter(&sc->sc_lock); 792 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 793 sc->sc_intrgen++; 794 mutex_exit(&sc->sc_lock); 795 796 return pcie_ih; 797 } 798 799 static void 800 tegra_pcie_intr_disestablish(void *v, void *vih) 801 { 802 struct tegra_pcie_softc *sc = v; 803 struct tegra_pcie_ih *pcie_ih = vih; 804 805 mutex_enter(&sc->sc_lock); 806 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 807 mutex_exit(&sc->sc_lock); 808 809 kmem_free(pcie_ih, sizeof(*pcie_ih)); 810 } 811