1 /* $NetBSD: tegra_pcie.c,v 1.24 2018/04/01 04:35:04 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.24 2018/04/01 04:35:04 ryo Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <arm/nvidia/tegra_reg.h> 52 #include <arm/nvidia/tegra_pciereg.h> 53 #include <arm/nvidia/tegra_pmcreg.h> 54 #include <arm/nvidia/tegra_var.h> 55 56 #include <dev/fdt/fdtvar.h> 57 58 /* Interrupt handle flags */ 59 #define IH_MPSAFE 0x80000000 60 61 static int tegra_pcie_match(device_t, cfdata_t, void *); 62 static void tegra_pcie_attach(device_t, device_t, void *); 63 64 #define TEGRA_PCIE_NBUS 256 65 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 66 67 struct tegra_pcie_ih { 68 int (*ih_callback)(void *); 69 void *ih_arg; 70 int ih_ipl; 71 int ih_mpsafe; 72 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 73 }; 74 75 struct tegra_pcie_softc { 76 device_t sc_dev; 77 bus_dma_tag_t sc_dmat; 78 bus_space_tag_t sc_bst; 79 bus_space_handle_t sc_bsh_afi; 80 bus_space_handle_t sc_bsh_pads; 81 bus_space_handle_t sc_bsh_rpconf; 82 int sc_phandle; 83 84 struct arm32_pci_chipset sc_pc; 85 86 void *sc_ih; 87 88 kmutex_t sc_lock; 89 90 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 91 u_int sc_intrgen; 92 93 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 94 }; 95 96 static int tegra_pcie_intr(void *); 97 static void tegra_pcie_init(pci_chipset_tag_t, void *); 98 static void tegra_pcie_enable(struct tegra_pcie_softc *); 99 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 100 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 101 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 102 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 103 uint, uint); 104 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 105 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 106 107 static void tegra_pcie_attach_hook(device_t, device_t, 108 struct pcibus_attach_args *); 109 static int tegra_pcie_bus_maxdevs(void *, int); 110 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 111 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 112 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 113 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 114 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 115 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 116 117 static int tegra_pcie_intr_map(const struct pci_attach_args *, 118 pci_intr_handle_t *); 119 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 120 char *, size_t); 121 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 122 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 123 uint64_t); 124 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 125 int, int (*)(void *), void *); 126 static void tegra_pcie_intr_disestablish(void *, void *); 127 128 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 129 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 130 131 static int 132 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 133 { 134 const char * const compatible[] = { 135 "nvidia,tegra210-pcie", 136 "nvidia,tegra124-pcie", 137 NULL 138 }; 139 struct fdt_attach_args * const faa = aux; 140 141 return of_match_compatible(faa->faa_phandle, compatible); 142 } 143 144 static void 145 tegra_pcie_attach(device_t parent, device_t self, void *aux) 146 { 147 struct tegra_pcie_softc * const sc = device_private(self); 148 struct fdt_attach_args * const faa = aux; 149 struct extent *ioext, *memext, *pmemext; 150 struct pcibus_attach_args pba; 151 bus_addr_t afi_addr, cs_addr, pads_addr; 152 bus_size_t afi_size, cs_size, pads_size; 153 char intrstr[128]; 154 int error; 155 156 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 157 aprint_error(": couldn't get afi registers\n"); 158 return; 159 } 160 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 161 aprint_error(": couldn't get pads registers\n"); 162 return; 163 } 164 #if notyet 165 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 166 aprint_error(": couldn't get cs registers\n"); 167 return; 168 } 169 #else 170 cs_addr = TEGRA_PCIE_RPCONF_BASE; 171 cs_size = TEGRA_PCIE_RPCONF_SIZE; 172 #endif 173 174 sc->sc_dev = self; 175 sc->sc_dmat = faa->faa_dmat; 176 sc->sc_bst = faa->faa_bst; 177 sc->sc_phandle = faa->faa_phandle; 178 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 179 &sc->sc_bsh_afi); 180 if (error) { 181 aprint_error(": couldn't map afi registers: %d\n", error); 182 return; 183 } 184 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 185 &sc->sc_bsh_pads); 186 if (error) { 187 aprint_error(": couldn't map afi registers: %d\n", error); 188 return; 189 } 190 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 191 &sc->sc_bsh_rpconf); 192 if (error) { 193 aprint_error(": couldn't map cs registers: %d\n", error); 194 return; 195 } 196 197 tegra_pcie_conf_map_buses(sc); 198 199 TAILQ_INIT(&sc->sc_intrs); 200 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 201 202 aprint_naive("\n"); 203 aprint_normal(": PCIE\n"); 204 205 tegra_pmc_power(PMC_PARTID_PCX, true); 206 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 207 208 tegra_pcie_enable_clocks(sc); 209 210 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 211 aprint_error_dev(self, "failed to decode interrupt\n"); 212 return; 213 } 214 215 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 216 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 217 if (sc->sc_ih == NULL) { 218 aprint_error_dev(self, "failed to establish interrupt on %s\n", 219 intrstr); 220 return; 221 } 222 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 223 224 tegra_pcie_setup(sc); 225 226 tegra_pcie_init(&sc->sc_pc, sc); 227 228 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 229 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 230 NULL, 0, EX_NOWAIT); 231 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 232 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 233 NULL, 0, EX_NOWAIT); 234 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 235 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 236 NULL, 0, EX_NOWAIT); 237 238 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 239 arm_dcache_align); 240 241 extent_destroy(ioext); 242 extent_destroy(memext); 243 extent_destroy(pmemext); 244 245 if (error) { 246 aprint_error_dev(self, "configuration failed (%d)\n", 247 error); 248 return; 249 } 250 251 tegra_pcie_enable(sc); 252 253 tegra_pcie_enable_ports(sc); 254 255 memset(&pba, 0, sizeof(pba)); 256 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 257 PCI_FLAGS_MRM_OKAY | 258 PCI_FLAGS_MWI_OKAY | 259 PCI_FLAGS_MEM_OKAY | 260 PCI_FLAGS_IO_OKAY; 261 pba.pba_iot = sc->sc_bst; 262 pba.pba_memt = sc->sc_bst; 263 pba.pba_dmat = sc->sc_dmat; 264 pba.pba_pc = &sc->sc_pc; 265 pba.pba_bus = 0; 266 267 config_found_ia(self, "pcibus", &pba, pcibusprint); 268 } 269 270 static int 271 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 272 { 273 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 274 AFI_MSG_REG); 275 struct tegra_pcie_ih *pcie_ih; 276 int rv = 0; 277 278 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 279 mutex_enter(&sc->sc_lock); 280 const u_int lastgen = sc->sc_intrgen; 281 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 282 int (*callback)(void *) = pcie_ih->ih_callback; 283 void *arg = pcie_ih->ih_arg; 284 const int mpsafe = pcie_ih->ih_mpsafe; 285 mutex_exit(&sc->sc_lock); 286 287 if (!mpsafe) 288 KERNEL_LOCK(1, curlwp); 289 rv += callback(arg); 290 if (!mpsafe) 291 KERNEL_UNLOCK_ONE(curlwp); 292 293 mutex_enter(&sc->sc_lock); 294 if (lastgen != sc->sc_intrgen) 295 break; 296 } 297 mutex_exit(&sc->sc_lock); 298 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 299 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 300 msg); 301 } else { 302 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 303 rv = 1; 304 } 305 306 return rv; 307 } 308 309 static int 310 tegra_pcie_intr(void *priv) 311 { 312 struct tegra_pcie_softc *sc = priv; 313 int rv; 314 315 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 316 AFI_INTR_CODE_REG); 317 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 318 AFI_INTR_SIGNATURE_REG); 319 320 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 321 case AFI_INTR_CODE_SM_MSG: 322 rv = tegra_pcie_legacy_intr(sc); 323 break; 324 default: 325 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 326 code, sig); 327 rv = 1; 328 break; 329 } 330 331 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 332 333 return rv; 334 } 335 336 static void 337 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 338 { 339 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 340 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 341 struct fdtbus_reset *rst; 342 struct clk *clk; 343 int n; 344 345 for (n = 0; n < __arraycount(clock_names); n++) { 346 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 347 if (clk == NULL || clk_enable(clk) != 0) 348 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 349 clock_names[n]); 350 } 351 352 for (n = 0; n < __arraycount(reset_names); n++) { 353 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 354 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 355 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 356 reset_names[n]); 357 } 358 } 359 360 #if 0 361 static void 362 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 363 { 364 uint32_t val; 365 366 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 367 val &= ~AFI_PEXn_CTRL_RST_L; 368 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 369 370 delay(2000); 371 372 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 373 val |= AFI_PEXn_CTRL_RST_L; 374 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 375 } 376 #endif 377 378 static void 379 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 380 { 381 struct fdtbus_phy *phy; 382 const u_int *data; 383 int child, len, n; 384 uint32_t val; 385 386 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 387 if (!fdtbus_status_okay(child)) 388 continue; 389 390 /* Enable PHYs */ 391 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 392 if (fdtbus_phy_enable(phy, true) != 0) 393 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 394 fdtbus_get_string(child, "name"), n); 395 396 data = fdtbus_get_prop(child, "reg", &len); 397 if (data == NULL || len < 4) 398 continue; 399 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 400 401 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 402 val |= AFI_PEXn_CTRL_CLKREQ_EN; 403 val |= AFI_PEXn_CTRL_REFCLK_EN; 404 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 405 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 406 407 #if 0 408 tegra_pcie_reset_port(sc, index); 409 #endif 410 411 } 412 } 413 414 static void 415 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 416 { 417 uint32_t val, cfg, lanes; 418 int child, len; 419 const u_int *data; 420 size_t i; 421 422 /* Enable PLLE control */ 423 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 424 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 425 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 426 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 427 428 /* Disable PEX clock bias pad power down */ 429 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 430 431 /* Configure PCIE mode and enable ports */ 432 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 433 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 434 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 435 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 436 437 lanes = 0; 438 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 439 if (!fdtbus_status_okay(child)) 440 continue; 441 data = fdtbus_get_prop(child, "reg", &len); 442 if (data == NULL || len < 4) 443 continue; 444 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 445 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 446 continue; 447 lanes |= (val << (index << 3)); 448 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 449 } 450 451 switch (lanes) { 452 case 0x0104: 453 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 454 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 455 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 456 break; 457 case 0x0102: 458 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 459 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 460 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 461 break; 462 } 463 464 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 465 466 /* Configure refclk pad */ 467 const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL }; 468 if (of_match_compatible(sc->sc_phandle, tegra124_compat)) 469 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 470 0x44ac44ac); 471 const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL }; 472 if (of_match_compatible(sc->sc_phandle, tegra210_compat)) 473 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 474 0x90b890b8); 475 476 /* 477 * Map PCI address spaces into ARM address space via 478 * HyperTransport-like "FPCI". 479 */ 480 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 481 /* 482 * === BEWARE === 483 * 484 * We depend on our TEGRA_PCIE_IO window overlaping the 485 * TEGRA_PCIE_A1 window to allow us to use the same 486 * bus_space_tag for both PCI IO and Memory spaces. 487 * 488 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 489 * mapping for 0x0000000-0x1ffffff of PCI IO space. 490 */ 491 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 492 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 493 494 /* HyperTransport Technology Type 1 Address Format */ 495 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 496 0xfdff000000 >> 8 | 0, }, 497 498 /* 1:1 MMIO mapping */ 499 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 500 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 501 502 /* Extended HyperTransport Technology Type 1 Address Format */ 503 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 504 0xfe10000000 >> 8 | 0, }, 505 506 /* 1:1 prefetchable MMIO mapping */ 507 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 508 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 509 }; 510 511 for (i = 0; i < AFI_AXI_NBAR; i++) { 512 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 513 AFI_AXI_BARi_SZ(i), 0); 514 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 515 AFI_AXI_BARi_START(i), 0); 516 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 517 AFI_FPCI_BARi(i), 0); 518 } 519 520 for (i = 0; i < __arraycount(pcie_init_table); i++) { 521 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 522 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 523 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 524 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 525 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 526 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 527 } 528 } 529 530 static void 531 tegra_pcie_enable(struct tegra_pcie_softc *sc) 532 { 533 /* disable MSI */ 534 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 535 AFI_MSI_BAR_SZ_REG, 0); 536 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 537 AFI_MSI_FPCI_BAR_ST_REG, 0); 538 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 539 AFI_MSI_AXI_BAR_ST_REG, 0); 540 541 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 542 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 543 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 544 AFI_AFI_INTR_ENABLE_REG, 0); 545 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 546 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 547 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 548 } 549 550 static void 551 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 552 uint frg) 553 { 554 bus_addr_t a; 555 556 KASSERT(bus >= 1); 557 KASSERT(bus < TEGRA_PCIE_NBUS); 558 KASSERT(frg < TEGRA_PCIE_ECFB); 559 560 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 561 device_printf(sc->sc_dev, "bus %u fragment %#x already " 562 "mapped\n", bus, frg); 563 return; 564 } 565 566 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 567 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 568 &sc->sc_bsh_extc[bus-1][frg]) != 0) 569 device_printf(sc->sc_dev, "couldn't map PCIE " 570 "configuration for bus %u fragment %#x", bus, frg); 571 } 572 573 /* map non-non-extended configuration space for full bus range */ 574 static void 575 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 576 { 577 uint i; 578 579 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 580 tegra_pcie_conf_frag_map(sc, bus, i); 581 } 582 } 583 584 /* map non-extended configuration space for full bus range */ 585 static void 586 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 587 { 588 uint b; 589 590 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 591 tegra_pcie_conf_frag_map(sc, b, 0); 592 } 593 } 594 595 void 596 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 597 { 598 pc->pc_conf_v = priv; 599 pc->pc_attach_hook = tegra_pcie_attach_hook; 600 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 601 pc->pc_make_tag = tegra_pcie_make_tag; 602 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 603 pc->pc_conf_read = tegra_pcie_conf_read; 604 pc->pc_conf_write = tegra_pcie_conf_write; 605 pc->pc_conf_hook = tegra_pcie_conf_hook; 606 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 607 608 pc->pc_intr_v = priv; 609 pc->pc_intr_map = tegra_pcie_intr_map; 610 pc->pc_intr_string = tegra_pcie_intr_string; 611 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 612 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 613 pc->pc_intr_establish = tegra_pcie_intr_establish; 614 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 615 } 616 617 static void 618 tegra_pcie_attach_hook(device_t parent, device_t self, 619 struct pcibus_attach_args *pba) 620 { 621 const pci_chipset_tag_t pc = pba->pba_pc; 622 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 623 624 if (pba->pba_bus >= 1) { 625 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 626 } 627 } 628 629 static int 630 tegra_pcie_bus_maxdevs(void *v, int busno) 631 { 632 return busno == 0 ? 2 : 32; 633 } 634 635 static pcitag_t 636 tegra_pcie_make_tag(void *v, int b, int d, int f) 637 { 638 return (b << 16) | (d << 11) | (f << 8); 639 } 640 641 static void 642 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 643 { 644 if (bp) 645 *bp = (tag >> 16) & 0xff; 646 if (dp) 647 *dp = (tag >> 11) & 0x1f; 648 if (fp) 649 *fp = (tag >> 8) & 0x7; 650 } 651 652 static pcireg_t 653 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 654 { 655 struct tegra_pcie_softc *sc = v; 656 bus_space_handle_t bsh; 657 int b, d, f; 658 u_int reg; 659 660 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 661 return (pcireg_t) -1; 662 663 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 664 665 if (b >= TEGRA_PCIE_NBUS) 666 return (pcireg_t) -1; 667 668 if (b == 0) { 669 if (d >= 2 || f != 0) 670 return (pcireg_t) -1; 671 reg = d * 0x1000 + offset; 672 bsh = sc->sc_bsh_rpconf; 673 } else { 674 reg = (d << 11) | (f << 8) | (offset & 0xff); 675 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 676 if (bsh == 0) 677 return (pcireg_t) -1; 678 } 679 680 return bus_space_read_4(sc->sc_bst, bsh, reg); 681 } 682 683 static void 684 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 685 { 686 struct tegra_pcie_softc *sc = v; 687 bus_space_handle_t bsh; 688 int b, d, f; 689 u_int reg; 690 691 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 692 return; 693 694 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 695 696 if (b >= TEGRA_PCIE_NBUS) 697 return; 698 699 if (b == 0) { 700 if (d >= 2 || f != 0) 701 return; 702 reg = d * 0x1000 + offset; 703 bsh = sc->sc_bsh_rpconf; 704 } else { 705 reg = (d << 11) | (f << 8) | (offset & 0xff); 706 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 707 if (bsh == 0) 708 return; 709 } 710 711 bus_space_write_4(sc->sc_bst, bsh, reg, val); 712 } 713 714 static int 715 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 716 { 717 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 718 } 719 720 static void 721 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 722 int *ilinep) 723 { 724 *ilinep = 5; 725 } 726 727 static int 728 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 729 { 730 if (pa->pa_intrpin == 0) 731 return EINVAL; 732 *ih = pa->pa_intrpin; 733 return 0; 734 } 735 736 static const char * 737 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 738 { 739 struct tegra_pcie_softc *sc = v; 740 741 if (ih == PCI_INTERRUPT_PIN_NONE) 742 return NULL; 743 744 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 745 return NULL; 746 747 return buf; 748 } 749 750 const struct evcnt * 751 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 752 { 753 return NULL; 754 } 755 756 static int 757 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 758 { 759 switch (attr) { 760 case PCI_INTR_MPSAFE: 761 if (data) 762 *ih |= IH_MPSAFE; 763 else 764 *ih &= ~IH_MPSAFE; 765 return 0; 766 default: 767 return ENODEV; 768 } 769 } 770 771 static void * 772 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 773 int (*callback)(void *), void *arg) 774 { 775 struct tegra_pcie_softc *sc = v; 776 struct tegra_pcie_ih *pcie_ih; 777 778 if (ih == 0) 779 return NULL; 780 781 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 782 pcie_ih->ih_callback = callback; 783 pcie_ih->ih_arg = arg; 784 pcie_ih->ih_ipl = ipl; 785 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 786 787 mutex_enter(&sc->sc_lock); 788 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 789 sc->sc_intrgen++; 790 mutex_exit(&sc->sc_lock); 791 792 return pcie_ih; 793 } 794 795 static void 796 tegra_pcie_intr_disestablish(void *v, void *vih) 797 { 798 struct tegra_pcie_softc *sc = v; 799 struct tegra_pcie_ih *pcie_ih = vih; 800 801 mutex_enter(&sc->sc_lock); 802 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 803 mutex_exit(&sc->sc_lock); 804 805 kmem_free(pcie_ih, sizeof(*pcie_ih)); 806 } 807