1 /* $NetBSD: tegra_pcie.c,v 1.38 2021/05/12 04:07:34 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.38 2021/05/12 04:07:34 thorpej Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kmem.h> 38 #include <sys/kernel.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <arm/nvidia/tegra_reg.h> 53 #include <arm/nvidia/tegra_pciereg.h> 54 #include <arm/nvidia/tegra_pmcreg.h> 55 #include <arm/nvidia/tegra_var.h> 56 57 #include <dev/fdt/fdtvar.h> 58 59 /* Interrupt handle flags */ 60 #define IH_MPSAFE 0x80000000 61 62 static int tegra_pcie_match(device_t, cfdata_t, void *); 63 static void tegra_pcie_attach(device_t, device_t, void *); 64 65 #define TEGRA_PCIE_NBUS 256 66 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 67 68 enum tegra_pcie_type { 69 TEGRA_PCIE_124 = 0, 70 TEGRA_PCIE_210 = 1, 71 }; 72 73 struct tegra_pcie_ih { 74 int (*ih_callback)(void *); 75 void *ih_arg; 76 int ih_ipl; 77 int ih_mpsafe; 78 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 79 }; 80 81 struct tegra_pcie_softc { 82 device_t sc_dev; 83 bus_dma_tag_t sc_dmat; 84 bus_space_tag_t sc_bst; 85 bus_space_handle_t sc_bsh_afi; 86 bus_space_handle_t sc_bsh_pads; 87 bus_space_handle_t sc_bsh_rpconf; 88 int sc_phandle; 89 enum tegra_pcie_type sc_type; 90 91 struct arm32_pci_chipset sc_pc; 92 93 void *sc_ih; 94 95 kmutex_t sc_lock; 96 97 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 98 u_int sc_intrgen; 99 100 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 101 }; 102 103 static int tegra_pcie_intr(void *); 104 static void tegra_pcie_init(pci_chipset_tag_t, void *); 105 static void tegra_pcie_enable(struct tegra_pcie_softc *); 106 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 107 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 108 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 109 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 110 uint, uint); 111 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 112 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 113 114 static void tegra_pcie_attach_hook(device_t, device_t, 115 struct pcibus_attach_args *); 116 static int tegra_pcie_bus_maxdevs(void *, int); 117 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 118 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 119 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 120 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 121 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 122 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 123 124 static int tegra_pcie_intr_map(const struct pci_attach_args *, 125 pci_intr_handle_t *); 126 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 127 char *, size_t); 128 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 129 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 130 uint64_t); 131 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 132 int, int (*)(void *), void *, 133 const char *); 134 static void tegra_pcie_intr_disestablish(void *, void *); 135 136 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 137 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 138 139 static const struct device_compatible_entry compat_data[] = { 140 { .compat = "nvidia,tegra210-pcie", .value = TEGRA_PCIE_210 }, 141 { .compat = "nvidia,tegra124-pcie", .value = TEGRA_PCIE_124 }, 142 DEVICE_COMPAT_EOL 143 }; 144 145 static int 146 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 147 { 148 struct fdt_attach_args * const faa = aux; 149 150 return of_compatible_match(faa->faa_phandle, compat_data); 151 } 152 153 static void 154 tegra_pcie_attach(device_t parent, device_t self, void *aux) 155 { 156 struct tegra_pcie_softc * const sc = device_private(self); 157 struct fdt_attach_args * const faa = aux; 158 const struct device_compatible_entry *dce; 159 struct pciconf_resources *pcires; 160 struct pcibus_attach_args pba; 161 bus_addr_t afi_addr, cs_addr, pads_addr; 162 bus_size_t afi_size, cs_size, pads_size; 163 char intrstr[128]; 164 int error; 165 166 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 167 aprint_error(": couldn't get afi registers\n"); 168 return; 169 } 170 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 171 aprint_error(": couldn't get pads registers\n"); 172 return; 173 } 174 #if notyet 175 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 176 aprint_error(": couldn't get cs registers\n"); 177 return; 178 } 179 #else 180 cs_addr = TEGRA_PCIE_RPCONF_BASE; 181 cs_size = TEGRA_PCIE_RPCONF_SIZE; 182 #endif 183 184 sc->sc_dev = self; 185 sc->sc_dmat = faa->faa_dmat; 186 sc->sc_bst = faa->faa_bst; 187 sc->sc_phandle = faa->faa_phandle; 188 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 189 &sc->sc_bsh_afi); 190 if (error) { 191 aprint_error(": couldn't map afi registers: %d\n", error); 192 return; 193 } 194 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 195 &sc->sc_bsh_pads); 196 if (error) { 197 aprint_error(": couldn't map pads registers: %d\n", error); 198 return; 199 } 200 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 201 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh_rpconf); 202 if (error) { 203 aprint_error(": couldn't map cs registers: %d\n", error); 204 return; 205 } 206 207 dce = of_compatible_lookup(faa->faa_phandle, compat_data); 208 KASSERT(dce != NULL); 209 sc->sc_type = dce->value; 210 211 tegra_pcie_conf_map_buses(sc); 212 213 TAILQ_INIT(&sc->sc_intrs); 214 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 215 216 aprint_naive("\n"); 217 aprint_normal(": PCIE\n"); 218 219 tegra_pmc_power(PMC_PARTID_PCX, true); 220 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 221 222 tegra_pcie_enable_clocks(sc); 223 224 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 225 aprint_error_dev(self, "failed to decode interrupt\n"); 226 return; 227 } 228 229 sc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_VM, 230 FDT_INTR_MPSAFE, tegra_pcie_intr, sc, device_xname(self)); 231 if (sc->sc_ih == NULL) { 232 aprint_error_dev(self, "failed to establish interrupt on %s\n", 233 intrstr); 234 return; 235 } 236 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 237 238 tegra_pcie_setup(sc); 239 240 tegra_pcie_init(&sc->sc_pc, sc); 241 242 pcires = pciconf_resource_init(); 243 244 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 245 TEGRA_PCIE_IO_BASE, TEGRA_PCIE_IO_SIZE); 246 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 247 TEGRA_PCIE_MEM_BASE, TEGRA_PCIE_MEM_SIZE); 248 pciconf_resource_add(pcires, PCICONF_RESOURCE_PREFETCHABLE_MEM, 249 TEGRA_PCIE_PMEM_BASE, TEGRA_PCIE_PMEM_SIZE); 250 251 error = pci_configure_bus(&sc->sc_pc, pcires, 0, 252 arm_dcache_align); 253 254 pciconf_resource_fini(pcires); 255 256 if (error) { 257 aprint_error_dev(self, "configuration failed (%d)\n", 258 error); 259 return; 260 } 261 262 tegra_pcie_enable(sc); 263 264 tegra_pcie_enable_ports(sc); 265 266 memset(&pba, 0, sizeof(pba)); 267 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 268 PCI_FLAGS_MRM_OKAY | 269 PCI_FLAGS_MWI_OKAY | 270 PCI_FLAGS_MEM_OKAY | 271 PCI_FLAGS_IO_OKAY; 272 pba.pba_iot = sc->sc_bst; 273 pba.pba_memt = sc->sc_bst; 274 pba.pba_dmat = sc->sc_dmat; 275 pba.pba_pc = &sc->sc_pc; 276 pba.pba_bus = 0; 277 278 config_found(self, &pba, pcibusprint, 279 CFARG_DEVHANDLE, device_handle(self), 280 CFARG_EOL); 281 } 282 283 static int 284 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 285 { 286 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 287 AFI_MSG_REG); 288 struct tegra_pcie_ih *pcie_ih; 289 int rv = 0; 290 291 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 292 mutex_enter(&sc->sc_lock); 293 const u_int lastgen = sc->sc_intrgen; 294 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 295 int (*callback)(void *) = pcie_ih->ih_callback; 296 void *arg = pcie_ih->ih_arg; 297 const int mpsafe = pcie_ih->ih_mpsafe; 298 mutex_exit(&sc->sc_lock); 299 300 if (!mpsafe) 301 KERNEL_LOCK(1, curlwp); 302 rv += callback(arg); 303 if (!mpsafe) 304 KERNEL_UNLOCK_ONE(curlwp); 305 306 mutex_enter(&sc->sc_lock); 307 if (lastgen != sc->sc_intrgen) 308 break; 309 } 310 mutex_exit(&sc->sc_lock); 311 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 312 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 313 msg); 314 } else { 315 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 316 rv = 1; 317 } 318 319 return rv; 320 } 321 322 static int 323 tegra_pcie_intr(void *priv) 324 { 325 struct tegra_pcie_softc *sc = priv; 326 int rv; 327 328 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 329 AFI_INTR_CODE_REG); 330 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 331 AFI_INTR_SIGNATURE_REG); 332 333 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 334 case AFI_INTR_CODE_SM_MSG: 335 rv = tegra_pcie_legacy_intr(sc); 336 break; 337 default: 338 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 339 code, sig); 340 rv = 1; 341 break; 342 } 343 344 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 345 346 return rv; 347 } 348 349 static void 350 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 351 { 352 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 353 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 354 struct fdtbus_reset *rst; 355 struct clk *clk; 356 int n; 357 358 for (n = 0; n < __arraycount(clock_names); n++) { 359 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 360 if (clk == NULL || clk_enable(clk) != 0) 361 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 362 clock_names[n]); 363 } 364 365 for (n = 0; n < __arraycount(reset_names); n++) { 366 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 367 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 368 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 369 reset_names[n]); 370 } 371 } 372 373 #if 0 374 static void 375 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 376 { 377 uint32_t val; 378 379 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 380 val &= ~AFI_PEXn_CTRL_RST_L; 381 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 382 383 delay(2000); 384 385 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 386 val |= AFI_PEXn_CTRL_RST_L; 387 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 388 } 389 #endif 390 391 static void 392 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 393 { 394 struct fdtbus_phy *phy; 395 const u_int *data; 396 int child, len, n; 397 uint32_t val; 398 399 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 400 if (!fdtbus_status_okay(child)) 401 continue; 402 403 /* Enable PHYs */ 404 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 405 if (fdtbus_phy_enable(phy, true) != 0) 406 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 407 fdtbus_get_string(child, "name"), n); 408 409 data = fdtbus_get_prop(child, "reg", &len); 410 if (data == NULL || len < 4) 411 continue; 412 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 413 414 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 415 val |= AFI_PEXn_CTRL_CLKREQ_EN; 416 val |= AFI_PEXn_CTRL_REFCLK_EN; 417 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 418 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 419 420 #if 0 421 tegra_pcie_reset_port(sc, index); 422 #endif 423 424 } 425 } 426 427 static void 428 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 429 { 430 uint32_t val, cfg, lanes; 431 int child, len; 432 const u_int *data; 433 size_t i; 434 435 /* Enable PLLE control */ 436 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 437 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 438 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 439 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 440 441 /* Disable PEX clock bias pad power down */ 442 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 443 444 /* Configure PCIE mode and enable ports */ 445 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 446 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 447 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 448 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 449 450 lanes = 0; 451 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 452 if (!fdtbus_status_okay(child)) 453 continue; 454 data = fdtbus_get_prop(child, "reg", &len); 455 if (data == NULL || len < 4) 456 continue; 457 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 458 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 459 continue; 460 lanes |= (val << (index << 3)); 461 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 462 } 463 464 switch (lanes) { 465 case 0x0104: 466 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 467 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 468 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 469 break; 470 case 0x0102: 471 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 472 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 473 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 474 break; 475 } 476 477 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 478 479 /* Configure refclk pad */ 480 if (sc->sc_type == TEGRA_PCIE_124) { 481 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, 482 PADS_REFCLK_CFG0_REG, 0x44ac44ac); 483 } 484 if (sc->sc_type == TEGRA_PCIE_210) { 485 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, 486 PADS_REFCLK_CFG0_REG, 0x90b890b8); 487 } 488 489 /* 490 * Map PCI address spaces into ARM address space via 491 * HyperTransport-like "FPCI". 492 */ 493 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 494 /* 495 * === BEWARE === 496 * 497 * We depend on our TEGRA_PCIE_IO window overlaping the 498 * TEGRA_PCIE_A1 window to allow us to use the same 499 * bus_space_tag for both PCI IO and Memory spaces. 500 * 501 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 502 * mapping for 0x0000000-0x1ffffff of PCI IO space. 503 */ 504 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 505 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 506 507 /* HyperTransport Technology Type 1 Address Format */ 508 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 509 0xfdff000000 >> 8 | 0, }, 510 511 /* 1:1 MMIO mapping */ 512 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 513 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 514 515 /* Extended HyperTransport Technology Type 1 Address Format */ 516 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 517 0xfe10000000 >> 8 | 0, }, 518 519 /* 1:1 prefetchable MMIO mapping */ 520 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 521 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 522 }; 523 524 for (i = 0; i < AFI_AXI_NBAR; i++) { 525 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 526 AFI_AXI_BARi_SZ(i), 0); 527 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 528 AFI_AXI_BARi_START(i), 0); 529 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 530 AFI_FPCI_BARi(i), 0); 531 } 532 533 for (i = 0; i < __arraycount(pcie_init_table); i++) { 534 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 535 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 536 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 537 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 538 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 539 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 540 } 541 } 542 543 static void 544 tegra_pcie_enable(struct tegra_pcie_softc *sc) 545 { 546 /* disable MSI */ 547 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 548 AFI_MSI_BAR_SZ_REG, 0); 549 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 550 AFI_MSI_FPCI_BAR_ST_REG, 0); 551 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 552 AFI_MSI_AXI_BAR_ST_REG, 0); 553 554 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 555 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 556 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 557 AFI_AFI_INTR_ENABLE_REG, 0); 558 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 559 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 560 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 561 } 562 563 static void 564 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 565 uint frg) 566 { 567 bus_addr_t a; 568 569 KASSERT(bus >= 1); 570 KASSERT(bus < TEGRA_PCIE_NBUS); 571 KASSERT(frg < TEGRA_PCIE_ECFB); 572 573 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 574 device_printf(sc->sc_dev, "bus %u fragment %#x already " 575 "mapped\n", bus, frg); 576 return; 577 } 578 579 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 580 if (bus_space_map(sc->sc_bst, a, 1 << 16, 581 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, 582 &sc->sc_bsh_extc[bus-1][frg]) != 0) 583 device_printf(sc->sc_dev, "couldn't map PCIE " 584 "configuration for bus %u fragment %#x", bus, frg); 585 } 586 587 /* map non-non-extended configuration space for full bus range */ 588 static void 589 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 590 { 591 uint i; 592 593 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 594 tegra_pcie_conf_frag_map(sc, bus, i); 595 } 596 } 597 598 /* map non-extended configuration space for full bus range */ 599 static void 600 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 601 { 602 uint b; 603 604 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 605 tegra_pcie_conf_frag_map(sc, b, 0); 606 } 607 } 608 609 void 610 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 611 { 612 pc->pc_conf_v = priv; 613 pc->pc_attach_hook = tegra_pcie_attach_hook; 614 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 615 pc->pc_make_tag = tegra_pcie_make_tag; 616 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 617 pc->pc_conf_read = tegra_pcie_conf_read; 618 pc->pc_conf_write = tegra_pcie_conf_write; 619 pc->pc_conf_hook = tegra_pcie_conf_hook; 620 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 621 622 pc->pc_intr_v = priv; 623 pc->pc_intr_map = tegra_pcie_intr_map; 624 pc->pc_intr_string = tegra_pcie_intr_string; 625 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 626 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 627 pc->pc_intr_establish = tegra_pcie_intr_establish; 628 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 629 } 630 631 static void 632 tegra_pcie_attach_hook(device_t parent, device_t self, 633 struct pcibus_attach_args *pba) 634 { 635 const pci_chipset_tag_t pc = pba->pba_pc; 636 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 637 638 if (pba->pba_bus >= 1) { 639 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 640 } 641 } 642 643 static int 644 tegra_pcie_bus_maxdevs(void *v, int busno) 645 { 646 return busno == 0 ? 2 : 32; 647 } 648 649 static pcitag_t 650 tegra_pcie_make_tag(void *v, int b, int d, int f) 651 { 652 return (b << 16) | (d << 11) | (f << 8); 653 } 654 655 static void 656 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 657 { 658 if (bp) 659 *bp = (tag >> 16) & 0xff; 660 if (dp) 661 *dp = (tag >> 11) & 0x1f; 662 if (fp) 663 *fp = (tag >> 8) & 0x7; 664 } 665 666 static pcireg_t 667 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 668 { 669 struct tegra_pcie_softc *sc = v; 670 bus_space_handle_t bsh; 671 int b, d, f; 672 u_int reg; 673 674 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 675 return (pcireg_t) -1; 676 677 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 678 679 if (b >= TEGRA_PCIE_NBUS) 680 return (pcireg_t) -1; 681 682 if (b == 0) { 683 if (d >= 2 || f != 0) 684 return (pcireg_t) -1; 685 reg = d * 0x1000 + offset; 686 bsh = sc->sc_bsh_rpconf; 687 } else { 688 reg = (d << 11) | (f << 8) | (offset & 0xff); 689 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 690 if (bsh == 0) 691 return (pcireg_t) -1; 692 } 693 694 return bus_space_read_4(sc->sc_bst, bsh, reg); 695 } 696 697 static void 698 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 699 { 700 struct tegra_pcie_softc *sc = v; 701 bus_space_handle_t bsh; 702 int b, d, f; 703 u_int reg; 704 705 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 706 return; 707 708 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 709 710 if (b >= TEGRA_PCIE_NBUS) 711 return; 712 713 if (b == 0) { 714 if (d >= 2 || f != 0) 715 return; 716 reg = d * 0x1000 + offset; 717 bsh = sc->sc_bsh_rpconf; 718 } else { 719 reg = (d << 11) | (f << 8) | (offset & 0xff); 720 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 721 if (bsh == 0) 722 return; 723 } 724 725 bus_space_write_4(sc->sc_bst, bsh, reg, val); 726 } 727 728 static int 729 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 730 { 731 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 732 } 733 734 static void 735 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 736 int *ilinep) 737 { 738 *ilinep = 5; 739 } 740 741 static int 742 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 743 { 744 if (pa->pa_intrpin == 0) 745 return EINVAL; 746 *ih = pa->pa_intrpin; 747 return 0; 748 } 749 750 static const char * 751 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 752 { 753 struct tegra_pcie_softc *sc = v; 754 755 if (ih == PCI_INTERRUPT_PIN_NONE) 756 return NULL; 757 758 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 759 return NULL; 760 761 return buf; 762 } 763 764 const struct evcnt * 765 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 766 { 767 return NULL; 768 } 769 770 static int 771 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 772 { 773 switch (attr) { 774 case PCI_INTR_MPSAFE: 775 if (data) 776 *ih |= IH_MPSAFE; 777 else 778 *ih &= ~IH_MPSAFE; 779 return 0; 780 default: 781 return ENODEV; 782 } 783 } 784 785 static void * 786 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 787 int (*callback)(void *), void *arg, const char *xname) 788 { 789 struct tegra_pcie_softc *sc = v; 790 struct tegra_pcie_ih *pcie_ih; 791 792 if (ih == 0) 793 return NULL; 794 795 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 796 pcie_ih->ih_callback = callback; 797 pcie_ih->ih_arg = arg; 798 pcie_ih->ih_ipl = ipl; 799 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 800 801 mutex_enter(&sc->sc_lock); 802 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 803 sc->sc_intrgen++; 804 mutex_exit(&sc->sc_lock); 805 806 return pcie_ih; 807 } 808 809 static void 810 tegra_pcie_intr_disestablish(void *v, void *vih) 811 { 812 struct tegra_pcie_softc *sc = v; 813 struct tegra_pcie_ih *pcie_ih = vih; 814 815 mutex_enter(&sc->sc_lock); 816 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 817 mutex_exit(&sc->sc_lock); 818 819 kmem_free(pcie_ih, sizeof(*pcie_ih)); 820 } 821