1 /* $NetBSD: tegra_pcie.c,v 1.23 2017/10/19 16:01:58 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.23 2017/10/19 16:01:58 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <arm/cpufunc.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <arm/nvidia/tegra_reg.h> 50 #include <arm/nvidia/tegra_pciereg.h> 51 #include <arm/nvidia/tegra_pmcreg.h> 52 #include <arm/nvidia/tegra_var.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 /* Interrupt handle flags */ 57 #define IH_MPSAFE 0x80000000 58 59 static int tegra_pcie_match(device_t, cfdata_t, void *); 60 static void tegra_pcie_attach(device_t, device_t, void *); 61 62 #define TEGRA_PCIE_NBUS 256 63 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 64 65 struct tegra_pcie_ih { 66 int (*ih_callback)(void *); 67 void *ih_arg; 68 int ih_ipl; 69 int ih_mpsafe; 70 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 71 }; 72 73 struct tegra_pcie_softc { 74 device_t sc_dev; 75 bus_dma_tag_t sc_dmat; 76 bus_space_tag_t sc_bst; 77 bus_space_handle_t sc_bsh_afi; 78 bus_space_handle_t sc_bsh_pads; 79 bus_space_handle_t sc_bsh_rpconf; 80 int sc_phandle; 81 82 struct arm32_pci_chipset sc_pc; 83 84 void *sc_ih; 85 86 kmutex_t sc_lock; 87 88 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 89 u_int sc_intrgen; 90 91 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 92 }; 93 94 static int tegra_pcie_intr(void *); 95 static void tegra_pcie_init(pci_chipset_tag_t, void *); 96 static void tegra_pcie_enable(struct tegra_pcie_softc *); 97 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 98 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 99 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 100 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 101 uint, uint); 102 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 103 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 104 105 static void tegra_pcie_attach_hook(device_t, device_t, 106 struct pcibus_attach_args *); 107 static int tegra_pcie_bus_maxdevs(void *, int); 108 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 109 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 110 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 111 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 112 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 113 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 114 115 static int tegra_pcie_intr_map(const struct pci_attach_args *, 116 pci_intr_handle_t *); 117 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 118 char *, size_t); 119 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 120 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 121 uint64_t); 122 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 123 int, int (*)(void *), void *); 124 static void tegra_pcie_intr_disestablish(void *, void *); 125 126 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 127 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 128 129 static int 130 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 131 { 132 const char * const compatible[] = { 133 "nvidia,tegra210-pcie", 134 "nvidia,tegra124-pcie", 135 NULL 136 }; 137 struct fdt_attach_args * const faa = aux; 138 139 return of_match_compatible(faa->faa_phandle, compatible); 140 } 141 142 static void 143 tegra_pcie_attach(device_t parent, device_t self, void *aux) 144 { 145 struct tegra_pcie_softc * const sc = device_private(self); 146 struct fdt_attach_args * const faa = aux; 147 struct extent *ioext, *memext, *pmemext; 148 struct pcibus_attach_args pba; 149 bus_addr_t afi_addr, cs_addr, pads_addr; 150 bus_size_t afi_size, cs_size, pads_size; 151 char intrstr[128]; 152 int error; 153 154 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 155 aprint_error(": couldn't get afi registers\n"); 156 return; 157 } 158 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 159 aprint_error(": couldn't get pads registers\n"); 160 return; 161 } 162 #if notyet 163 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 164 aprint_error(": couldn't get cs registers\n"); 165 return; 166 } 167 #else 168 cs_addr = TEGRA_PCIE_RPCONF_BASE; 169 cs_size = TEGRA_PCIE_RPCONF_SIZE; 170 #endif 171 172 sc->sc_dev = self; 173 sc->sc_dmat = faa->faa_dmat; 174 sc->sc_bst = faa->faa_bst; 175 sc->sc_phandle = faa->faa_phandle; 176 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 177 &sc->sc_bsh_afi); 178 if (error) { 179 aprint_error(": couldn't map afi registers: %d\n", error); 180 return; 181 } 182 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 183 &sc->sc_bsh_pads); 184 if (error) { 185 aprint_error(": couldn't map afi registers: %d\n", error); 186 return; 187 } 188 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 189 &sc->sc_bsh_rpconf); 190 if (error) { 191 aprint_error(": couldn't map cs registers: %d\n", error); 192 return; 193 } 194 195 tegra_pcie_conf_map_buses(sc); 196 197 TAILQ_INIT(&sc->sc_intrs); 198 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 199 200 aprint_naive("\n"); 201 aprint_normal(": PCIE\n"); 202 203 tegra_pmc_power(PMC_PARTID_PCX, true); 204 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 205 206 tegra_pcie_enable_clocks(sc); 207 208 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 209 aprint_error_dev(self, "failed to decode interrupt\n"); 210 return; 211 } 212 213 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 214 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 215 if (sc->sc_ih == NULL) { 216 aprint_error_dev(self, "failed to establish interrupt on %s\n", 217 intrstr); 218 return; 219 } 220 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 221 222 tegra_pcie_setup(sc); 223 224 tegra_pcie_init(&sc->sc_pc, sc); 225 226 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 227 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 228 NULL, 0, EX_NOWAIT); 229 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 230 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 231 NULL, 0, EX_NOWAIT); 232 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 233 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 234 NULL, 0, EX_NOWAIT); 235 236 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 237 arm_dcache_align); 238 239 extent_destroy(ioext); 240 extent_destroy(memext); 241 extent_destroy(pmemext); 242 243 if (error) { 244 aprint_error_dev(self, "configuration failed (%d)\n", 245 error); 246 return; 247 } 248 249 tegra_pcie_enable(sc); 250 251 tegra_pcie_enable_ports(sc); 252 253 memset(&pba, 0, sizeof(pba)); 254 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 255 PCI_FLAGS_MRM_OKAY | 256 PCI_FLAGS_MWI_OKAY | 257 PCI_FLAGS_MEM_OKAY | 258 PCI_FLAGS_IO_OKAY; 259 pba.pba_iot = sc->sc_bst; 260 pba.pba_memt = sc->sc_bst; 261 pba.pba_dmat = sc->sc_dmat; 262 pba.pba_pc = &sc->sc_pc; 263 pba.pba_bus = 0; 264 265 config_found_ia(self, "pcibus", &pba, pcibusprint); 266 } 267 268 static int 269 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 270 { 271 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 272 AFI_MSG_REG); 273 struct tegra_pcie_ih *pcie_ih; 274 int rv = 0; 275 276 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 277 mutex_enter(&sc->sc_lock); 278 const u_int lastgen = sc->sc_intrgen; 279 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 280 int (*callback)(void *) = pcie_ih->ih_callback; 281 void *arg = pcie_ih->ih_arg; 282 const int mpsafe = pcie_ih->ih_mpsafe; 283 mutex_exit(&sc->sc_lock); 284 285 if (!mpsafe) 286 KERNEL_LOCK(1, curlwp); 287 rv += callback(arg); 288 if (!mpsafe) 289 KERNEL_UNLOCK_ONE(curlwp); 290 291 mutex_enter(&sc->sc_lock); 292 if (lastgen != sc->sc_intrgen) 293 break; 294 } 295 mutex_exit(&sc->sc_lock); 296 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 297 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 298 msg); 299 } else { 300 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 301 rv = 1; 302 } 303 304 return rv; 305 } 306 307 static int 308 tegra_pcie_intr(void *priv) 309 { 310 struct tegra_pcie_softc *sc = priv; 311 int rv; 312 313 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 314 AFI_INTR_CODE_REG); 315 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 316 AFI_INTR_SIGNATURE_REG); 317 318 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 319 case AFI_INTR_CODE_SM_MSG: 320 rv = tegra_pcie_legacy_intr(sc); 321 break; 322 default: 323 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 324 code, sig); 325 rv = 1; 326 break; 327 } 328 329 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 330 331 return rv; 332 } 333 334 static void 335 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 336 { 337 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 338 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 339 struct fdtbus_reset *rst; 340 struct clk *clk; 341 int n; 342 343 for (n = 0; n < __arraycount(clock_names); n++) { 344 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 345 if (clk == NULL || clk_enable(clk) != 0) 346 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 347 clock_names[n]); 348 } 349 350 for (n = 0; n < __arraycount(reset_names); n++) { 351 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 352 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 353 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 354 reset_names[n]); 355 } 356 } 357 358 #if 0 359 static void 360 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 361 { 362 uint32_t val; 363 364 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 365 val &= ~AFI_PEXn_CTRL_RST_L; 366 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 367 368 delay(2000); 369 370 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 371 val |= AFI_PEXn_CTRL_RST_L; 372 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 373 } 374 #endif 375 376 static void 377 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 378 { 379 struct fdtbus_phy *phy; 380 const u_int *data; 381 int child, len, n; 382 uint32_t val; 383 384 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 385 if (!fdtbus_status_okay(child)) 386 continue; 387 388 /* Enable PHYs */ 389 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 390 if (fdtbus_phy_enable(phy, true) != 0) 391 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 392 fdtbus_get_string(child, "name"), n); 393 394 data = fdtbus_get_prop(child, "reg", &len); 395 if (data == NULL || len < 4) 396 continue; 397 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 398 399 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 400 val |= AFI_PEXn_CTRL_CLKREQ_EN; 401 val |= AFI_PEXn_CTRL_REFCLK_EN; 402 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 403 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 404 405 #if 0 406 tegra_pcie_reset_port(sc, index); 407 #endif 408 409 } 410 } 411 412 static void 413 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 414 { 415 uint32_t val, cfg, lanes; 416 int child, len; 417 const u_int *data; 418 size_t i; 419 420 /* Enable PLLE control */ 421 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 422 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 423 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 424 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 425 426 /* Disable PEX clock bias pad power down */ 427 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 428 429 /* Configure PCIE mode and enable ports */ 430 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 431 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 432 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 433 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 434 435 lanes = 0; 436 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 437 if (!fdtbus_status_okay(child)) 438 continue; 439 data = fdtbus_get_prop(child, "reg", &len); 440 if (data == NULL || len < 4) 441 continue; 442 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 443 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 444 continue; 445 lanes |= (val << (index << 3)); 446 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 447 } 448 449 switch (lanes) { 450 case 0x0104: 451 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 452 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 453 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 454 break; 455 case 0x0102: 456 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 457 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 458 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 459 break; 460 } 461 462 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 463 464 /* Configure refclk pad */ 465 const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL }; 466 if (of_match_compatible(sc->sc_phandle, tegra124_compat)) 467 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 468 0x44ac44ac); 469 const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL }; 470 if (of_match_compatible(sc->sc_phandle, tegra210_compat)) 471 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 472 0x90b890b8); 473 474 /* 475 * Map PCI address spaces into ARM address space via 476 * HyperTransport-like "FPCI". 477 */ 478 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 479 /* 480 * === BEWARE === 481 * 482 * We depend on our TEGRA_PCIE_IO window overlaping the 483 * TEGRA_PCIE_A1 window to allow us to use the same 484 * bus_space_tag for both PCI IO and Memory spaces. 485 * 486 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 487 * mapping for 0x0000000-0x1ffffff of PCI IO space. 488 */ 489 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 490 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 491 492 /* HyperTransport Technology Type 1 Address Format */ 493 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 494 0xfdff000000 >> 8 | 0, }, 495 496 /* 1:1 MMIO mapping */ 497 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 498 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 499 500 /* Extended HyperTransport Technology Type 1 Address Format */ 501 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 502 0xfe10000000 >> 8 | 0, }, 503 504 /* 1:1 prefetchable MMIO mapping */ 505 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 506 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 507 }; 508 509 for (i = 0; i < AFI_AXI_NBAR; i++) { 510 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 511 AFI_AXI_BARi_SZ(i), 0); 512 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 513 AFI_AXI_BARi_START(i), 0); 514 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 515 AFI_FPCI_BARi(i), 0); 516 } 517 518 for (i = 0; i < __arraycount(pcie_init_table); i++) { 519 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 520 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 521 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 522 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 523 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 524 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 525 } 526 } 527 528 static void 529 tegra_pcie_enable(struct tegra_pcie_softc *sc) 530 { 531 /* disable MSI */ 532 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 533 AFI_MSI_BAR_SZ_REG, 0); 534 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 535 AFI_MSI_FPCI_BAR_ST_REG, 0); 536 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 537 AFI_MSI_AXI_BAR_ST_REG, 0); 538 539 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 540 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 541 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 542 AFI_AFI_INTR_ENABLE_REG, 0); 543 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 544 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 545 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 546 } 547 548 static void 549 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 550 uint frg) 551 { 552 bus_addr_t a; 553 554 KASSERT(bus >= 1); 555 KASSERT(bus < TEGRA_PCIE_NBUS); 556 KASSERT(frg < TEGRA_PCIE_ECFB); 557 558 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 559 device_printf(sc->sc_dev, "bus %u fragment %#x already " 560 "mapped\n", bus, frg); 561 return; 562 } 563 564 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 565 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 566 &sc->sc_bsh_extc[bus-1][frg]) != 0) 567 device_printf(sc->sc_dev, "couldn't map PCIE " 568 "configuration for bus %u fragment %#x", bus, frg); 569 } 570 571 /* map non-non-extended configuration space for full bus range */ 572 static void 573 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 574 { 575 uint i; 576 577 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 578 tegra_pcie_conf_frag_map(sc, bus, i); 579 } 580 } 581 582 /* map non-extended configuration space for full bus range */ 583 static void 584 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 585 { 586 uint b; 587 588 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 589 tegra_pcie_conf_frag_map(sc, b, 0); 590 } 591 } 592 593 void 594 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 595 { 596 pc->pc_conf_v = priv; 597 pc->pc_attach_hook = tegra_pcie_attach_hook; 598 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 599 pc->pc_make_tag = tegra_pcie_make_tag; 600 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 601 pc->pc_conf_read = tegra_pcie_conf_read; 602 pc->pc_conf_write = tegra_pcie_conf_write; 603 pc->pc_conf_hook = tegra_pcie_conf_hook; 604 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 605 606 pc->pc_intr_v = priv; 607 pc->pc_intr_map = tegra_pcie_intr_map; 608 pc->pc_intr_string = tegra_pcie_intr_string; 609 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 610 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 611 pc->pc_intr_establish = tegra_pcie_intr_establish; 612 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 613 } 614 615 static void 616 tegra_pcie_attach_hook(device_t parent, device_t self, 617 struct pcibus_attach_args *pba) 618 { 619 const pci_chipset_tag_t pc = pba->pba_pc; 620 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 621 622 if (pba->pba_bus >= 1) { 623 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 624 } 625 } 626 627 static int 628 tegra_pcie_bus_maxdevs(void *v, int busno) 629 { 630 return busno == 0 ? 2 : 32; 631 } 632 633 static pcitag_t 634 tegra_pcie_make_tag(void *v, int b, int d, int f) 635 { 636 return (b << 16) | (d << 11) | (f << 8); 637 } 638 639 static void 640 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 641 { 642 if (bp) 643 *bp = (tag >> 16) & 0xff; 644 if (dp) 645 *dp = (tag >> 11) & 0x1f; 646 if (fp) 647 *fp = (tag >> 8) & 0x7; 648 } 649 650 static pcireg_t 651 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 652 { 653 struct tegra_pcie_softc *sc = v; 654 bus_space_handle_t bsh; 655 int b, d, f; 656 u_int reg; 657 658 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 659 return (pcireg_t) -1; 660 661 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 662 663 if (b >= TEGRA_PCIE_NBUS) 664 return (pcireg_t) -1; 665 666 if (b == 0) { 667 if (d >= 2 || f != 0) 668 return (pcireg_t) -1; 669 reg = d * 0x1000 + offset; 670 bsh = sc->sc_bsh_rpconf; 671 } else { 672 reg = (d << 11) | (f << 8) | (offset & 0xff); 673 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 674 if (bsh == 0) 675 return (pcireg_t) -1; 676 } 677 678 return bus_space_read_4(sc->sc_bst, bsh, reg); 679 } 680 681 static void 682 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 683 { 684 struct tegra_pcie_softc *sc = v; 685 bus_space_handle_t bsh; 686 int b, d, f; 687 u_int reg; 688 689 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 690 return; 691 692 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 693 694 if (b >= TEGRA_PCIE_NBUS) 695 return; 696 697 if (b == 0) { 698 if (d >= 2 || f != 0) 699 return; 700 reg = d * 0x1000 + offset; 701 bsh = sc->sc_bsh_rpconf; 702 } else { 703 reg = (d << 11) | (f << 8) | (offset & 0xff); 704 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 705 if (bsh == 0) 706 return; 707 } 708 709 bus_space_write_4(sc->sc_bst, bsh, reg, val); 710 } 711 712 static int 713 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 714 { 715 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 716 } 717 718 static void 719 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 720 int *ilinep) 721 { 722 *ilinep = 5; 723 } 724 725 static int 726 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 727 { 728 if (pa->pa_intrpin == 0) 729 return EINVAL; 730 *ih = pa->pa_intrpin; 731 return 0; 732 } 733 734 static const char * 735 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 736 { 737 struct tegra_pcie_softc *sc = v; 738 739 if (ih == PCI_INTERRUPT_PIN_NONE) 740 return NULL; 741 742 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 743 return NULL; 744 745 return buf; 746 } 747 748 const struct evcnt * 749 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 750 { 751 return NULL; 752 } 753 754 static int 755 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 756 { 757 switch (attr) { 758 case PCI_INTR_MPSAFE: 759 if (data) 760 *ih |= IH_MPSAFE; 761 else 762 *ih &= ~IH_MPSAFE; 763 return 0; 764 default: 765 return ENODEV; 766 } 767 } 768 769 static void * 770 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 771 int (*callback)(void *), void *arg) 772 { 773 struct tegra_pcie_softc *sc = v; 774 struct tegra_pcie_ih *pcie_ih; 775 776 if (ih == 0) 777 return NULL; 778 779 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 780 pcie_ih->ih_callback = callback; 781 pcie_ih->ih_arg = arg; 782 pcie_ih->ih_ipl = ipl; 783 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 784 785 mutex_enter(&sc->sc_lock); 786 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 787 sc->sc_intrgen++; 788 mutex_exit(&sc->sc_lock); 789 790 return pcie_ih; 791 } 792 793 static void 794 tegra_pcie_intr_disestablish(void *v, void *vih) 795 { 796 struct tegra_pcie_softc *sc = v; 797 struct tegra_pcie_ih *pcie_ih = vih; 798 799 mutex_enter(&sc->sc_lock); 800 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 801 mutex_exit(&sc->sc_lock); 802 803 kmem_free(pcie_ih, sizeof(*pcie_ih)); 804 } 805