1 /* $NetBSD: tegra_pcie.c,v 1.31 2020/07/07 03:38:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.31 2020/07/07 03:38:46 thorpej Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kmem.h> 38 #include <sys/kernel.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <arm/nvidia/tegra_reg.h> 53 #include <arm/nvidia/tegra_pciereg.h> 54 #include <arm/nvidia/tegra_pmcreg.h> 55 #include <arm/nvidia/tegra_var.h> 56 57 #include <dev/fdt/fdtvar.h> 58 59 /* Interrupt handle flags */ 60 #define IH_MPSAFE 0x80000000 61 62 static int tegra_pcie_match(device_t, cfdata_t, void *); 63 static void tegra_pcie_attach(device_t, device_t, void *); 64 65 #define TEGRA_PCIE_NBUS 256 66 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 67 68 struct tegra_pcie_ih { 69 int (*ih_callback)(void *); 70 void *ih_arg; 71 int ih_ipl; 72 int ih_mpsafe; 73 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 74 }; 75 76 struct tegra_pcie_softc { 77 device_t sc_dev; 78 bus_dma_tag_t sc_dmat; 79 bus_space_tag_t sc_bst; 80 bus_space_handle_t sc_bsh_afi; 81 bus_space_handle_t sc_bsh_pads; 82 bus_space_handle_t sc_bsh_rpconf; 83 int sc_phandle; 84 85 struct arm32_pci_chipset sc_pc; 86 87 void *sc_ih; 88 89 kmutex_t sc_lock; 90 91 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 92 u_int sc_intrgen; 93 94 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 95 }; 96 97 static int tegra_pcie_intr(void *); 98 static void tegra_pcie_init(pci_chipset_tag_t, void *); 99 static void tegra_pcie_enable(struct tegra_pcie_softc *); 100 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 101 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 102 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 103 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 104 uint, uint); 105 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 106 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 107 108 static void tegra_pcie_attach_hook(device_t, device_t, 109 struct pcibus_attach_args *); 110 static int tegra_pcie_bus_maxdevs(void *, int); 111 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 112 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 113 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 114 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 115 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 116 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 117 118 static int tegra_pcie_intr_map(const struct pci_attach_args *, 119 pci_intr_handle_t *); 120 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 121 char *, size_t); 122 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 123 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 124 uint64_t); 125 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 126 int, int (*)(void *), void *, 127 const char *); 128 static void tegra_pcie_intr_disestablish(void *, void *); 129 130 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 131 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 132 133 static int 134 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 135 { 136 const char * const compatible[] = { 137 "nvidia,tegra210-pcie", 138 "nvidia,tegra124-pcie", 139 NULL 140 }; 141 struct fdt_attach_args * const faa = aux; 142 143 return of_match_compatible(faa->faa_phandle, compatible); 144 } 145 146 static void 147 tegra_pcie_attach(device_t parent, device_t self, void *aux) 148 { 149 struct tegra_pcie_softc * const sc = device_private(self); 150 struct fdt_attach_args * const faa = aux; 151 struct pciconf_resources *pcires; 152 struct pcibus_attach_args pba; 153 bus_addr_t afi_addr, cs_addr, pads_addr; 154 bus_size_t afi_size, cs_size, pads_size; 155 char intrstr[128]; 156 int error; 157 158 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 159 aprint_error(": couldn't get afi registers\n"); 160 return; 161 } 162 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 163 aprint_error(": couldn't get pads registers\n"); 164 return; 165 } 166 #if notyet 167 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 168 aprint_error(": couldn't get cs registers\n"); 169 return; 170 } 171 #else 172 cs_addr = TEGRA_PCIE_RPCONF_BASE; 173 cs_size = TEGRA_PCIE_RPCONF_SIZE; 174 #endif 175 176 sc->sc_dev = self; 177 sc->sc_dmat = faa->faa_dmat; 178 sc->sc_bst = faa->faa_bst; 179 sc->sc_phandle = faa->faa_phandle; 180 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 181 &sc->sc_bsh_afi); 182 if (error) { 183 aprint_error(": couldn't map afi registers: %d\n", error); 184 return; 185 } 186 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 187 &sc->sc_bsh_pads); 188 if (error) { 189 aprint_error(": couldn't map pads registers: %d\n", error); 190 return; 191 } 192 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 193 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh_rpconf); 194 if (error) { 195 aprint_error(": couldn't map cs registers: %d\n", error); 196 return; 197 } 198 199 tegra_pcie_conf_map_buses(sc); 200 201 TAILQ_INIT(&sc->sc_intrs); 202 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 203 204 aprint_naive("\n"); 205 aprint_normal(": PCIE\n"); 206 207 tegra_pmc_power(PMC_PARTID_PCX, true); 208 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 209 210 tegra_pcie_enable_clocks(sc); 211 212 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 213 aprint_error_dev(self, "failed to decode interrupt\n"); 214 return; 215 } 216 217 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 218 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 219 if (sc->sc_ih == NULL) { 220 aprint_error_dev(self, "failed to establish interrupt on %s\n", 221 intrstr); 222 return; 223 } 224 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 225 226 tegra_pcie_setup(sc); 227 228 tegra_pcie_init(&sc->sc_pc, sc); 229 230 pcires = pciconf_resource_init(); 231 232 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 233 TEGRA_PCIE_IO_BASE, TEGRA_PCIE_IO_SIZE); 234 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 235 TEGRA_PCIE_MEM_BASE, TEGRA_PCIE_MEM_SIZE); 236 pciconf_resource_add(pcires, PCICONF_RESOURCE_PREFETCHABLE_MEM, 237 TEGRA_PCIE_PMEM_BASE, TEGRA_PCIE_PMEM_SIZE); 238 239 error = pci_configure_bus(&sc->sc_pc, pcires, 0, 240 arm_dcache_align); 241 242 pciconf_resource_fini(pcires); 243 244 if (error) { 245 aprint_error_dev(self, "configuration failed (%d)\n", 246 error); 247 return; 248 } 249 250 tegra_pcie_enable(sc); 251 252 tegra_pcie_enable_ports(sc); 253 254 memset(&pba, 0, sizeof(pba)); 255 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 256 PCI_FLAGS_MRM_OKAY | 257 PCI_FLAGS_MWI_OKAY | 258 PCI_FLAGS_MEM_OKAY | 259 PCI_FLAGS_IO_OKAY; 260 pba.pba_iot = sc->sc_bst; 261 pba.pba_memt = sc->sc_bst; 262 pba.pba_dmat = sc->sc_dmat; 263 pba.pba_pc = &sc->sc_pc; 264 pba.pba_bus = 0; 265 266 config_found_ia(self, "pcibus", &pba, pcibusprint); 267 } 268 269 static int 270 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 271 { 272 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 273 AFI_MSG_REG); 274 struct tegra_pcie_ih *pcie_ih; 275 int rv = 0; 276 277 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 278 mutex_enter(&sc->sc_lock); 279 const u_int lastgen = sc->sc_intrgen; 280 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 281 int (*callback)(void *) = pcie_ih->ih_callback; 282 void *arg = pcie_ih->ih_arg; 283 const int mpsafe = pcie_ih->ih_mpsafe; 284 mutex_exit(&sc->sc_lock); 285 286 if (!mpsafe) 287 KERNEL_LOCK(1, curlwp); 288 rv += callback(arg); 289 if (!mpsafe) 290 KERNEL_UNLOCK_ONE(curlwp); 291 292 mutex_enter(&sc->sc_lock); 293 if (lastgen != sc->sc_intrgen) 294 break; 295 } 296 mutex_exit(&sc->sc_lock); 297 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 298 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 299 msg); 300 } else { 301 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 302 rv = 1; 303 } 304 305 return rv; 306 } 307 308 static int 309 tegra_pcie_intr(void *priv) 310 { 311 struct tegra_pcie_softc *sc = priv; 312 int rv; 313 314 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 315 AFI_INTR_CODE_REG); 316 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 317 AFI_INTR_SIGNATURE_REG); 318 319 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 320 case AFI_INTR_CODE_SM_MSG: 321 rv = tegra_pcie_legacy_intr(sc); 322 break; 323 default: 324 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 325 code, sig); 326 rv = 1; 327 break; 328 } 329 330 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 331 332 return rv; 333 } 334 335 static void 336 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 337 { 338 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 339 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 340 struct fdtbus_reset *rst; 341 struct clk *clk; 342 int n; 343 344 for (n = 0; n < __arraycount(clock_names); n++) { 345 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 346 if (clk == NULL || clk_enable(clk) != 0) 347 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 348 clock_names[n]); 349 } 350 351 for (n = 0; n < __arraycount(reset_names); n++) { 352 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 353 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 354 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 355 reset_names[n]); 356 } 357 } 358 359 #if 0 360 static void 361 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 362 { 363 uint32_t val; 364 365 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 366 val &= ~AFI_PEXn_CTRL_RST_L; 367 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 368 369 delay(2000); 370 371 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 372 val |= AFI_PEXn_CTRL_RST_L; 373 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 374 } 375 #endif 376 377 static void 378 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 379 { 380 struct fdtbus_phy *phy; 381 const u_int *data; 382 int child, len, n; 383 uint32_t val; 384 385 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 386 if (!fdtbus_status_okay(child)) 387 continue; 388 389 /* Enable PHYs */ 390 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 391 if (fdtbus_phy_enable(phy, true) != 0) 392 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 393 fdtbus_get_string(child, "name"), n); 394 395 data = fdtbus_get_prop(child, "reg", &len); 396 if (data == NULL || len < 4) 397 continue; 398 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 399 400 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 401 val |= AFI_PEXn_CTRL_CLKREQ_EN; 402 val |= AFI_PEXn_CTRL_REFCLK_EN; 403 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 404 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 405 406 #if 0 407 tegra_pcie_reset_port(sc, index); 408 #endif 409 410 } 411 } 412 413 static void 414 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 415 { 416 uint32_t val, cfg, lanes; 417 int child, len; 418 const u_int *data; 419 size_t i; 420 421 /* Enable PLLE control */ 422 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 423 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 424 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 425 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 426 427 /* Disable PEX clock bias pad power down */ 428 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 429 430 /* Configure PCIE mode and enable ports */ 431 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 432 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 433 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 434 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 435 436 lanes = 0; 437 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 438 if (!fdtbus_status_okay(child)) 439 continue; 440 data = fdtbus_get_prop(child, "reg", &len); 441 if (data == NULL || len < 4) 442 continue; 443 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 444 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 445 continue; 446 lanes |= (val << (index << 3)); 447 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 448 } 449 450 switch (lanes) { 451 case 0x0104: 452 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 453 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 454 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 455 break; 456 case 0x0102: 457 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 458 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 459 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 460 break; 461 } 462 463 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 464 465 /* Configure refclk pad */ 466 const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL }; 467 if (of_match_compatible(sc->sc_phandle, tegra124_compat)) 468 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 469 0x44ac44ac); 470 const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL }; 471 if (of_match_compatible(sc->sc_phandle, tegra210_compat)) 472 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 473 0x90b890b8); 474 475 /* 476 * Map PCI address spaces into ARM address space via 477 * HyperTransport-like "FPCI". 478 */ 479 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 480 /* 481 * === BEWARE === 482 * 483 * We depend on our TEGRA_PCIE_IO window overlaping the 484 * TEGRA_PCIE_A1 window to allow us to use the same 485 * bus_space_tag for both PCI IO and Memory spaces. 486 * 487 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 488 * mapping for 0x0000000-0x1ffffff of PCI IO space. 489 */ 490 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 491 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 492 493 /* HyperTransport Technology Type 1 Address Format */ 494 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 495 0xfdff000000 >> 8 | 0, }, 496 497 /* 1:1 MMIO mapping */ 498 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 499 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 500 501 /* Extended HyperTransport Technology Type 1 Address Format */ 502 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 503 0xfe10000000 >> 8 | 0, }, 504 505 /* 1:1 prefetchable MMIO mapping */ 506 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 507 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 508 }; 509 510 for (i = 0; i < AFI_AXI_NBAR; i++) { 511 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 512 AFI_AXI_BARi_SZ(i), 0); 513 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 514 AFI_AXI_BARi_START(i), 0); 515 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 516 AFI_FPCI_BARi(i), 0); 517 } 518 519 for (i = 0; i < __arraycount(pcie_init_table); i++) { 520 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 521 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 522 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 523 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 524 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 525 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 526 } 527 } 528 529 static void 530 tegra_pcie_enable(struct tegra_pcie_softc *sc) 531 { 532 /* disable MSI */ 533 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 534 AFI_MSI_BAR_SZ_REG, 0); 535 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 536 AFI_MSI_FPCI_BAR_ST_REG, 0); 537 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 538 AFI_MSI_AXI_BAR_ST_REG, 0); 539 540 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 541 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 542 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 543 AFI_AFI_INTR_ENABLE_REG, 0); 544 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 545 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 546 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 547 } 548 549 static void 550 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 551 uint frg) 552 { 553 bus_addr_t a; 554 555 KASSERT(bus >= 1); 556 KASSERT(bus < TEGRA_PCIE_NBUS); 557 KASSERT(frg < TEGRA_PCIE_ECFB); 558 559 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 560 device_printf(sc->sc_dev, "bus %u fragment %#x already " 561 "mapped\n", bus, frg); 562 return; 563 } 564 565 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 566 if (bus_space_map(sc->sc_bst, a, 1 << 16, 567 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, 568 &sc->sc_bsh_extc[bus-1][frg]) != 0) 569 device_printf(sc->sc_dev, "couldn't map PCIE " 570 "configuration for bus %u fragment %#x", bus, frg); 571 } 572 573 /* map non-non-extended configuration space for full bus range */ 574 static void 575 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 576 { 577 uint i; 578 579 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 580 tegra_pcie_conf_frag_map(sc, bus, i); 581 } 582 } 583 584 /* map non-extended configuration space for full bus range */ 585 static void 586 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 587 { 588 uint b; 589 590 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 591 tegra_pcie_conf_frag_map(sc, b, 0); 592 } 593 } 594 595 void 596 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 597 { 598 pc->pc_conf_v = priv; 599 pc->pc_attach_hook = tegra_pcie_attach_hook; 600 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 601 pc->pc_make_tag = tegra_pcie_make_tag; 602 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 603 pc->pc_conf_read = tegra_pcie_conf_read; 604 pc->pc_conf_write = tegra_pcie_conf_write; 605 pc->pc_conf_hook = tegra_pcie_conf_hook; 606 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 607 608 pc->pc_intr_v = priv; 609 pc->pc_intr_map = tegra_pcie_intr_map; 610 pc->pc_intr_string = tegra_pcie_intr_string; 611 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 612 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 613 pc->pc_intr_establish = tegra_pcie_intr_establish; 614 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 615 } 616 617 static void 618 tegra_pcie_attach_hook(device_t parent, device_t self, 619 struct pcibus_attach_args *pba) 620 { 621 const pci_chipset_tag_t pc = pba->pba_pc; 622 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 623 624 if (pba->pba_bus >= 1) { 625 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 626 } 627 } 628 629 static int 630 tegra_pcie_bus_maxdevs(void *v, int busno) 631 { 632 return busno == 0 ? 2 : 32; 633 } 634 635 static pcitag_t 636 tegra_pcie_make_tag(void *v, int b, int d, int f) 637 { 638 return (b << 16) | (d << 11) | (f << 8); 639 } 640 641 static void 642 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 643 { 644 if (bp) 645 *bp = (tag >> 16) & 0xff; 646 if (dp) 647 *dp = (tag >> 11) & 0x1f; 648 if (fp) 649 *fp = (tag >> 8) & 0x7; 650 } 651 652 static pcireg_t 653 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 654 { 655 struct tegra_pcie_softc *sc = v; 656 bus_space_handle_t bsh; 657 int b, d, f; 658 u_int reg; 659 660 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 661 return (pcireg_t) -1; 662 663 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 664 665 if (b >= TEGRA_PCIE_NBUS) 666 return (pcireg_t) -1; 667 668 if (b == 0) { 669 if (d >= 2 || f != 0) 670 return (pcireg_t) -1; 671 reg = d * 0x1000 + offset; 672 bsh = sc->sc_bsh_rpconf; 673 } else { 674 reg = (d << 11) | (f << 8) | (offset & 0xff); 675 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 676 if (bsh == 0) 677 return (pcireg_t) -1; 678 } 679 680 return bus_space_read_4(sc->sc_bst, bsh, reg); 681 } 682 683 static void 684 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 685 { 686 struct tegra_pcie_softc *sc = v; 687 bus_space_handle_t bsh; 688 int b, d, f; 689 u_int reg; 690 691 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 692 return; 693 694 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 695 696 if (b >= TEGRA_PCIE_NBUS) 697 return; 698 699 if (b == 0) { 700 if (d >= 2 || f != 0) 701 return; 702 reg = d * 0x1000 + offset; 703 bsh = sc->sc_bsh_rpconf; 704 } else { 705 reg = (d << 11) | (f << 8) | (offset & 0xff); 706 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 707 if (bsh == 0) 708 return; 709 } 710 711 bus_space_write_4(sc->sc_bst, bsh, reg, val); 712 } 713 714 static int 715 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 716 { 717 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 718 } 719 720 static void 721 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 722 int *ilinep) 723 { 724 *ilinep = 5; 725 } 726 727 static int 728 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 729 { 730 if (pa->pa_intrpin == 0) 731 return EINVAL; 732 *ih = pa->pa_intrpin; 733 return 0; 734 } 735 736 static const char * 737 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 738 { 739 struct tegra_pcie_softc *sc = v; 740 741 if (ih == PCI_INTERRUPT_PIN_NONE) 742 return NULL; 743 744 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 745 return NULL; 746 747 return buf; 748 } 749 750 const struct evcnt * 751 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 752 { 753 return NULL; 754 } 755 756 static int 757 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 758 { 759 switch (attr) { 760 case PCI_INTR_MPSAFE: 761 if (data) 762 *ih |= IH_MPSAFE; 763 else 764 *ih &= ~IH_MPSAFE; 765 return 0; 766 default: 767 return ENODEV; 768 } 769 } 770 771 static void * 772 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 773 int (*callback)(void *), void *arg, const char *xname) 774 { 775 struct tegra_pcie_softc *sc = v; 776 struct tegra_pcie_ih *pcie_ih; 777 778 if (ih == 0) 779 return NULL; 780 781 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 782 pcie_ih->ih_callback = callback; 783 pcie_ih->ih_arg = arg; 784 pcie_ih->ih_ipl = ipl; 785 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 786 787 mutex_enter(&sc->sc_lock); 788 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 789 sc->sc_intrgen++; 790 mutex_exit(&sc->sc_lock); 791 792 return pcie_ih; 793 } 794 795 static void 796 tegra_pcie_intr_disestablish(void *v, void *vih) 797 { 798 struct tegra_pcie_softc *sc = v; 799 struct tegra_pcie_ih *pcie_ih = vih; 800 801 mutex_enter(&sc->sc_lock); 802 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 803 mutex_exit(&sc->sc_lock); 804 805 kmem_free(pcie_ih, sizeof(*pcie_ih)); 806 } 807