1 /* $NetBSD: tegra_mc.c,v 1.5 2015/12/13 17:39:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_mc.c,v 1.5 2015/12/13 17:39:19 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_mcreg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_mc_match(device_t, cfdata_t, void *); 48 static void tegra_mc_attach(device_t, device_t, void *); 49 50 static int tegra_mc_intr(void *); 51 52 struct tegra_mc_softc { 53 device_t sc_dev; 54 bus_space_tag_t sc_bst; 55 bus_space_handle_t sc_bsh; 56 void *sc_ih; 57 }; 58 59 static struct tegra_mc_softc *mc_softc = NULL; 60 61 CFATTACH_DECL_NEW(tegra_mc, sizeof(struct tegra_mc_softc), 62 tegra_mc_match, tegra_mc_attach, NULL, NULL); 63 64 #define MC_READ(sc, reg) \ 65 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 66 #define MC_WRITE(sc, reg, val) \ 67 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 68 #define MC_SET_CLEAR(sc, reg, set, clr) \ 69 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 70 71 static int 72 tegra_mc_match(device_t parent, cfdata_t cf, void *aux) 73 { 74 const char * const compatible[] = { "nvidia,tegra124-mc", NULL }; 75 struct fdt_attach_args * const faa = aux; 76 77 return of_match_compatible(faa->faa_phandle, compatible); 78 } 79 80 static void 81 tegra_mc_attach(device_t parent, device_t self, void *aux) 82 { 83 struct tegra_mc_softc * const sc = device_private(self); 84 struct fdt_attach_args * const faa = aux; 85 char intrstr[128]; 86 bus_addr_t addr; 87 bus_size_t size; 88 int error; 89 90 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 91 aprint_error(": couldn't get registers\n"); 92 return; 93 } 94 95 sc->sc_dev = self; 96 sc->sc_bst = faa->faa_bst; 97 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 98 if (error) { 99 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 100 return; 101 } 102 103 KASSERT(mc_softc == NULL); 104 mc_softc = sc; 105 106 aprint_naive("\n"); 107 aprint_normal(": MC\n"); 108 109 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 110 aprint_error_dev(self, "failed to decode interrupt\n"); 111 return; 112 } 113 114 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 115 FDT_INTR_MPSAFE, tegra_mc_intr, sc); 116 if (sc->sc_ih == NULL) { 117 aprint_error_dev(self, "failed to establish interrupt on %s\n", 118 intrstr); 119 return; 120 } 121 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 122 123 MC_WRITE(sc, MC_INTSTATUS_REG, MC_INT__ALL); 124 MC_WRITE(sc, MC_INTMASK_REG, MC_INT__ALL); 125 } 126 127 int 128 tegra_mc_intr(void *v) 129 { 130 struct tegra_mc_softc * const sc = v; 131 132 const uint32_t status = MC_READ(sc, MC_INTSTATUS_REG); 133 134 if (status == 0) { 135 return 0; 136 } 137 138 const uint32_t err_status = MC_READ(sc, MC_ERR_STATUS_REG); 139 const uint32_t err_adr = MC_READ(sc, MC_ERR_ADR_REG); 140 141 device_printf(sc->sc_dev, "intrstatus %#x err %#x adr %#x\n", 142 status, err_status, err_adr); 143 144 MC_WRITE(sc, MC_INTSTATUS_REG, status); 145 146 return status; 147 } 148 149 psize_t 150 tegra_mc_memsize(void) 151 { 152 bus_space_tag_t bst; 153 bus_space_handle_t bsh; 154 155 if (mc_softc) { 156 bst = mc_softc->sc_bst; 157 bsh = mc_softc->sc_bsh; 158 } else { 159 bst = &armv7_generic_bs_tag; 160 bus_space_subregion(bst, tegra_apb_bsh, 161 TEGRA_MC_OFFSET, TEGRA_MC_SIZE, &bsh); 162 } 163 164 const uint32_t emem_cfg = bus_space_read_4(bst, bsh, MC_EMEM_CFG_0_REG); 165 const psize_t nmb = __SHIFTOUT(emem_cfg, MC_EMEM_CFG_0_EMEM_SIZE_MB); 166 167 return nmb * 1024 * 1024; 168 } 169