1 /* $NetBSD: tegra_i2c.c,v 1.22 2018/09/25 22:23:22 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.22 2018/09/25 22:23:22 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 static i2c_tag_t tegra_i2c_get_tag(device_t); 51 52 struct fdtbus_i2c_controller_func tegra_i2c_funcs = { 53 .get_tag = tegra_i2c_get_tag 54 }; 55 56 struct tegra_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 struct fdtbus_reset * sc_rst; 63 u_int sc_cid; 64 65 struct i2c_controller sc_ic; 66 kmutex_t sc_lock; 67 kcondvar_t sc_cv; 68 }; 69 70 static void tegra_i2c_init(struct tegra_i2c_softc *); 71 static int tegra_i2c_intr(void *); 72 73 static int tegra_i2c_acquire_bus(void *, int); 74 static void tegra_i2c_release_bus(void *, int); 75 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 76 size_t, void *, size_t, int); 77 78 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 79 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 80 const uint8_t *, size_t, int, bool); 81 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 82 size_t, int); 83 84 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 85 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 86 87 #define I2C_WRITE(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89 #define I2C_READ(sc, reg) \ 90 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 91 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 92 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 93 94 static int 95 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 const char * const compatible[] = { 98 "nvidia,tegra210-i2c", 99 "nvidia,tegra124-i2c", 100 "nvidia,tegra114-i2c", 101 NULL 102 }; 103 struct fdt_attach_args * const faa = aux; 104 105 return of_match_compatible(faa->faa_phandle, compatible); 106 } 107 108 static void 109 tegra_i2c_attach(device_t parent, device_t self, void *aux) 110 { 111 struct tegra_i2c_softc * const sc = device_private(self); 112 struct fdt_attach_args * const faa = aux; 113 const int phandle = faa->faa_phandle; 114 char intrstr[128]; 115 bus_addr_t addr; 116 bus_size_t size; 117 int error; 118 119 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 120 aprint_error(": couldn't get registers\n"); 121 return; 122 } 123 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 124 if (sc->sc_clk == NULL) { 125 aprint_error(": couldn't get clock div-clk\n"); 126 return; 127 } 128 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 129 if (sc->sc_rst == NULL) { 130 aprint_error(": couldn't get reset i2c\n"); 131 return; 132 } 133 134 sc->sc_dev = self; 135 sc->sc_bst = faa->faa_bst; 136 sc->sc_cid = device_unit(self); 137 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 138 if (error) { 139 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 140 addr, error); 141 return; 142 } 143 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 144 cv_init(&sc->sc_cv, device_xname(self)); 145 146 aprint_naive("\n"); 147 aprint_normal(": I2C\n"); 148 149 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 150 aprint_error_dev(self, "failed to decode interrupt\n"); 151 return; 152 } 153 154 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 155 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 156 if (sc->sc_ih == NULL) { 157 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 158 intrstr); 159 return; 160 } 161 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 162 163 /* 164 * Recommended setting for standard mode is to use an I2C source div 165 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 166 */ 167 fdtbus_reset_assert(sc->sc_rst); 168 error = clk_set_rate(sc->sc_clk, 20400000); 169 if (error) { 170 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 171 return; 172 } 173 error = clk_enable(sc->sc_clk); 174 if (error) { 175 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 176 return; 177 } 178 fdtbus_reset_deassert(sc->sc_rst); 179 180 tegra_i2c_init(sc); 181 182 sc->sc_ic.ic_cookie = sc; 183 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 184 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 185 sc->sc_ic.ic_exec = tegra_i2c_exec; 186 187 fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs); 188 189 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 190 } 191 192 static i2c_tag_t 193 tegra_i2c_get_tag(device_t dev) 194 { 195 struct tegra_i2c_softc * const sc = device_private(dev); 196 197 return &sc->sc_ic; 198 } 199 200 static void 201 tegra_i2c_init(struct tegra_i2c_softc *sc) 202 { 203 int retry = 10000; 204 205 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 206 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 207 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 208 209 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 210 I2C_WRITE(sc, I2C_CNFG_REG, 211 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 212 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 213 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 214 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 215 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 216 217 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 218 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 219 while (--retry > 0) { 220 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 221 break; 222 delay(10); 223 } 224 if (retry == 0) { 225 device_printf(sc->sc_dev, "config load timeout\n"); 226 } 227 } 228 229 static int 230 tegra_i2c_intr(void *priv) 231 { 232 struct tegra_i2c_softc * const sc = priv; 233 234 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 235 if (istatus == 0) 236 return 0; 237 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 238 239 mutex_enter(&sc->sc_lock); 240 cv_broadcast(&sc->sc_cv); 241 mutex_exit(&sc->sc_lock); 242 243 return 1; 244 } 245 246 static int 247 tegra_i2c_acquire_bus(void *priv, int flags) 248 { 249 struct tegra_i2c_softc * const sc = priv; 250 251 mutex_enter(&sc->sc_lock); 252 253 return 0; 254 } 255 256 static void 257 tegra_i2c_release_bus(void *priv, int flags) 258 { 259 struct tegra_i2c_softc * const sc = priv; 260 261 mutex_exit(&sc->sc_lock); 262 } 263 264 static int 265 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 266 size_t cmdlen, void *buf, size_t buflen, int flags) 267 { 268 struct tegra_i2c_softc * const sc = priv; 269 int retry, error; 270 271 #if notyet 272 if (cold) 273 #endif 274 flags |= I2C_F_POLL; 275 276 KASSERT(mutex_owned(&sc->sc_lock)); 277 278 if (buflen == 0 && cmdlen == 0) 279 return EINVAL; 280 281 if ((flags & I2C_F_POLL) == 0) { 282 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 283 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 284 I2C_INTERRUPT_MASK_TIMEOUT | 285 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 286 } 287 288 const uint32_t flush_mask = 289 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 290 291 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 292 for (retry = 10000; retry > 0; retry--) { 293 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 294 if ((v & flush_mask) == 0) 295 break; 296 delay(1); 297 } 298 if (retry == 0) { 299 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 300 return EIO; 301 } 302 303 if (cmdlen > 0) { 304 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 305 buflen > 0 ? true : false); 306 if (error) { 307 goto done; 308 } 309 } 310 311 if (buflen > 0) { 312 if (I2C_OP_READ_P(op)) { 313 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 314 } else { 315 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 316 } 317 } 318 319 done: 320 if ((flags & I2C_F_POLL) == 0) { 321 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 322 } 323 324 if (error) { 325 tegra_i2c_init(sc); 326 } 327 328 return error; 329 } 330 331 static int 332 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 333 { 334 int error, retry; 335 uint32_t stat = 0; 336 337 retry = (flags & I2C_F_POLL) ? 100000 : 100; 338 339 while (--retry > 0) { 340 if ((flags & I2C_F_POLL) == 0) { 341 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 342 uimax(mstohz(10), 1)); 343 if (error) { 344 return error; 345 } 346 } 347 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 348 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 349 break; 350 } 351 if (flags & I2C_F_POLL) { 352 delay(10); 353 } 354 } 355 if (retry == 0) { 356 #ifdef TEGRA_I2C_DEBUG 357 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 358 #endif 359 return ETIMEDOUT; 360 } 361 362 const uint32_t err_mask = 363 I2C_INTERRUPT_STATUS_NOACK | 364 I2C_INTERRUPT_STATUS_ARB_LOST | 365 I2C_INTERRUPT_MASK_TIMEOUT; 366 367 if (stat & err_mask) { 368 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 369 return EIO; 370 } 371 372 return 0; 373 } 374 375 static int 376 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 377 size_t buflen, int flags, bool repeat_start) 378 { 379 const uint8_t *p = buf; 380 size_t n, resid = buflen; 381 uint32_t data; 382 int retry; 383 384 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 385 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 386 387 /* Generic Header 0 */ 388 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 389 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 390 I2C_IOPACKET_WORD0_PROTHDRSZ) | 391 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 392 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 393 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 394 I2C_IOPACKET_WORD0_PROTOCOL) | 395 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 396 I2C_IOPACKET_WORD0_PKTTYPE)); 397 /* Generic Header 1 */ 398 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 399 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 400 /* I2C Master Transmit Packet Header */ 401 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 402 I2C_IOPACKET_XMITHDR_IE | 403 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 404 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 405 406 /* Transmit data */ 407 while (resid > 0) { 408 retry = 10000; 409 while (--retry > 0) { 410 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 411 const u_int cnt = 412 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 413 if (cnt > 0) 414 break; 415 delay(10); 416 } 417 if (retry == 0) { 418 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 419 return ETIMEDOUT; 420 } 421 422 for (n = 0, data = 0; n < uimin(resid, 4); n++) { 423 data |= (uint32_t)p[n] << (n * 8); 424 } 425 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 426 p += uimin(resid, 4); 427 resid -= uimin(resid, 4); 428 } 429 430 return tegra_i2c_wait(sc, flags); 431 } 432 433 static int 434 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 435 size_t buflen, int flags) 436 { 437 uint8_t *p = buf; 438 size_t n, resid = buflen; 439 uint32_t data; 440 int retry; 441 442 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 443 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 444 445 /* Generic Header 0 */ 446 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 447 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 448 I2C_IOPACKET_WORD0_PROTHDRSZ) | 449 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 450 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 451 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 452 I2C_IOPACKET_WORD0_PROTOCOL) | 453 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 454 I2C_IOPACKET_WORD0_PKTTYPE)); 455 /* Generic Header 1 */ 456 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 457 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 458 /* I2C Master Transmit Packet Header */ 459 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 460 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 461 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 462 463 while (resid > 0) { 464 retry = 10000; 465 while (--retry > 0) { 466 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 467 const u_int cnt = 468 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 469 if (cnt > 0) 470 break; 471 delay(10); 472 } 473 if (retry == 0) { 474 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 475 return ETIMEDOUT; 476 } 477 478 data = I2C_READ(sc, I2C_RX_FIFO_REG); 479 for (n = 0; n < uimin(resid, 4); n++) { 480 p[n] = (data >> (n * 8)) & 0xff; 481 } 482 p += uimin(resid, 4); 483 resid -= uimin(resid, 4); 484 } 485 486 return tegra_i2c_wait(sc, flags); 487 } 488