1 /* $NetBSD: tegra_i2c.c,v 1.10 2015/12/16 19:46:55 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.10 2015/12/16 19:46:55 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 /* XXX */ 48 static int 49 tegra_i2c_addr2port(bus_addr_t addr) 50 { 51 switch (addr) { 52 case TEGRA_APB_BASE + TEGRA_I2C1_OFFSET: 53 return 0; 54 case TEGRA_APB_BASE + TEGRA_I2C2_OFFSET: 55 return 1; 56 case TEGRA_APB_BASE + TEGRA_I2C3_OFFSET: 57 return 2; 58 case TEGRA_APB_BASE + TEGRA_I2C4_OFFSET: 59 return 3; 60 case TEGRA_APB_BASE + TEGRA_I2C5_OFFSET: 61 return 4; 62 case TEGRA_APB_BASE + TEGRA_I2C6_OFFSET: 63 return 5; 64 default: 65 return -1; 66 } 67 } 68 69 static int tegra_i2c_match(device_t, cfdata_t, void *); 70 static void tegra_i2c_attach(device_t, device_t, void *); 71 72 static i2c_tag_t tegra_i2c_get_tag(device_t); 73 74 struct fdtbus_i2c_controller_func tegra_i2c_funcs = { 75 .get_tag = tegra_i2c_get_tag 76 }; 77 78 struct tegra_i2c_softc { 79 device_t sc_dev; 80 bus_space_tag_t sc_bst; 81 bus_space_handle_t sc_bsh; 82 void * sc_ih; 83 u_int sc_port; 84 85 struct i2c_controller sc_ic; 86 kmutex_t sc_lock; 87 kcondvar_t sc_cv; 88 device_t sc_i2cdev; 89 }; 90 91 static void tegra_i2c_init(struct tegra_i2c_softc *); 92 static int tegra_i2c_intr(void *); 93 94 static int tegra_i2c_acquire_bus(void *, int); 95 static void tegra_i2c_release_bus(void *, int); 96 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 97 size_t, void *, size_t, int); 98 99 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 100 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 101 const uint8_t *, size_t, int, bool); 102 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 103 size_t, int); 104 105 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 106 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 107 108 #define I2C_WRITE(sc, reg, val) \ 109 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 110 #define I2C_READ(sc, reg) \ 111 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 112 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 113 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 114 115 static int 116 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 117 { 118 const char * const compatible[] = { "nvidia,tegra124-i2c", NULL }; 119 struct fdt_attach_args * const faa = aux; 120 121 return of_match_compatible(faa->faa_phandle, compatible); 122 } 123 124 static void 125 tegra_i2c_attach(device_t parent, device_t self, void *aux) 126 { 127 struct tegra_i2c_softc * const sc = device_private(self); 128 struct fdt_attach_args * const faa = aux; 129 const int phandle = faa->faa_phandle; 130 struct i2cbus_attach_args iba; 131 prop_dictionary_t devs; 132 char intrstr[128]; 133 bus_addr_t addr; 134 bus_size_t size; 135 u_int address_cells; 136 int error; 137 138 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 139 aprint_error(": couldn't get registers\n"); 140 return; 141 } 142 143 sc->sc_dev = self; 144 sc->sc_bst = faa->faa_bst; 145 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 146 if (error) { 147 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 148 return; 149 } 150 sc->sc_port = tegra_i2c_addr2port(addr); 151 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 152 cv_init(&sc->sc_cv, device_xname(self)); 153 154 aprint_naive("\n"); 155 aprint_normal(": I2C%d\n", sc->sc_port + 1); 156 157 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 158 aprint_error_dev(self, "failed to decode interrupt\n"); 159 return; 160 } 161 162 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 163 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 164 if (sc->sc_ih == NULL) { 165 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 166 intrstr); 167 return; 168 } 169 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 170 171 /* 172 * Recommended setting for standard mode is to use an I2C source div 173 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 174 */ 175 tegra_car_periph_i2c_enable(sc->sc_port, 20400000); 176 177 tegra_i2c_init(sc); 178 179 sc->sc_ic.ic_cookie = sc; 180 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 181 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 182 sc->sc_ic.ic_exec = tegra_i2c_exec; 183 184 fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs); 185 186 devs = prop_dictionary_create(); 187 188 if (of_getprop_uint32(phandle, "#address-cells", &address_cells)) 189 address_cells = 1; 190 191 of_enter_i2c_devs(devs, faa->faa_phandle, address_cells * 4, 0); 192 193 iba.iba_tag = &sc->sc_ic; 194 iba.iba_child_devices = prop_dictionary_get(devs, "i2c-child-devices"); 195 if (iba.iba_child_devices != NULL) { 196 prop_object_retain(iba.iba_child_devices); 197 } else { 198 iba.iba_child_devices = prop_array_create(); 199 } 200 prop_object_release(devs); 201 202 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 203 } 204 205 static i2c_tag_t 206 tegra_i2c_get_tag(device_t dev) 207 { 208 struct tegra_i2c_softc * const sc = device_private(dev); 209 210 return &sc->sc_ic; 211 } 212 213 static void 214 tegra_i2c_init(struct tegra_i2c_softc *sc) 215 { 216 int retry = 10000; 217 218 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 219 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 220 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 221 222 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 223 I2C_WRITE(sc, I2C_CNFG_REG, 224 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 225 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 226 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 227 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 228 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 229 230 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 231 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 232 while (--retry > 0) { 233 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 234 break; 235 delay(10); 236 } 237 if (retry == 0) { 238 device_printf(sc->sc_dev, "config load timeout\n"); 239 } 240 } 241 242 static int 243 tegra_i2c_intr(void *priv) 244 { 245 struct tegra_i2c_softc * const sc = priv; 246 247 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 248 if (istatus == 0) 249 return 0; 250 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 251 252 mutex_enter(&sc->sc_lock); 253 cv_broadcast(&sc->sc_cv); 254 mutex_exit(&sc->sc_lock); 255 256 return 1; 257 } 258 259 static int 260 tegra_i2c_acquire_bus(void *priv, int flags) 261 { 262 struct tegra_i2c_softc * const sc = priv; 263 264 mutex_enter(&sc->sc_lock); 265 266 return 0; 267 } 268 269 static void 270 tegra_i2c_release_bus(void *priv, int flags) 271 { 272 struct tegra_i2c_softc * const sc = priv; 273 274 mutex_exit(&sc->sc_lock); 275 } 276 277 static int 278 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 279 size_t cmdlen, void *buf, size_t buflen, int flags) 280 { 281 struct tegra_i2c_softc * const sc = priv; 282 int retry, error; 283 284 #if notyet 285 if (cold) 286 #endif 287 flags |= I2C_F_POLL; 288 289 KASSERT(mutex_owned(&sc->sc_lock)); 290 291 if ((flags & I2C_F_POLL) == 0) { 292 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 293 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 294 I2C_INTERRUPT_MASK_TIMEOUT | 295 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 296 } 297 298 const uint32_t flush_mask = 299 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 300 301 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 302 for (retry = 10000; retry > 0; retry--) { 303 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 304 if ((v & flush_mask) == 0) 305 break; 306 delay(1); 307 } 308 if (retry == 0) { 309 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 310 return EIO; 311 } 312 313 if (cmdlen > 0) { 314 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 315 I2C_OP_READ_P(op) ? true : false); 316 if (error) { 317 goto done; 318 } 319 } 320 321 if (I2C_OP_READ_P(op)) { 322 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 323 } else { 324 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 325 } 326 327 done: 328 if ((flags & I2C_F_POLL) == 0) { 329 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 330 } 331 332 if (error) { 333 tegra_i2c_init(sc); 334 } 335 336 return error; 337 } 338 339 static int 340 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 341 { 342 int error, retry; 343 uint32_t stat = 0; 344 345 retry = (flags & I2C_F_POLL) ? 100000 : 100; 346 347 while (--retry > 0) { 348 if ((flags & I2C_F_POLL) == 0) { 349 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 350 max(mstohz(10), 1)); 351 if (error) { 352 return error; 353 } 354 } 355 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 356 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 357 break; 358 } 359 if (flags & I2C_F_POLL) { 360 delay(10); 361 } 362 } 363 if (retry == 0) { 364 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 365 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 366 return ETIMEDOUT; 367 } 368 369 const uint32_t err_mask = 370 I2C_INTERRUPT_STATUS_NOACK | 371 I2C_INTERRUPT_STATUS_ARB_LOST | 372 I2C_INTERRUPT_MASK_TIMEOUT; 373 374 if (stat & err_mask) { 375 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 376 return EIO; 377 } 378 379 return 0; 380 } 381 382 static int 383 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 384 size_t buflen, int flags, bool repeat_start) 385 { 386 const uint8_t *p = buf; 387 size_t n, resid = buflen; 388 uint32_t data; 389 int retry; 390 391 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 392 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 393 394 /* Generic Header 0 */ 395 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 396 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 397 I2C_IOPACKET_WORD0_PROTHDRSZ) | 398 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 399 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 400 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 401 I2C_IOPACKET_WORD0_PROTOCOL) | 402 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 403 I2C_IOPACKET_WORD0_PKTTYPE)); 404 /* Generic Header 1 */ 405 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 406 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 407 /* I2C Master Transmit Packet Header */ 408 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 409 I2C_IOPACKET_XMITHDR_IE | 410 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 411 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 412 413 /* Transmit data */ 414 while (resid > 0) { 415 retry = 10000; 416 while (--retry > 0) { 417 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 418 const u_int cnt = 419 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 420 if (cnt > 0) 421 break; 422 delay(10); 423 } 424 if (retry == 0) { 425 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 426 return ETIMEDOUT; 427 } 428 429 for (n = 0, data = 0; n < min(resid, 4); n++) { 430 data |= (uint32_t)p[n] << (n * 8); 431 } 432 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 433 resid -= min(resid, 4); 434 p += min(resid, 4); 435 } 436 437 return tegra_i2c_wait(sc, flags); 438 } 439 440 static int 441 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 442 size_t buflen, int flags) 443 { 444 uint8_t *p = buf; 445 size_t n, resid = buflen; 446 uint32_t data; 447 int retry; 448 449 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 450 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 451 452 /* Generic Header 0 */ 453 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 454 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 455 I2C_IOPACKET_WORD0_PROTHDRSZ) | 456 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 457 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 458 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 459 I2C_IOPACKET_WORD0_PROTOCOL) | 460 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 461 I2C_IOPACKET_WORD0_PKTTYPE)); 462 /* Generic Header 1 */ 463 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 464 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 465 /* I2C Master Transmit Packet Header */ 466 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 467 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 468 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 469 470 while (resid > 0) { 471 retry = 10000; 472 while (--retry > 0) { 473 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 474 const u_int cnt = 475 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 476 if (cnt > 0) 477 break; 478 delay(10); 479 } 480 if (retry == 0) { 481 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 482 return ETIMEDOUT; 483 } 484 485 data = I2C_READ(sc, I2C_RX_FIFO_REG); 486 for (n = 0; n < min(resid, 4); n++) { 487 p[n] = (data >> (n * 8)) & 0xff; 488 } 489 resid -= min(resid, 4); 490 p += min(resid, 4); 491 } 492 493 return tegra_i2c_wait(sc, flags); 494 } 495 496 void 497 tegra_i2c_dvc_write(uint8_t addr, uint32_t data, size_t datalen) 498 { 499 bus_space_tag_t bst = &armv7_generic_bs_tag; 500 bus_space_handle_t bsh; 501 502 bus_space_subregion(bst, tegra_apb_bsh, TEGRA_I2C5_OFFSET, 503 TEGRA_I2C5_SIZE, &bsh); 504 505 bus_space_write_4(bst, bsh, I2C_CMD_ADDR0_REG, addr << 1); 506 bus_space_write_4(bst, bsh, I2C_CMD_DATA1_REG, data); 507 bus_space_write_4(bst, bsh, I2C_CNFG_REG, 508 __SHIFTIN(datalen - 1, I2C_CNFG_LENGTH) | 509 I2C_CNFG_NEW_MASTER_FSM | 510 I2C_CNFG_SEND); 511 } 512