1 /* $NetBSD: tegra124_cpu.c,v 1.4 2017/06/02 00:09:56 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 #include "opt_multiprocessor.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra124_cpu.c,v 1.4 2017/06/02 00:09:56 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arm/cpufunc.h> 45 46 #include <arm/nvidia/tegra_reg.h> 47 #include <arm/nvidia/tegra_pmcreg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 51 #define FUSE_SKU_INFO_REG 0x010 52 #define FUSE_CPU_SPEEDO_0_REG 0x014 53 #define FUSE_CPU_IDDQ_REG 0x018 54 #define FUSE_FT_REV_REG 0x028 55 #define FUSE_CPU_SPEEDO_1_REG 0x02c 56 #define FUSE_CPU_SPEEDO_2_REG 0x030 57 #define FUSE_SOC_SPEEDO_0_REG 0x034 58 #define FUSE_SOC_SPEEDO_1_REG 0x038 59 #define FUSE_SOC_SPEEDO_2_REG 0x03c 60 #define FUSE_SOC_IDDQ_REG 0x040 61 #define FUSE_GPU_IDDQ_REG 0x128 62 63 static void tegra124_speedo_init(void); 64 static int tegra124_speedo_init_ids(uint32_t); 65 static bool tegra124_speedo_rate_ok(u_int); 66 67 static u_int tegra124_cpufreq_set_rate(u_int); 68 static u_int tegra124_cpufreq_get_rate(void); 69 static size_t tegra124_cpufreq_get_available(u_int *, size_t); 70 71 static int tegra124_cpu_match(device_t, cfdata_t, void *); 72 static void tegra124_cpu_attach(device_t, device_t, void *); 73 static int tegra124_cpu_init_cpufreq(device_t); 74 75 CFATTACH_DECL_NEW(tegra124_cpu, 0, tegra124_cpu_match, tegra124_cpu_attach, 76 NULL, NULL); 77 78 static const struct tegra_cpufreq_func tegra124_cpufreq_func = { 79 .set_rate = tegra124_cpufreq_set_rate, 80 .get_rate = tegra124_cpufreq_get_rate, 81 .get_available = tegra124_cpufreq_get_available, 82 }; 83 84 static struct tegra124_cpufreq_rate { 85 u_int rate; 86 u_int divm; 87 u_int divn; 88 u_int divp; 89 u_int uvol; 90 } tegra124_cpufreq_rates[] = { 91 { 2316, 1, 193, 0, 1360000 }, 92 { 2100, 1, 175, 0, 1260000 }, 93 { 1896, 1, 158, 0, 1180000 }, 94 { 1692, 1, 141, 0, 1100000 }, 95 { 1500, 1, 125, 0, 1020000 }, 96 { 1296, 1, 108, 0, 960000 }, 97 { 1092, 1, 91, 0, 900000 }, 98 { 900, 1, 75, 0, 840000 }, 99 { 696, 1, 58, 0, 800000 } 100 }; 101 102 static const u_int tegra124_cpufreq_max[] = { 103 2014, 104 2320, 105 2116, 106 2524 107 }; 108 109 static struct tegra124_speedo { 110 u_int cpu_speedo_id; 111 u_int soc_speedo_id; 112 u_int gpu_speedo_id; 113 } tegra124_speedo = { 114 .cpu_speedo_id = 0, 115 .soc_speedo_id = 0, 116 .gpu_speedo_id = 0 117 }; 118 119 static struct clk *tegra124_clk_pllx = NULL; 120 static struct fdtbus_regulator *tegra124_reg_vddcpu = NULL; 121 122 static int 123 tegra124_cpu_match(device_t parent, cfdata_t cf, void *aux) 124 { 125 const char * const compatible[] = { "nvidia,tegra124", NULL }; 126 struct fdt_attach_args *faa = aux; 127 128 if (OF_finddevice("/cpus/cpu@0") != faa->faa_phandle) 129 return 0; 130 131 return of_match_compatible(OF_finddevice("/"), compatible); 132 } 133 134 static void 135 tegra124_cpu_attach(device_t parent, device_t self, void *aux) 136 { 137 aprint_naive("\n"); 138 aprint_normal(": DVFS\n"); 139 140 config_finalize_register(self, tegra124_cpu_init_cpufreq); 141 } 142 143 static int 144 tegra124_cpu_init_cpufreq(device_t dev) 145 { 146 tegra124_speedo_init(); 147 148 int cpu_node = OF_finddevice("/cpus/cpu@0"); 149 if (cpu_node != -1) { 150 tegra124_clk_pllx = fdtbus_clock_get(cpu_node, "pll_x"); 151 tegra124_reg_vddcpu = fdtbus_regulator_acquire(cpu_node, 152 "vdd-cpu-supply"); 153 } 154 if (tegra124_clk_pllx == NULL) { 155 aprint_error_dev(dev, "couldn't find clock pll_x\n"); 156 return 0; 157 } 158 if (tegra124_reg_vddcpu == NULL) { 159 aprint_error_dev(dev, "couldn't find voltage regulator\n"); 160 return 0; 161 } 162 163 tegra_cpufreq_register(&tegra124_cpufreq_func); 164 165 return 0; 166 } 167 168 static void 169 tegra124_speedo_init(void) 170 { 171 uint32_t sku_id; 172 173 sku_id = tegra_fuse_read(FUSE_SKU_INFO_REG); 174 tegra124_speedo_init_ids(sku_id); 175 } 176 177 static int 178 tegra124_speedo_init_ids(uint32_t sku_id) 179 { 180 int threshold = 0; 181 182 switch (sku_id) { 183 case 0x00: 184 case 0x0f: 185 case 0x23: 186 break; /* use default */ 187 case 0x83: 188 tegra124_speedo.cpu_speedo_id = 2; 189 break; 190 case 0x1f: 191 case 0x87: 192 case 0x27: 193 tegra124_speedo.cpu_speedo_id = 2; 194 tegra124_speedo.soc_speedo_id = 0; 195 tegra124_speedo.gpu_speedo_id = 1; 196 break; 197 case 0x81: 198 case 0x21: 199 case 0x07: 200 tegra124_speedo.cpu_speedo_id = 1; 201 tegra124_speedo.soc_speedo_id = 1; 202 tegra124_speedo.gpu_speedo_id = 1; 203 threshold = 1; 204 break; 205 case 0x49: 206 case 0x4a: 207 case 0x48: 208 tegra124_speedo.cpu_speedo_id = 4; 209 tegra124_speedo.soc_speedo_id = 2; 210 tegra124_speedo.gpu_speedo_id = 3; 211 threshold = 1; 212 break; 213 default: 214 aprint_error("tegra124: unknown SKU ID %#x\n", sku_id); 215 break; /* use default */ 216 } 217 218 return threshold; 219 } 220 221 static bool 222 tegra124_speedo_rate_ok(u_int rate) 223 { 224 u_int tbl = 0; 225 226 if (tegra124_speedo.cpu_speedo_id < __arraycount(tegra124_cpufreq_max)) 227 tbl = tegra124_speedo.cpu_speedo_id; 228 229 return rate <= tegra124_cpufreq_max[tbl]; 230 } 231 232 233 static u_int 234 tegra124_cpufreq_set_rate(u_int rate) 235 { 236 const u_int nrates = __arraycount(tegra124_cpufreq_rates); 237 const struct tegra124_cpufreq_rate *r = NULL; 238 CPU_INFO_ITERATOR cii; 239 struct cpu_info *ci; 240 u_int cur_uvol; 241 int error; 242 243 if (tegra124_speedo_rate_ok(rate) == false) 244 return EINVAL; 245 246 for (int i = 0; i < nrates; i++) { 247 if (tegra124_cpufreq_rates[i].rate == rate) { 248 r = &tegra124_cpufreq_rates[i]; 249 break; 250 } 251 } 252 if (r == NULL) 253 return EINVAL; 254 255 error = fdtbus_regulator_get_voltage(tegra124_reg_vddcpu, &cur_uvol); 256 if (error != 0) 257 return error; 258 259 if (cur_uvol < r->uvol) { 260 error = fdtbus_regulator_set_voltage(tegra124_reg_vddcpu, 261 r->uvol, r->uvol); 262 if (error != 0) 263 return error; 264 } 265 266 error = clk_set_rate(tegra124_clk_pllx, r->rate * 1000000); 267 if (error == 0) { 268 rate = tegra124_cpufreq_get_rate(); 269 for (CPU_INFO_FOREACH(cii, ci)) { 270 ci->ci_data.cpu_cc_freq = rate * 1000000; 271 } 272 } 273 274 if (cur_uvol > r->uvol) { 275 (void)fdtbus_regulator_set_voltage(tegra124_reg_vddcpu, 276 r->uvol, r->uvol); 277 } 278 279 return error; 280 } 281 282 static u_int 283 tegra124_cpufreq_get_rate(void) 284 { 285 return clk_get_rate(tegra124_clk_pllx) / 1000000; 286 } 287 288 static size_t 289 tegra124_cpufreq_get_available(u_int *pavail, size_t maxavail) 290 { 291 const u_int nrates = __arraycount(tegra124_cpufreq_rates); 292 u_int n, cnt; 293 294 KASSERT(nrates <= maxavail); 295 296 for (n = 0, cnt = 0; n < nrates; n++) { 297 if (tegra124_speedo_rate_ok(tegra124_cpufreq_rates[n].rate)) { 298 pavail[cnt++] = tegra124_cpufreq_rates[n].rate; 299 } 300 } 301 302 return cnt; 303 } 304