1 /* $NetBSD: pci_machdep.c,v 1.2 2011/04/04 20:37:46 dyoung Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.2 2011/04/04 20:37:46 dyoung Exp $"); 30 31 #include "opt_mvsoc.h" 32 #include "gtpci.h" 33 #include "mvpex.h" 34 #include "pci.h" 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pciconf.h> 42 43 #include <arm/marvell/mvsocreg.h> 44 #include <arm/marvell/mvsocvar.h> 45 #include <arm/marvell/mvsocgppvar.h> 46 #if NGTPCI > 0 47 #include <dev/marvell/gtpcireg.h> 48 #include <dev/marvell/gtpcivar.h> 49 #endif 50 #if NMVPEX > 0 51 #include <dev/marvell/mvpexreg.h> 52 #include <dev/marvell/mvpexvar.h> 53 #endif 54 55 #include <machine/pci_machdep.h> 56 57 #if defined(ORION) 58 #include <arm/marvell/orionreg.h> 59 #endif 60 #if defined(KIRKWOOD) 61 #include <arm/marvell/kirkwoodreg.h> 62 #endif 63 #include <dev/marvell/marvellreg.h> 64 65 66 #if NGTPCI > 0 67 #if NGTPCI_MBUS > 0 68 static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int); 69 static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t); 70 #endif 71 static int gtpci_gpp_intr_map(const struct pci_attach_args *, 72 pci_intr_handle_t *); 73 static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t); 74 static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t); 75 static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *); 76 static void gtpci_gpp_intr_disestablish(void *, void *); 77 78 struct arm32_pci_chipset arm32_gtpci_chipset = { 79 NULL, /* conf_v */ 80 gtpci_attach_hook, 81 gtpci_bus_maxdevs, 82 gtpci_make_tag, 83 gtpci_decompose_tag, 84 #if NGTPCI_MBUS > 0 85 gtpci_mbus_conf_read, /* XXXX: always this functions */ 86 gtpci_mbus_conf_write, 87 #else 88 gtpci_conf_read, 89 gtpci_conf_write, 90 #endif 91 NULL, /* intr_v */ 92 gtpci_gpp_intr_map, 93 gtpci_gpp_intr_string, 94 gtpci_gpp_intr_evcnt, 95 gtpci_gpp_intr_establish, 96 gtpci_gpp_intr_disestablish, 97 #ifdef __HAVE_PCI_CONF_HOOK 98 gtpci_conf_hook, 99 #endif 100 }; 101 #endif 102 103 #if NMVPEX > 0 104 #if NMVPEX_MBUS > 0 105 static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int); 106 #endif 107 108 struct arm32_pci_chipset arm32_mvpex0_chipset = { 109 NULL, /* conf_v */ 110 mvpex_attach_hook, 111 mvpex_bus_maxdevs, 112 mvpex_make_tag, 113 mvpex_decompose_tag, 114 #if NMVPEX_MBUS > 0 115 mvpex_mbus_conf_read, /* XXXX: always this functions */ 116 #else 117 mvpex_conf_read, 118 #endif 119 mvpex_conf_write, 120 NULL, /* intr_v */ 121 mvpex_intr_map, 122 mvpex_intr_string, 123 mvpex_intr_evcnt, 124 mvpex_intr_establish, 125 mvpex_intr_disestablish, 126 #ifdef __HAVE_PCI_CONF_HOOK 127 mvpex_conf_hook, 128 #endif 129 }; 130 struct arm32_pci_chipset arm32_mvpex1_chipset = { 131 NULL, /* conf_v */ 132 mvpex_attach_hook, 133 mvpex_bus_maxdevs, 134 mvpex_make_tag, 135 mvpex_decompose_tag, 136 #if NMVPEX_MBUS > 0 137 mvpex_mbus_conf_read, /* XXXX: always this functions */ 138 #else 139 mvpex_conf_read, 140 #endif 141 mvpex_conf_write, 142 NULL, /* intr_v */ 143 mvpex_intr_map, 144 mvpex_intr_string, 145 mvpex_intr_evcnt, 146 mvpex_intr_establish, 147 mvpex_intr_disestablish, 148 #ifdef __HAVE_PCI_CONF_HOOK 149 mvpex_conf_hook, 150 #endif 151 }; 152 #endif 153 154 155 void 156 pci_conf_interrupt(pci_chipset_tag_t v, int bus, int dev, int pin, int swiz, 157 int *iline) 158 { 159 160 /* nothing */ 161 } 162 163 164 #if NGTPCI > 0 165 #if NGTPCI_MBUS > 0 166 #define GTPCI_MBUS_CA 0x0c78 /* Configuration Address */ 167 #define GTPCI_MBUS_CD 0x0c7c /* Configuration Data */ 168 169 static pcireg_t 170 gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg) 171 { 172 struct gtpci_softc *sc = v; 173 const pcireg_t addr = tag | reg; 174 175 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 176 addr | GTPCI_CA_CONFIGEN); 177 if ((addr | GTPCI_CA_CONFIGEN) != 178 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 179 return -1; 180 181 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD); 182 } 183 184 static void 185 gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 186 { 187 struct gtpci_softc *sc = v; 188 pcireg_t addr = tag | (reg & 0xfc); 189 190 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 191 addr | GTPCI_CA_CONFIGEN); 192 if ((addr | GTPCI_CA_CONFIGEN) != 193 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 194 return; 195 196 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data); 197 } 198 #endif /* NGTPCI_MBUS */ 199 200 /* 201 * We assume to use GPP interrupt as PCI interrupts. 202 * pci_intr_map() shall returns number of GPP between 0 and 31. However 203 * returns 0xff, because we do not know the connected pin number for GPP 204 * of your board. 205 * pci_intr_string() shall returns string "gpp <num>". 206 * pci_intr_establish() established interrupt in the pin of all GPP. 207 * Moreover, the return value will be disregarded. For instance, the 208 * setting for interrupt is not done. 209 */ 210 211 /* ARGSUSED */ 212 static int 213 gtpci_gpp_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 214 { 215 216 *ihp = pa->pa_intrpin; 217 return 0; 218 } 219 220 /* ARGSUSED */ 221 static const char * 222 gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin) 223 { 224 struct gtpci_softc *sc = v; 225 prop_array_t int2gpp; 226 prop_object_t gpp; 227 static char intrstr[8]; 228 229 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 230 gpp = prop_array_get(int2gpp, pin); 231 sprintf(intrstr, "gpp %d", (int)prop_number_integer_value(gpp)); 232 233 return intrstr; 234 } 235 236 /* ARGSUSED */ 237 static const struct evcnt * 238 gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin) 239 { 240 241 return NULL; 242 } 243 244 static void * 245 gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl, 246 int (*intrhand)(void *), void *intrarg) 247 { 248 struct gtpci_softc *sc = v; 249 prop_array_t int2gpp; 250 prop_object_t gpp; 251 int gpp_pin; 252 253 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 254 gpp = prop_array_get(int2gpp, int_pin); 255 gpp_pin = prop_number_integer_value(gpp); 256 return mvsocgpp_intr_establish(gpp_pin, ipl, 0, intrhand, intrarg); 257 } 258 259 static void 260 gtpci_gpp_intr_disestablish(void *v, void *ih) 261 { 262 263 mvsocgpp_intr_disestablish(ih); 264 } 265 #endif 266 267 #if NMVPEX_MBUS > 0 268 static pcireg_t 269 mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg) 270 { 271 struct mvpex_softc *sc = v; 272 pcireg_t addr, data, pci_cs; 273 uint32_t stat; 274 int bus, dev, func, pexbus, pexdev; 275 276 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 277 278 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 279 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 280 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 281 if (bus != pexbus || dev != pexdev) 282 if (stat & MVPEX_STAT_DLDOWN) 283 return -1; 284 285 if (bus == pexbus) { 286 if (pexdev == 0) { 287 if (dev != 1 && dev != pexdev) 288 return -1; 289 } else { 290 if (dev != 0 && dev != pexdev) 291 return -1; 292 } 293 if (func != 0) 294 return -1; 295 } 296 297 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 298 299 #if defined(ORION) 300 /* 301 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration 302 * This guideline is relevant for all devices except of the following 303 * devices: 304 * 88F5281-BO and above, and 88F5181L-A0 and above 305 */ 306 if ((bus != pexbus || dev != pexdev) && 307 !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) && 308 !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) { 309 310 /* PCI-Express configuration read work-around */ 311 /* 312 * We will use one of the Punit (AHBToMbus) windows to 313 * access the xbar and read the data from there 314 * 315 * Need to configure the 2 free Punit (AHB to MBus bridge) 316 * address decoding windows: 317 * Configure the flash Window to handle Configuration space 318 * requests for PEX0/1: 319 * 320 * Configuration transactions from the CPU should write/read 321 * the data to/from address of the form: 322 * addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1) 323 * addr[27:24]: extended register number 324 * addr[23:16]: bus number 325 * addr[15:11]: device number 326 * addr[10: 8]: function number 327 * addr[ 7: 0]: register number 328 */ 329 330 struct mvsoc_softc *soc = 331 device_private(device_parent(sc->sc_dev));; 332 bus_space_handle_t pcicfg_ioh; 333 uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size; 334 int window, target, attr, base, size, s; 335 const int pex_pcicfg_tag = 336 (sc->sc_model == MARVELL_ORION_1_88F1181) ? 337 ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM; 338 339 window = mvsoc_target(pex_pcicfg_tag, 340 &target, &attr, &base, &size); 341 if (window >= nwindow) { 342 aprint_error_dev(sc->sc_dev, 343 "can't read pcicfg space\n"); 344 return -1; 345 } 346 347 s = splhigh(); 348 349 remapl = remaph = 0; 350 if (window == 0 || window == 1) { 351 remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window)); 352 remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window)); 353 } 354 355 wc = 356 MVSOC_MLMB_WCR_WINEN | 357 MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG) | 358 MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16); 359 if (sc->sc_model == MARVELL_ORION_1_88F1181) { 360 pcicfg_addr = base; 361 pcicfg_size = size; 362 } else if (sc->sc_model == MARVELL_ORION_1_88F5182) { 363 #define PEX_PCICFG_RW_WA_BASE 0x50000000 364 #define PEX_PCICFG_RW_WA_5182_BASE 0xf0000000 365 #define PEX_PCICFG_RW_WA_SIZE (16 * 1024 * 1024) 366 pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE; 367 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 368 } else { 369 pcicfg_addr = PEX_PCICFG_RW_WA_BASE; 370 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 371 } 372 write_mlmbreg(MVSOC_MLMB_WCR(window), 373 wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size)); 374 write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr); 375 376 if (window == 0 || window == 1) { 377 write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr); 378 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 379 } 380 381 if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0, 382 &pcicfg_ioh) == 0) { 383 data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr); 384 bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size); 385 } else 386 data = -1; 387 388 write_mlmbreg(MVSOC_MLMB_WCR(window), 389 MVSOC_MLMB_WCR_WINEN | 390 MVSOC_MLMB_WCR_ATTR(attr) | 391 MVSOC_MLMB_WCR_TARGET(target) | 392 MVSOC_MLMB_WCR_SIZE(size)); 393 write_mlmbreg(MVSOC_MLMB_WBR(window), base); 394 if (window == 0 || window == 1) { 395 write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl); 396 write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph); 397 } 398 399 splx(s); 400 #else 401 if (0) { 402 #endif 403 } else { 404 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 405 addr | MVPEX_CA_CONFIGEN); 406 if ((addr | MVPEX_CA_CONFIGEN) != 407 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 408 return -1; 409 410 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 411 PCI_COMMAND_STATUS_REG); 412 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 413 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 414 415 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 416 } 417 418 return data; 419 } 420 #endif 421