1 /* $NetBSD: mvsocgpp.c,v 1.5 2012/11/21 08:03:18 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.5 2012/11/21 08:03:18 msaitoh Exp $"); 30 31 #include "gpio.h" 32 33 #define _INTR_PRIVATE 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/evcnt.h> 40 #include <sys/gpio.h> 41 #include <sys/kmem.h> 42 43 #include <machine/intr.h> 44 45 #include <arm/marvell/mvsocreg.h> 46 #include <arm/marvell/mvsocvar.h> 47 #include <arm/marvell/mvsocgppreg.h> 48 #include <arm/marvell/mvsocgppvar.h> 49 #include <arm/pic/picvar.h> 50 51 #include <dev/marvell/marvellvar.h> 52 53 #if NGPIO > 0 54 #include <sys/gpio.h> 55 #include <dev/gpio/gpiovar.h> 56 #endif 57 58 #define MVSOCGPP_DUMPREG 59 60 #define MVSOCGPP_READ(sc, reg) \ 61 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 62 #define MVSOCGPP_WRITE(sc, reg, val) \ 63 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 64 65 struct mvsocgpp_softc { 66 device_t sc_dev; 67 68 bus_space_tag_t sc_iot; 69 bus_space_handle_t sc_ioh; 70 71 struct mvsocgpp_pic { 72 struct pic_softc gpio_pic; 73 int group; 74 int shift; 75 uint32_t edge; 76 uint32_t level; 77 } *sc_pic; 78 79 #if NGPIO > 0 80 struct gpio_chipset_tag sc_gpio_chipset; 81 gpio_pin_t *sc_pins; 82 #endif 83 }; 84 85 static int mvsocgpp_match(device_t, struct cfdata *, void *); 86 static void mvsocgpp_attach(device_t, device_t, void *); 87 88 #ifdef MVSOCGPP_DUMPREG 89 static void mvsocgpp_dump_reg(struct mvsocgpp_softc *); 90 #endif 91 92 static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 93 static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t); 94 static int gpio_pic_find_pending_irqs(struct pic_softc *); 95 static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *); 96 97 static struct pic_ops gpio_pic_ops = { 98 .pic_unblock_irqs = gpio_pic_unblock_irqs, 99 .pic_block_irqs = gpio_pic_block_irqs, 100 .pic_find_pending_irqs = gpio_pic_find_pending_irqs, 101 .pic_establish_irq = gpio_pic_establish_irq, 102 }; 103 104 static struct mvsocgpp_softc *mvsocgpp_softc; /* One unit per One SoC */ 105 int gpp_irqbase = 0; 106 int gpp_npins = 0; 107 108 109 CFATTACH_DECL_NEW(mvsocgpp, sizeof(struct mvsocgpp_softc), 110 mvsocgpp_match, mvsocgpp_attach, NULL, NULL); 111 112 113 /* ARGSUSED */ 114 static int 115 mvsocgpp_match(device_t parent, struct cfdata *match, void *aux) 116 { 117 struct marvell_attach_args *mva = aux; 118 119 if (strcmp(mva->mva_name, match->cf_name) != 0) 120 return 0; 121 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 122 mva->mva_irq == MVA_IRQ_DEFAULT) 123 return 0; 124 125 mva->mva_size = MVSOC_GPP_SIZE; 126 return 1; 127 } 128 129 /* ARGSUSED */ 130 static void 131 mvsocgpp_attach(device_t parent, device_t self, void *aux) 132 { 133 struct mvsocgpp_softc *sc = device_private(self); 134 struct marvell_attach_args *mva = aux; 135 struct pic_softc *gpio_pic; 136 #if NGPIO > 0 137 struct gpiobus_attach_args gba; 138 gpio_pin_t *pins; 139 uint32_t mask, dir, valin, valout, polarity, blink; 140 #endif 141 int i, j; 142 void *ih; 143 144 dir = valin = valout = polarity = blink = 0; 145 146 aprint_normal(": Marvell SoC General Purpose I/O Port Interface\n"); 147 aprint_naive("\n"); 148 149 sc->sc_dev = self; 150 sc->sc_iot = mva->mva_iot; 151 /* Map I/O registers for oriongpp */ 152 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 153 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 154 aprint_error_dev(self, "can't map registers\n"); 155 return; 156 } 157 158 if (gpp_npins > 0) 159 aprint_normal_dev(self, "%d gpio pins\n", gpp_npins); 160 else { 161 aprint_error_dev(self, "gpp_npins not initialized\n"); 162 return; 163 } 164 165 mvsocgpp_softc = sc; 166 167 for (i = 0; i < gpp_npins; i += 32) 168 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(i), 0); 169 170 sc->sc_pic = 171 kmem_zalloc(sizeof(struct mvsocgpp_pic) * howmany(gpp_npins, 8), 172 KM_SLEEP); 173 for (i = 0, j = 0; i < gpp_npins; i += 8, j++) { 174 gpio_pic = &(sc->sc_pic + j)->gpio_pic; 175 gpio_pic->pic_ops = &gpio_pic_ops; 176 snprintf(gpio_pic->pic_name, sizeof(gpio_pic->pic_name), 177 "%s[%d:%d]", device_xname(self), i + 7, i); 178 gpio_pic->pic_maxsources = 179 (gpp_npins - i) > 8 ? 8 : gpp_npins - i; 180 pic_add(gpio_pic, gpp_irqbase + i); 181 aprint_normal_dev(self, "interrupts %d..%d", 182 gpp_irqbase + i, gpp_irqbase + i + 7); 183 ih = intr_establish(mva->mva_irq + j, 184 IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic); 185 aprint_normal(", intr %d\n", mva->mva_irq + j); 186 187 (sc->sc_pic + j)->group = j; 188 (sc->sc_pic + j)->shift = (j & 3) * 8; 189 } 190 191 #ifdef MVSOCGPP_DUMPREG 192 mvsocgpp_dump_reg(sc); 193 #endif 194 195 #if NGPIO > 0 196 sc->sc_pins = kmem_zalloc(sizeof(gpio_pin_t) * gpp_npins, KM_SLEEP); 197 198 for (i = 0, mask = 1; i < gpp_npins; i++, mask <<= 1) { 199 if ((i & (32 - 1)) == 0) { 200 mask = 1; 201 dir = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(i)); 202 valin = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(i)); 203 valout = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(i)); 204 polarity = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(i)); 205 blink = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(i)); 206 } 207 pins = &sc->sc_pins[i]; 208 pins->pin_num = i; 209 pins->pin_caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 210 GPIO_PIN_INVIN | GPIO_PIN_PULSATE); 211 if (dir & mask) { 212 pins->pin_flags = GPIO_PIN_INPUT; 213 pins->pin_state = 214 (valin & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 215 } else { 216 pins->pin_flags = GPIO_PIN_OUTPUT; 217 pins->pin_state = 218 (valout & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 219 } 220 if (polarity & mask) { 221 pins->pin_flags |= GPIO_PIN_INVIN; 222 } 223 if (blink & mask) { 224 pins->pin_flags |= GPIO_PIN_PULSATE; 225 } 226 } 227 sc->sc_gpio_chipset.gp_cookie = sc; 228 sc->sc_gpio_chipset.gp_pin_read = mvsocgpp_pin_read; 229 sc->sc_gpio_chipset.gp_pin_write = mvsocgpp_pin_write; 230 sc->sc_gpio_chipset.gp_pin_ctl = mvsocgpp_pin_ctl; 231 gba.gba_gc = &sc->sc_gpio_chipset; 232 gba.gba_pins = sc->sc_pins; 233 gba.gba_npins = gpp_npins; 234 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 235 #endif 236 } 237 238 /* 239 * arch/arm/pic functions. 240 */ 241 242 static void 243 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 244 { 245 struct mvsocgpp_softc *sc = mvsocgpp_softc; 246 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 247 uint32_t mask; 248 int pin = mvsocgpp_pic->group << 3; 249 250 irq_mask = irq_mask << mvsocgpp_pic->shift; 251 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin), 252 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask); 253 if (irq_mask & mvsocgpp_pic->edge) { 254 mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)); 255 mask |= (irq_mask & mvsocgpp_pic->edge); 256 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), mask); 257 } 258 if (irq_mask & mvsocgpp_pic->level) { 259 mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)); 260 mask |= (irq_mask & mvsocgpp_pic->level); 261 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), mask); 262 } 263 } 264 265 /* ARGSUSED */ 266 static void 267 gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 268 { 269 struct mvsocgpp_softc *sc = mvsocgpp_softc; 270 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 271 int pin = mvsocgpp_pic->group << 3; 272 273 irq_mask = irq_mask << mvsocgpp_pic->shift; 274 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), 275 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask); 276 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), 277 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)) & ~irq_mask); 278 } 279 280 static int 281 gpio_pic_find_pending_irqs(struct pic_softc *pic) 282 { 283 struct mvsocgpp_softc *sc = mvsocgpp_softc; 284 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 285 uint32_t pending; 286 int pin = mvsocgpp_pic->group << 3; 287 288 pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)); 289 pending &= (0xff << mvsocgpp_pic->shift); 290 pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) | 291 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin))); 292 pending = pending >> mvsocgpp_pic->shift; 293 294 if (pending == 0) 295 return 0; 296 297 return pic_mark_pending_sources(pic, 0, pending); 298 } 299 300 static void 301 gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is) 302 { 303 struct mvsocgpp_softc *sc = mvsocgpp_softc; 304 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 305 uint32_t im, ilm, mask; 306 int type, pin; 307 308 type = is->is_type; 309 pin = pic->pic_irqbase + is->is_irq - gpp_irqbase; 310 mask = MVSOCGPP_GPIOPIN(pin); 311 312 switch (type) { 313 case IST_LEVEL_LOW: 314 case IST_EDGE_FALLING: 315 mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT | GPIO_PIN_INVIN); 316 break; 317 318 case IST_LEVEL_HIGH: 319 case IST_EDGE_RISING: 320 mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT); 321 break; 322 323 default: 324 panic("unknwon interrupt type %d for pin %d.\n", type, pin); 325 } 326 327 im = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)); 328 ilm = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)); 329 switch (type) { 330 case IST_EDGE_FALLING: 331 case IST_EDGE_RISING: 332 im |= mask; 333 ilm &= ~mask; 334 mvsocgpp_pic->edge |= mask; 335 mvsocgpp_pic->level &= ~mask; 336 break; 337 338 case IST_LEVEL_LOW: 339 case IST_LEVEL_HIGH: 340 im &= ~mask; 341 ilm |= mask; 342 mvsocgpp_pic->edge &= ~mask; 343 mvsocgpp_pic->level |= mask; 344 break; 345 } 346 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), im); 347 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), ilm); 348 } 349 350 351 /* 352 * gpio(4) functions, and can call you. 353 */ 354 355 /* ARGSUSED */ 356 int 357 mvsocgpp_pin_read(void *arg, int pin) 358 { 359 struct mvsocgpp_softc *sc = mvsocgpp_softc; 360 uint32_t val; 361 362 KASSERT(sc != NULL); 363 364 val = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(pin)); 365 return (val & MVSOCGPP_GPIOPIN(pin)) != 0; 366 } 367 368 /* ARGSUSED */ 369 void 370 mvsocgpp_pin_write(void *arg, int pin, int value) 371 { 372 struct mvsocgpp_softc *sc = mvsocgpp_softc; 373 uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin); 374 375 KASSERT(sc != NULL); 376 377 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(pin)); 378 if (value) 379 new = old | mask; 380 else 381 new = old & ~mask; 382 if (new != old) 383 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODO(pin), new); 384 } 385 386 /* ARGSUSED */ 387 void 388 mvsocgpp_pin_ctl(void *arg, int pin, int flags) 389 { 390 struct mvsocgpp_softc *sc = mvsocgpp_softc; 391 uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin); 392 393 KASSERT(sc != NULL); 394 395 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(pin)); 396 switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 397 case GPIO_PIN_INPUT: 398 new = old | mask; 399 break; 400 401 case GPIO_PIN_OUTPUT: 402 new = old & ~mask; 403 break; 404 405 default: 406 return; 407 } 408 if (new != old) 409 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODOEC(pin), new); 410 411 /* Blink every 2^24 TCLK */ 412 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(pin)); 413 if (flags & GPIO_PIN_PULSATE) 414 new = old | mask; 415 else 416 new = old & ~mask; 417 if (new != old) 418 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOBE(pin), new); 419 420 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(pin)); 421 if (flags & GPIO_PIN_INVIN) 422 new = old | mask; 423 else 424 new = old & ~mask; 425 if (new != old) 426 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODIP(pin), new); 427 } 428 429 430 #ifdef MVSOCGPP_DUMPREG 431 static void 432 mvsocgpp_dump_reg(struct mvsocgpp_softc *sc) 433 { 434 435 aprint_normal_dev(sc->sc_dev, " Data Out: \t0x%08x\n", 436 MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(0))); 437 aprint_normal_dev(sc->sc_dev, " Data Out Enable Control: \t0x%08x\n", 438 MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(0))); 439 aprint_normal_dev(sc->sc_dev, " Data Blink Enable: \t0x%08x\n", 440 MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(0))); 441 aprint_normal_dev(sc->sc_dev, " Data In Polarity: \t0x%08x\n", 442 MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(0))); 443 aprint_normal_dev(sc->sc_dev, " Data In: \t0x%08x\n", 444 MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(0))); 445 aprint_normal_dev(sc->sc_dev, " Interrupt Cause: \t0x%08x\n", 446 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(0))); 447 aprint_normal_dev(sc->sc_dev, " Interrupt Mask: \t0x%08x\n", 448 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(0))); 449 aprint_normal_dev(sc->sc_dev, " Interrupt Level Mask: \t0x%08x\n", 450 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(0))); 451 452 if (gpp_npins <= 32) 453 return; 454 455 aprint_normal_dev(sc->sc_dev, " High Data Out: \t0x%08x\n", 456 MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(32))); 457 aprint_normal_dev(sc->sc_dev, " High Data Out Enable Ctrl:\t0x%08x\n", 458 MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(32))); 459 aprint_normal_dev(sc->sc_dev, " High Blink Enable: \t0x%08x\n", 460 MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(32))); 461 aprint_normal_dev(sc->sc_dev, " High Data In Polarity: \t0x%08x\n", 462 MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(32))); 463 aprint_normal_dev(sc->sc_dev, " High Data In: \t0x%08x\n", 464 MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(32))); 465 aprint_normal_dev(sc->sc_dev, " High Interrupt Cause: \t0x%08x\n", 466 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(32))); 467 aprint_normal_dev(sc->sc_dev, " High Interrupt Mask: \t0x%08x\n", 468 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(32))); 469 aprint_normal_dev(sc->sc_dev, " High Interrupt Level Mask:\t0x%08x\n", 470 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(32))); 471 } 472 #endif 473