1 /* $NetBSD: mvsoc.c,v 1.1 2010/10/03 05:49:24 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.1 2010/10/03 05:49:24 kiyohara Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 49 #include "locators.h" 50 51 52 static int mvsoc_match(device_t, struct cfdata *, void *); 53 static void mvsoc_attach(device_t, device_t, void *); 54 55 static int mvsoc_print(void *, const char *); 56 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 57 58 uint32_t mvPclk, mvSysclk, mvTclk = 0; 59 int nwindow = 0, nremap = 0; 60 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 61 vaddr_t mlmb_base; 62 63 void (*mvsoc_intr_init)(void); 64 65 66 /* attributes */ 67 static struct { 68 int tag; 69 uint32_t attr; 70 uint32_t target; 71 } mvsoc_tags[] = { 72 { MARVELL_TAG_SDRAM_CS0, 73 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 74 { MARVELL_TAG_SDRAM_CS1, 75 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 76 { MARVELL_TAG_SDRAM_CS2, 77 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 78 { MARVELL_TAG_SDRAM_CS3, 79 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 80 81 #if defined(ORION) 82 { ORION_TAG_DEVICE_CS0, 83 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 84 { ORION_TAG_DEVICE_CS1, 85 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 86 { ORION_TAG_DEVICE_CS2, 87 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 88 { ORION_TAG_DEVICE_BOOTCS, 89 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 90 { ORION_TAG_FLASH_CS, 91 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 92 { ORION_TAG_PEX0_MEM, 93 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX }, 94 { ORION_TAG_PEX0_IO, 95 ORION_ATTR_PEX_IO, ORION_UNITID_PEX }, 96 { ORION_TAG_PEX1_MEM, 97 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 98 { ORION_TAG_PEX1_IO, 99 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 100 { ORION_TAG_PCI_MEM, 101 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 102 { ORION_TAG_PCI_IO, 103 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 104 { ORION_TAG_CRYPT, 105 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 106 #endif 107 108 #if defined(KIRKWOOD) 109 { KIRKWOOD_TAG_NAND, 110 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 111 { KIRKWOOD_TAG_SPI, 112 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 113 { KIRKWOOD_TAG_BOOTROM, 114 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 115 { KIRKWOOD_TAG_PEX_MEM, 116 KIRKWOOD_ATTR_PEX_MEM, KIRKWOOD_UNITID_PEX }, 117 { KIRKWOOD_TAG_PEX_IO, 118 KIRKWOOD_ATTR_PEX_IO, KIRKWOOD_UNITID_PEX }, 119 { KIRKWOOD_TAG_CRYPT, 120 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 121 #endif 122 }; 123 124 #if defined(ORION) 125 #define ORION_1(m) MARVELL_ORION_1_ ## m 126 #define ORION_2(m) MARVELL_ORION_2_ ## m 127 #endif 128 #if defined(KIRKWOOD) 129 #undef KIRKWOOD 130 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 131 #endif 132 #if defined(MV78XX0) 133 #undef MV78XX0 134 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 135 #endif 136 static struct { 137 uint16_t model; 138 uint8_t rev; 139 const char *modelstr; 140 const char *revstr; 141 const char *typestr; 142 } nametbl[] = { 143 #if defined(ORION) 144 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 145 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 146 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 147 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 148 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 149 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 150 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 151 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 152 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 153 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 154 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 155 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 156 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 157 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 158 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 159 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 160 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 161 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 162 163 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 164 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 165 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 166 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 167 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 168 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 169 #endif 170 171 #if defined(KIRKWOOD) 172 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 173 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 174 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 175 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 176 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 177 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 178 #endif 179 180 #if defined(MV78XX0) 181 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 182 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 183 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 184 #endif 185 }; 186 187 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 188 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 189 static const struct mvsoc_periph { 190 int model; 191 const char *name; 192 int unit; 193 bus_size_t offset; 194 int irq; 195 } mvsoc_periphs[] = { 196 #if defined(ORION) 197 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 198 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 199 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 200 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 201 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 202 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 203 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 204 205 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 206 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 207 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 208 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 209 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 210 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 211 // { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 212 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 213 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 214 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 215 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 216 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 217 218 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 219 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 220 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 221 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 222 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 223 // { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, 0 }, 224 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 225 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 226 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 227 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 228 229 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 230 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 231 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 232 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 233 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 234 // { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 235 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 236 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 237 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 238 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 239 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 240 241 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 242 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 243 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 244 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 245 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 246 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 247 // { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 248 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 249 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 250 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 251 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 252 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 253 254 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 255 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 256 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 257 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 258 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 259 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 260 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 261 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 262 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 263 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 264 265 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 266 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 267 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 268 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 269 270 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 271 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 272 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 273 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 274 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 275 // { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 276 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 277 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 278 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 279 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 280 281 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 282 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 283 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 284 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 285 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 286 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 287 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 288 289 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 290 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 291 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 292 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 293 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 294 // { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 295 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 296 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 297 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 298 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 299 #endif 300 301 #if defined(KIRKWOOD) 302 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 303 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 304 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 305 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 306 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 307 // { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 308 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 309 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 310 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 311 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 312 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 313 314 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 315 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 316 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 317 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 318 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 319 // { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 320 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 321 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 322 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 323 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 324 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 325 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 326 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 327 328 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 329 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 330 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 331 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 332 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 333 // { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 334 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 335 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 336 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 337 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 338 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 339 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 340 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 341 #endif 342 343 #if defined(MV78XX0) 344 { MV78XX0(MV78100), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 345 { MV78XX0(MV78100), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 346 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 347 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 348 { MV78XX0(MV78100), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 349 : 350 351 { MV78XX0(MV78200), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 352 { MV78XX0(MV78200), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 353 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 354 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 355 { MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 356 : 357 #endif 358 }; 359 360 361 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 362 mvsoc_match, mvsoc_attach, NULL, NULL); 363 364 /* ARGSUSED */ 365 static int 366 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 367 { 368 369 return 1; 370 } 371 372 /* ARGSUSED */ 373 static void 374 mvsoc_attach(device_t parent, device_t self, void *aux) 375 { 376 struct mvsoc_softc *sc = device_private(self); 377 struct marvell_attach_args mva; 378 uint16_t model; 379 uint8_t rev; 380 int i; 381 382 sc->sc_dev = self; 383 sc->sc_iot = &mvsoc_bs_tag; 384 sc->sc_addr = regbase; 385 sc->sc_dmat = &mvsoc_bus_dma_tag; 386 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 387 0) { 388 aprint_error_dev(self, "can't map registers\n"); 389 return; 390 } 391 392 model = mvsoc_model(); 393 rev = mvsoc_rev(); 394 for (i = 0; i < __arraycount(nametbl); i++) 395 if (nametbl[i].model == model && nametbl[i].rev == rev) 396 break; 397 if (i >= __arraycount(nametbl)) 398 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 399 400 aprint_normal(": Marvell %s %s%s %s\n", 401 nametbl[i].modelstr, 402 nametbl[i].revstr != NULL ? "Rev. " : "", 403 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 404 nametbl[i].typestr); 405 aprint_normal("%s: CPU Clock %d.%03d MHz" 406 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 407 device_xname(self), 408 mvPclk / 1000000, (mvPclk / 1000) % 1000, 409 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 410 mvTclk / 1000000, (mvTclk / 1000) % 1000); 411 aprint_naive("\n"); 412 413 mvsoc_intr_init(); 414 415 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 416 if (mvsoc_periphs[i].model != model) 417 continue; 418 419 mva.mva_name = mvsoc_periphs[i].name; 420 mva.mva_model = model; 421 mva.mva_revision = rev; 422 mva.mva_iot = sc->sc_iot; 423 mva.mva_ioh = sc->sc_ioh; 424 mva.mva_unit = mvsoc_periphs[i].unit; 425 mva.mva_addr = sc->sc_addr; 426 mva.mva_offset = mvsoc_periphs[i].offset; 427 mva.mva_size = 0; 428 mva.mva_dmat = sc->sc_dmat; 429 mva.mva_irq = mvsoc_periphs[i].irq; 430 431 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 432 mvsoc_print, mvsoc_search); 433 } 434 } 435 436 static int 437 mvsoc_print(void *aux, const char *pnp) 438 { 439 struct marvell_attach_args *mva = aux; 440 441 if (pnp) 442 aprint_normal("%s at %s unit %d", 443 mva->mva_name, pnp, mva->mva_unit); 444 else { 445 if (mva->mva_unit != MVA_UNIT_DEFAULT) 446 aprint_normal(" unit %d", mva->mva_unit); 447 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 448 aprint_normal(" offset 0x%04lx", mva->mva_offset); 449 if (mva->mva_size > 0) 450 aprint_normal("-0x%04lx", 451 mva->mva_offset + mva->mva_size - 1); 452 } 453 if (mva->mva_irq != MVA_IRQ_DEFAULT) 454 aprint_normal(" irq %d", mva->mva_irq); 455 } 456 457 return UNCONF; 458 } 459 460 /* ARGSUSED */ 461 static int 462 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 463 { 464 465 return config_match(parent, cf, aux); 466 } 467 468 /* ARGSUSED */ 469 int 470 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 471 uint64_t *base, uint32_t *size) 472 { 473 uint32_t base32; 474 int rv; 475 476 rv = mvsoc_target(tag, target, attribute, &base32, size); 477 *base = base32; 478 if (rv == -1) 479 return -1; 480 return 0; 481 } 482 483 484 /* 485 * These functions is called before bus_space is initialized. 486 */ 487 488 void 489 mvsoc_bootstrap(bus_addr_t iobase) 490 { 491 492 regbase = iobase; 493 dsc_base = iobase + MVSOC_DSC_BASE; 494 mlmb_base = iobase + MVSOC_MLMB_BASE; 495 pex_base = iobase + MVSOC_PEX_BASE; 496 } 497 498 /* 499 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 500 */ 501 uint16_t 502 mvsoc_model() 503 { 504 /* 505 * We read product-id from vendor/device register of PCI-Express. 506 */ 507 uint32_t reg; 508 uint16_t model; 509 510 KASSERT(regbase != 0xffffffff); 511 512 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 513 model = PCI_PRODUCT(reg); 514 515 #if defined(ORION) 516 if (model == PCI_PRODUCT_MARVELL_88F5182) { 517 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 518 ORION_PMI_SAMPLE_AT_RESET); 519 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 520 model = PCI_PRODUCT_MARVELL_88F5082; 521 } 522 #endif 523 524 return model; 525 } 526 527 uint8_t 528 mvsoc_rev() 529 { 530 uint32_t reg; 531 uint8_t rev; 532 533 KASSERT(regbase != 0xffffffff); 534 535 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 536 rev = PCI_REVISION(reg); 537 538 return rev; 539 } 540 541 542 int 543 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 544 uint32_t *size) 545 { 546 int i; 547 548 KASSERT(regbase != 0xffffffff); 549 550 if (tag == MVSOC_TAG_INTERNALREG) { 551 if (target != NULL) 552 *target = 0; 553 if (attr != NULL) 554 *attr = 0; 555 if (base != NULL) 556 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 557 MVSOC_MLMB_IRBAR_BASE_MASK; 558 if (size != NULL) 559 *size = 0; 560 561 return 0; 562 } 563 564 /* sanity check */ 565 for (i = 0; i < __arraycount(mvsoc_tags); i++) 566 if (mvsoc_tags[i].tag == tag) 567 break; 568 if (i >= __arraycount(mvsoc_tags)) 569 return -1; 570 571 if (target != NULL) 572 *target = mvsoc_tags[i].target; 573 if (attr != NULL) 574 *attr = mvsoc_tags[i].attr; 575 576 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 577 /* 578 * Read DDR SDRAM Controller Address Decode Registers 579 */ 580 uint32_t baseaddrreg, sizereg; 581 int cs = 0; 582 583 switch (mvsoc_tags[i].attr) { 584 case MARVELL_ATTR_SDRAM_CS0: 585 cs = 0; 586 break; 587 case MARVELL_ATTR_SDRAM_CS1: 588 cs = 1; 589 break; 590 case MARVELL_ATTR_SDRAM_CS2: 591 cs = 2; 592 break; 593 case MARVELL_ATTR_SDRAM_CS3: 594 cs = 3; 595 break; 596 } 597 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 598 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 599 baseaddrreg = *(volatile uint32_t *)(dsc_base + 600 MVSOC_DSC_CSBAR(cs)); 601 602 if (base != NULL) 603 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 604 if (size != NULL) 605 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 606 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 607 } else { 608 if (base != NULL) 609 *base = 0; 610 if (size != NULL) 611 *size = 0; 612 } 613 return 0; 614 } else { 615 /* 616 * Read CPU Address Map Registers 617 */ 618 uint32_t basereg, ctrlreg, ta, tamask; 619 620 ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) | 621 MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr); 622 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 623 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 624 625 if (base != NULL) 626 *base = 0; 627 if (size != NULL) 628 *size = 0; 629 630 for (i = 0; i < nwindow; i++) { 631 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 632 if ((ctrlreg & tamask) != ta) 633 continue; 634 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 635 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 636 637 if (base != NULL) 638 *base = 639 basereg & MVSOC_MLMB_WBR_BASE_MASK; 640 if (size != NULL) 641 *size = (ctrlreg & 642 MVSOC_MLMB_WCR_SIZE_MASK) + 643 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 644 } 645 break; 646 } 647 return i; 648 } 649 } 650