1 /* $NetBSD: mvsoc.c,v 1.10 2012/10/19 06:14:44 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.10 2012/10/19 06:14:44 msaitoh Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 49 #include "locators.h" 50 51 #ifdef MVSOC_CONSOLE_EARLY 52 #include <dev/ic/ns16550reg.h> 53 #include <dev/ic/comreg.h> 54 #include <dev/cons.h> 55 #endif 56 57 static int mvsoc_match(device_t, struct cfdata *, void *); 58 static void mvsoc_attach(device_t, device_t, void *); 59 60 static int mvsoc_print(void *, const char *); 61 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 62 63 uint32_t mvPclk, mvSysclk, mvTclk = 0; 64 int nwindow = 0, nremap = 0; 65 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 66 vaddr_t mlmb_base; 67 68 void (*mvsoc_intr_init)(void); 69 70 71 #ifdef MVSOC_CONSOLE_EARLY 72 static vaddr_t com_base; 73 74 static inline uint32_t 75 uart_read(bus_size_t o) 76 { 77 return *(volatile uint32_t *)(com_base + (o << 2)); 78 } 79 80 static inline void 81 uart_write(bus_size_t o, uint32_t v) 82 { 83 *(volatile uint32_t *)(com_base + (o << 2)) = v; 84 } 85 86 static int 87 mvsoc_cngetc(dev_t dv) 88 { 89 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 90 return -1; 91 92 return uart_read(com_data) & 0xff; 93 } 94 95 static void 96 mvsoc_cnputc(dev_t dv, int c) 97 { 98 int timo = 150000; 99 100 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 101 ; 102 103 uart_write(com_data, c); 104 105 timo = 150000; 106 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 107 ; 108 } 109 110 static struct consdev mvsoc_earlycons = { 111 .cn_putc = mvsoc_cnputc, 112 .cn_getc = mvsoc_cngetc, 113 .cn_pollc = nullcnpollc, 114 }; 115 #endif 116 117 118 /* attributes */ 119 static struct { 120 int tag; 121 uint32_t attr; 122 uint32_t target; 123 } mvsoc_tags[] = { 124 { MARVELL_TAG_SDRAM_CS0, 125 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 126 { MARVELL_TAG_SDRAM_CS1, 127 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 128 { MARVELL_TAG_SDRAM_CS2, 129 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 130 { MARVELL_TAG_SDRAM_CS3, 131 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 132 133 #if defined(ORION) 134 { ORION_TAG_DEVICE_CS0, 135 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 136 { ORION_TAG_DEVICE_CS1, 137 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 138 { ORION_TAG_DEVICE_CS2, 139 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 140 { ORION_TAG_DEVICE_BOOTCS, 141 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 142 { ORION_TAG_FLASH_CS, 143 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 144 { ORION_TAG_PEX0_MEM, 145 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 146 { ORION_TAG_PEX0_IO, 147 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 148 { ORION_TAG_PEX1_MEM, 149 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 150 { ORION_TAG_PEX1_IO, 151 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 152 { ORION_TAG_PCI_MEM, 153 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 154 { ORION_TAG_PCI_IO, 155 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 156 { ORION_TAG_CRYPT, 157 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 158 #endif 159 160 #if defined(KIRKWOOD) 161 { KIRKWOOD_TAG_NAND, 162 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 163 { KIRKWOOD_TAG_SPI, 164 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 165 { KIRKWOOD_TAG_BOOTROM, 166 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 167 { KIRKWOOD_TAG_PEX_MEM, 168 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 169 { KIRKWOOD_TAG_PEX_IO, 170 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 171 { KIRKWOOD_TAG_PEX1_MEM, 172 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 173 { KIRKWOOD_TAG_PEX1_IO, 174 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 175 { KIRKWOOD_TAG_CRYPT, 176 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 177 #endif 178 }; 179 180 #if defined(ORION) 181 #define ORION_1(m) MARVELL_ORION_1_ ## m 182 #define ORION_2(m) MARVELL_ORION_2_ ## m 183 #endif 184 #if defined(KIRKWOOD) 185 #undef KIRKWOOD 186 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 187 #endif 188 #if defined(MV78XX0) 189 #undef MV78XX0 190 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 191 #endif 192 static struct { 193 uint16_t model; 194 uint8_t rev; 195 const char *modelstr; 196 const char *revstr; 197 const char *typestr; 198 } nametbl[] = { 199 #if defined(ORION) 200 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 201 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 202 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 203 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 204 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 205 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 206 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 207 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 208 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 209 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 210 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 211 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 212 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 213 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 214 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 215 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 216 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 217 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 218 219 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 220 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 221 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 222 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 223 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 224 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 225 #endif 226 227 #if defined(KIRKWOOD) 228 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 229 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 230 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 231 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 232 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 233 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 234 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 235 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 236 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 237 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 238 #endif 239 240 #if defined(MV78XX0) 241 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 242 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 243 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 244 #endif 245 }; 246 247 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 248 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 249 static const struct mvsoc_periph { 250 int model; 251 const char *name; 252 int unit; 253 bus_size_t offset; 254 int irq; 255 uint32_t clkpwr_bit; 256 } mvsoc_periphs[] = { 257 #if defined(ORION) 258 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 259 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 260 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 261 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 262 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 263 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 264 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 265 266 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 267 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 268 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 269 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 270 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 271 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 272 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 273 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 274 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 275 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 276 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 277 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 278 279 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 280 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 281 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 282 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 283 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 284 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 285 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 286 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 287 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 288 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 289 290 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 291 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 292 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 293 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 294 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 295 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 296 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 297 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 298 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 299 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 300 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 301 302 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 303 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 304 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 305 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 306 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 307 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 308 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 309 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 310 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 311 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 312 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 313 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 314 315 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 316 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 317 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 318 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 319 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 320 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 321 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 322 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 323 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 324 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 325 326 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 327 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 328 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 329 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 330 331 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 332 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 333 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 334 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 335 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 336 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 337 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 338 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 339 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 340 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 341 342 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 343 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 344 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 345 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 346 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 347 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 348 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 349 350 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 351 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 352 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 353 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 354 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 355 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 356 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 357 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 358 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 359 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 360 #endif 361 362 #if defined(KIRKWOOD) 363 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 364 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 365 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 366 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 367 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 368 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 369 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 370 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 371 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 372 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 373 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 374 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 375 376 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 377 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 378 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 379 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 380 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 381 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 382 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 383 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 384 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 385 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 386 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 387 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 388 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 389 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 390 391 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 392 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 393 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 394 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 395 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 396 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT, 397 MVSOC_MLMB_CLKGATING_BIT(3) }, 398 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 399 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 400 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT, 401 MVSOC_MLMB_CLKGATING_BIT(17) }, 402 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT, 403 MVSOC_MLMB_CLKGATING_BIT(0) }, 404 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT, 405 MVSOC_MLMB_CLKGATING_BIT(19) }, 406 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT, 407 MVSOC_MLMB_CLKGATING_BIT(2) }, 408 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA, 409 MVSOC_MLMB_CLKGATING_BIT(14) | 410 MVSOC_MLMB_CLKGATING_BIT(15) }, 411 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT, 412 MVSOC_MLMB_CLKGATING_BIT(4) }, 413 414 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 415 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 416 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 417 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 418 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 419 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 420 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 421 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 422 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 423 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 424 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 425 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 426 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 427 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 428 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 429 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 430 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 431 #endif 432 433 #if defined(MV78XX0) 434 { MV78XX0(MV78100), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 435 { MV78XX0(MV78100), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 436 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 437 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 438 { MV78XX0(MV78100), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 439 : 440 441 { MV78XX0(MV78200), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 442 { MV78XX0(MV78200), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 443 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 444 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 445 { MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 446 : 447 #endif 448 }; 449 450 451 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 452 mvsoc_match, mvsoc_attach, NULL, NULL); 453 454 /* ARGSUSED */ 455 static int 456 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 457 { 458 459 return 1; 460 } 461 462 /* ARGSUSED */ 463 static void 464 mvsoc_attach(device_t parent, device_t self, void *aux) 465 { 466 struct mvsoc_softc *sc = device_private(self); 467 struct marvell_attach_args mva; 468 uint16_t model; 469 uint8_t rev; 470 uint32_t clkpwr, clkpwrbit; 471 int i; 472 473 sc->sc_dev = self; 474 sc->sc_iot = &mvsoc_bs_tag; 475 sc->sc_addr = regbase; 476 sc->sc_dmat = &mvsoc_bus_dma_tag; 477 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 478 0) { 479 aprint_error_dev(self, "can't map registers\n"); 480 return; 481 } 482 483 model = mvsoc_model(); 484 rev = mvsoc_rev(); 485 for (i = 0; i < __arraycount(nametbl); i++) 486 if (nametbl[i].model == model && nametbl[i].rev == rev) 487 break; 488 if (i >= __arraycount(nametbl)) 489 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 490 491 aprint_normal(": Marvell %s %s%s %s\n", 492 nametbl[i].modelstr, 493 nametbl[i].revstr != NULL ? "Rev. " : "", 494 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 495 nametbl[i].typestr); 496 aprint_normal("%s: CPU Clock %d.%03d MHz" 497 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 498 device_xname(self), 499 mvPclk / 1000000, (mvPclk / 1000) % 1000, 500 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 501 mvTclk / 1000000, (mvTclk / 1000) % 1000); 502 aprint_naive("\n"); 503 504 mvsoc_intr_init(); 505 506 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 507 if (mvsoc_periphs[i].model != model) 508 continue; 509 510 /* Skip clock disabled devices */ 511 clkpwrbit = mvsoc_periphs[i].clkpwr_bit; 512 if (clkpwrbit != 0) { 513 clkpwr = read_mlmbreg(MVSOC_MLMB_CLKGATING); 514 515 if ((clkpwr & clkpwrbit) == 0) { 516 aprint_normal("%s: %s%d clock disabled\n", 517 device_xname(self), 518 mvsoc_periphs[i].name, 519 mvsoc_periphs[i].unit); 520 continue; 521 } 522 } 523 524 mva.mva_name = mvsoc_periphs[i].name; 525 mva.mva_model = model; 526 mva.mva_revision = rev; 527 mva.mva_iot = sc->sc_iot; 528 mva.mva_ioh = sc->sc_ioh; 529 mva.mva_unit = mvsoc_periphs[i].unit; 530 mva.mva_addr = sc->sc_addr; 531 mva.mva_offset = mvsoc_periphs[i].offset; 532 mva.mva_size = 0; 533 mva.mva_dmat = sc->sc_dmat; 534 mva.mva_irq = mvsoc_periphs[i].irq; 535 536 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 537 mvsoc_print, mvsoc_search); 538 } 539 } 540 541 static int 542 mvsoc_print(void *aux, const char *pnp) 543 { 544 struct marvell_attach_args *mva = aux; 545 546 if (pnp) 547 aprint_normal("%s at %s unit %d", 548 mva->mva_name, pnp, mva->mva_unit); 549 else { 550 if (mva->mva_unit != MVA_UNIT_DEFAULT) 551 aprint_normal(" unit %d", mva->mva_unit); 552 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 553 aprint_normal(" offset 0x%04lx", mva->mva_offset); 554 if (mva->mva_size > 0) 555 aprint_normal("-0x%04lx", 556 mva->mva_offset + mva->mva_size - 1); 557 } 558 if (mva->mva_irq != MVA_IRQ_DEFAULT) 559 aprint_normal(" irq %d", mva->mva_irq); 560 } 561 562 return UNCONF; 563 } 564 565 /* ARGSUSED */ 566 static int 567 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 568 { 569 570 return config_match(parent, cf, aux); 571 } 572 573 /* ARGSUSED */ 574 int 575 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 576 uint64_t *base, uint32_t *size) 577 { 578 uint32_t base32; 579 int rv; 580 581 rv = mvsoc_target(tag, target, attribute, &base32, size); 582 *base = base32; 583 if (rv == -1) 584 return -1; 585 return 0; 586 } 587 588 589 /* 590 * These functions is called before bus_space is initialized. 591 */ 592 593 void 594 mvsoc_bootstrap(bus_addr_t iobase) 595 { 596 597 regbase = iobase; 598 dsc_base = iobase + MVSOC_DSC_BASE; 599 mlmb_base = iobase + MVSOC_MLMB_BASE; 600 pex_base = iobase + MVSOC_PEX_BASE; 601 #ifdef MVSOC_CONSOLE_EARLY 602 com_base = iobase + MVSOC_COM0_BASE; 603 cn_tab = &mvsoc_earlycons; 604 printf("Hello\n"); 605 #endif 606 } 607 608 /* 609 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 610 */ 611 uint16_t 612 mvsoc_model(void) 613 { 614 /* 615 * We read product-id from vendor/device register of PCI-Express. 616 */ 617 uint32_t reg; 618 uint16_t model; 619 620 KASSERT(regbase != 0xffffffff); 621 622 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 623 model = PCI_PRODUCT(reg); 624 625 #if defined(ORION) 626 if (model == PCI_PRODUCT_MARVELL_88F5182) { 627 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 628 ORION_PMI_SAMPLE_AT_RESET); 629 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 630 model = PCI_PRODUCT_MARVELL_88F5082; 631 } 632 #endif 633 634 return model; 635 } 636 637 uint8_t 638 mvsoc_rev(void) 639 { 640 uint32_t reg; 641 uint8_t rev; 642 643 KASSERT(regbase != 0xffffffff); 644 645 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 646 rev = PCI_REVISION(reg); 647 648 return rev; 649 } 650 651 652 int 653 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 654 uint32_t *size) 655 { 656 int i; 657 658 KASSERT(regbase != 0xffffffff); 659 660 if (tag == MVSOC_TAG_INTERNALREG) { 661 if (target != NULL) 662 *target = 0; 663 if (attr != NULL) 664 *attr = 0; 665 if (base != NULL) 666 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 667 MVSOC_MLMB_IRBAR_BASE_MASK; 668 if (size != NULL) 669 *size = 0; 670 671 return 0; 672 } 673 674 /* sanity check */ 675 for (i = 0; i < __arraycount(mvsoc_tags); i++) 676 if (mvsoc_tags[i].tag == tag) 677 break; 678 if (i >= __arraycount(mvsoc_tags)) 679 return -1; 680 681 if (target != NULL) 682 *target = mvsoc_tags[i].target; 683 if (attr != NULL) 684 *attr = mvsoc_tags[i].attr; 685 686 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 687 /* 688 * Read DDR SDRAM Controller Address Decode Registers 689 */ 690 uint32_t baseaddrreg, sizereg; 691 int cs = 0; 692 693 switch (mvsoc_tags[i].attr) { 694 case MARVELL_ATTR_SDRAM_CS0: 695 cs = 0; 696 break; 697 case MARVELL_ATTR_SDRAM_CS1: 698 cs = 1; 699 break; 700 case MARVELL_ATTR_SDRAM_CS2: 701 cs = 2; 702 break; 703 case MARVELL_ATTR_SDRAM_CS3: 704 cs = 3; 705 break; 706 } 707 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 708 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 709 baseaddrreg = *(volatile uint32_t *)(dsc_base + 710 MVSOC_DSC_CSBAR(cs)); 711 712 if (base != NULL) 713 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 714 if (size != NULL) 715 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 716 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 717 } else { 718 if (base != NULL) 719 *base = 0; 720 if (size != NULL) 721 *size = 0; 722 } 723 return 0; 724 } else { 725 /* 726 * Read CPU Address Map Registers 727 */ 728 uint32_t basereg, ctrlreg, ta, tamask; 729 730 ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) | 731 MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr); 732 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 733 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 734 735 if (base != NULL) 736 *base = 0; 737 if (size != NULL) 738 *size = 0; 739 740 for (i = 0; i < nwindow; i++) { 741 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 742 if ((ctrlreg & tamask) != ta) 743 continue; 744 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 745 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 746 747 if (base != NULL) 748 *base = 749 basereg & MVSOC_MLMB_WBR_BASE_MASK; 750 if (size != NULL) 751 *size = (ctrlreg & 752 MVSOC_MLMB_WCR_SIZE_MASK) + 753 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 754 } 755 break; 756 } 757 return i; 758 } 759 } 760