1*0a668ec7Spho /* $NetBSD: cpu_mainbus.c,v 1.19 2024/05/09 12:41:08 pho Exp $ */
21a5fe5b5Smatt
31a5fe5b5Smatt /*
41a5fe5b5Smatt * Copyright (c) 1995 Mark Brinicombe.
51a5fe5b5Smatt * Copyright (c) 1995 Brini.
61a5fe5b5Smatt * All rights reserved.
71a5fe5b5Smatt *
81a5fe5b5Smatt * Redistribution and use in source and binary forms, with or without
91a5fe5b5Smatt * modification, are permitted provided that the following conditions
101a5fe5b5Smatt * are met:
111a5fe5b5Smatt * 1. Redistributions of source code must retain the above copyright
121a5fe5b5Smatt * notice, this list of conditions and the following disclaimer.
131a5fe5b5Smatt * 2. Redistributions in binary form must reproduce the above copyright
141a5fe5b5Smatt * notice, this list of conditions and the following disclaimer in the
151a5fe5b5Smatt * documentation and/or other materials provided with the distribution.
161a5fe5b5Smatt * 3. All advertising materials mentioning features or use of this software
171a5fe5b5Smatt * must display the following acknowledgement:
181a5fe5b5Smatt * This product includes software developed by Brini.
191a5fe5b5Smatt * 4. The name of the company nor the name of the author may be used to
201a5fe5b5Smatt * endorse or promote products derived from this software without specific
211a5fe5b5Smatt * prior written permission.
221a5fe5b5Smatt *
231a5fe5b5Smatt * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
241a5fe5b5Smatt * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
251a5fe5b5Smatt * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
261a5fe5b5Smatt * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
271a5fe5b5Smatt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
281a5fe5b5Smatt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
291a5fe5b5Smatt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
301a5fe5b5Smatt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
311a5fe5b5Smatt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
321a5fe5b5Smatt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
331a5fe5b5Smatt * SUCH DAMAGE.
341a5fe5b5Smatt *
351a5fe5b5Smatt * RiscBSD kernel project
361a5fe5b5Smatt *
371a5fe5b5Smatt * cpu.c
381a5fe5b5Smatt *
391a5fe5b5Smatt * Probing and configuration for the master cpu
401a5fe5b5Smatt *
411a5fe5b5Smatt * Created : 10/10/95
421a5fe5b5Smatt */
431a5fe5b5Smatt
442ea33784Smatt #include "locators.h"
45cd0fc78fSskrll #include "opt_multiprocessor.h"
462ea33784Smatt
4708716eaeSlukem #include <sys/cdefs.h>
48*0a668ec7Spho __KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.19 2024/05/09 12:41:08 pho Exp $");
4908716eaeSlukem
501a5fe5b5Smatt #include <sys/param.h>
51e1281176Sskrll #include <sys/types.h>
521a5fe5b5Smatt #include <sys/systm.h>
532ea33784Smatt #include <sys/cpu.h>
541a5fe5b5Smatt #include <sys/device.h>
551a5fe5b5Smatt #include <sys/proc.h>
562ea33784Smatt
57e1281176Sskrll #include <arm/cpuvar.h>
582ea33784Smatt #include <arm/mainbus/mainbus.h>
591a5fe5b5Smatt
601a5fe5b5Smatt /*
61e3a3a9f5Schris * Prototypes
62e3a3a9f5Schris */
63612b7ee5Smatt static int cpu_mainbus_match(device_t, cfdata_t, void *);
64612b7ee5Smatt static void cpu_mainbus_attach(device_t, device_t, void *);
65e3a3a9f5Schris
66e3a3a9f5Schris /*
67612b7ee5Smatt * int cpumatch(device_t parent, cfdata_t cf, void *aux)
681a5fe5b5Smatt *
691a5fe5b5Smatt * Probe for the main cpu. Currently all this does is return 1 to
701a5fe5b5Smatt * indicate that the cpu was found.
711a5fe5b5Smatt */
72e1281176Sskrll #ifndef MULTIPROCESSOR
732b3dd61aSmatt #define arm_cpu_max 1
742ea33784Smatt #endif
751a5fe5b5Smatt
761a5fe5b5Smatt static int
cpu_mainbus_match(device_t parent,cfdata_t cf,void * aux)77612b7ee5Smatt cpu_mainbus_match(device_t parent, cfdata_t cf, void *aux)
781a5fe5b5Smatt {
792ea33784Smatt struct mainbus_attach_args * const mb = aux;
802ea33784Smatt int id = mb->mb_core;
812ea33784Smatt
822ea33784Smatt if (id != MAINBUSCF_CORE_DEFAULT) {
8395c1bdefSmatt if (id == 0)
84e1281176Sskrll return cpu_info_store[0].ci_dev == NULL;
8595c1bdefSmatt if (id >= arm_cpu_max)
862ea33784Smatt return 0;
8795c1bdefSmatt #ifdef MULTIPROCESSOR
8895c1bdefSmatt if (cpu_info[id] != NULL)
892ea33784Smatt return 0;
9095c1bdefSmatt #endif
912ea33784Smatt return 1;
922ea33784Smatt }
932ea33784Smatt
94e1281176Sskrll if (cpu_info_store[0].ci_dev == NULL) {
9595c1bdefSmatt mb->mb_core = 0;
9695c1bdefSmatt return 1;
9795c1bdefSmatt }
9895c1bdefSmatt
992ea33784Smatt #ifdef MULTIPROCESSOR
10095c1bdefSmatt for (id = 1; id < arm_cpu_max; id++) {
10195c1bdefSmatt if (cpu_info[id] != NULL)
1022ea33784Smatt continue;
1032ea33784Smatt mb->mb_core = id;
1042ea33784Smatt return 1;
1052ea33784Smatt }
10695c1bdefSmatt #endif
10795c1bdefSmatt
1082ea33784Smatt return 0;
1091a5fe5b5Smatt }
1101a5fe5b5Smatt
1111a5fe5b5Smatt /*
112612b7ee5Smatt * void cpusattach(device_t parent, device_t dev, void *aux)
1131a5fe5b5Smatt *
1141a5fe5b5Smatt * Attach the main cpu
1151a5fe5b5Smatt */
1161a5fe5b5Smatt
1171a5fe5b5Smatt static void
cpu_mainbus_attach(device_t parent,device_t self,void * aux)118612b7ee5Smatt cpu_mainbus_attach(device_t parent, device_t self, void *aux)
1191a5fe5b5Smatt {
1202ea33784Smatt struct mainbus_attach_args * const mb = aux;
1212ea33784Smatt
1222ea33784Smatt cpu_attach(self, mb->mb_core);
1231a5fe5b5Smatt }
1241a5fe5b5Smatt
125*0a668ec7Spho CFATTACH_DECL2_NEW(cpu_mainbus, 0,
126*0a668ec7Spho cpu_mainbus_match, cpu_mainbus_attach, NULL, NULL,
127*0a668ec7Spho cpu_rescan, cpu_childdetached);
128