1 /* $NetBSD: ixp12x0_pci.c,v 1.17 2020/07/07 03:38:46 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA and Naoto Shimazaki. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.17 2020/07/07 03:38:46 thorpej Exp $"); 33 34 /* 35 * PCI configuration support for IXP12x0 Network Processor chip. 36 */ 37 38 #include "opt_pci.h" 39 #include "pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <arm/ixp12x0/ixp12x0reg.h> 49 #include <arm/ixp12x0/ixp12x0var.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pciconf.h> 54 55 #include <arm/locore.h> 56 57 void ixp12x0_pci_attach_hook(device_t, device_t, 58 struct pcibus_attach_args *); 59 int ixp12x0_pci_bus_maxdevs(void *, int); 60 pcitag_t ixp12x0_pci_make_tag(void *, int, int, int); 61 void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 62 pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int); 63 void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t); 64 void ixp12x0_pci_conf_interrupt(void *, int, int, int, int, int *); 65 66 static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int); 67 68 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 69 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 70 71 #define MAX_PCI_DEVICES 4 72 73 /* 74 * IXM1200 PCI configuration Cycles 75 * Device Address 76 * ------------------------------------- 77 * 0 IXP1200 0x0800 - 0x08FF 78 * 1 i21555 0x1000 - 0x10FF 79 * 2 i82559 0x2000 - 0x20FF 80 * 3 PMC expansion 0x4000 - 0x40FF 81 */ 82 83 void 84 ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie) 85 { 86 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 87 struct ixp12x0_softc *sc = cookie; 88 #endif 89 pc->pc_conf_v = cookie; 90 pc->pc_attach_hook = ixp12x0_pci_attach_hook; 91 pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs; 92 pc->pc_make_tag = ixp12x0_pci_make_tag; 93 pc->pc_decompose_tag = ixp12x0_pci_decompose_tag; 94 pc->pc_conf_read = ixp12x0_pci_conf_read; 95 pc->pc_conf_write = ixp12x0_pci_conf_write; 96 pc->pc_conf_interrupt = ixp12x0_pci_conf_interrupt; 97 98 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 99 struct pciconf_resources *pcires = pciconf_resource_init(); 100 101 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 102 0, IXP12X0_PCI_IO_SIZE); 103 104 /* PCI MEM space is mapped same address as real memory */ 105 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 106 IXP12X0_PCI_MEM_HWBASE, IXP12X0_PCI_MEM_SIZE); 107 108 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 109 pci_configure_bus(pc, pcires, 0 /* XXX bus = 0 */, 110 arm_dcache_align); 111 112 pciconf_resource_fini(pcires); 113 #endif 114 } 115 116 void 117 ixp12x0_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 118 { 119 /* Nothing */ 120 } 121 122 void 123 ixp12x0_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 124 { 125 /* Nothing to do. */ 126 } 127 128 int 129 ixp12x0_pci_bus_maxdevs(void *v, int busno) 130 { 131 return(MAX_PCI_DEVICES); 132 } 133 134 pcitag_t 135 ixp12x0_pci_make_tag(void *v, int bus, int device, int function) 136 { 137 #ifdef PCI_DEBUG 138 printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 139 v, bus, device, function); 140 #endif 141 return ((bus << 16) | (device << 11) | (function << 8)); 142 } 143 144 void 145 ixp12x0_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep, int *functionp) 146 { 147 #ifdef PCI_DEBUG 148 printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 149 v, tag, (int)busp, (int)devicep, (int)functionp); 150 #endif 151 152 if (busp != NULL) 153 *busp = (tag >> 16) & 0xff; 154 if (devicep != NULL) 155 *devicep = (tag >> 11) & 0x1f; 156 if (functionp != NULL) 157 *functionp = (tag >> 8) & 0x7; 158 } 159 160 static vaddr_t 161 ixp12x0_pci_conf_setup(void *v, struct ixp12x0_softc *sc, pcitag_t tag, int offset) 162 { 163 int bus, device, function; 164 vaddr_t addr; 165 166 if ((unsigned int)offset >= PCI_CONF_SIZE) 167 return 0; 168 169 ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function); 170 171 if (bus == 0) { 172 /* configuration type 0 */ 173 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 174 ((1 << (device + 10)) | (offset & ~3)); 175 } else { 176 /* configuration type 1 */ 177 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf1_ioh) + 178 ((bus << 16) | (device << 11) | 179 (function << 8) | (offset & ~3) | 1); 180 } 181 return addr; 182 } 183 184 pcireg_t 185 ixp12x0_pci_conf_read(void *v, pcitag_t tag, int offset) 186 { 187 struct ixp12x0_softc *sc = v; 188 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 189 pcireg_t rv; 190 int s; 191 192 #ifdef PCI_DEBUG 193 printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n", 194 sc->sc_conf0_ioh, va, tag, offset); 195 #endif 196 if (va == 0) 197 return -1; 198 199 PCI_CONF_LOCK(s); 200 201 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 202 #ifdef PCI_DEBUG 203 printf("conf_read: %lx bad address\n", va); 204 #endif 205 rv = (pcireg_t) - 1; 206 } 207 208 PCI_CONF_UNLOCK(s); 209 210 return rv; 211 } 212 213 void 214 ixp12x0_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 215 { 216 struct ixp12x0_softc *sc = v; 217 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 218 int s; 219 220 #ifdef PCI_DEBUG 221 printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n", 222 tag, offset, va, sc->sc_conf0_ioh); 223 #endif 224 225 PCI_CONF_LOCK(s); 226 227 *(pcireg_t *) va = val; 228 229 PCI_CONF_UNLOCK(s); 230 } 231