xref: /netbsd-src/sys/arch/arm/iomd/iomd_irqhandler.c (revision fad4c9f71477ae11cea2ee75ec82151ac770a534)
1 /*	$NetBSD: iomd_irqhandler.c,v 1.10 2006/05/11 12:05:37 yamt Exp $	*/
2 
3 /*
4  * Copyright (c) 1994-1998 Mark Brinicombe.
5  * Copyright (c) 1994 Brini.
6  * All rights reserved.
7  *
8  * This code is derived from software written for Brini by Mark Brinicombe
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by Mark Brinicombe
21  *	for the NetBSD Project.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
28  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
30  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37  * IRQ/FIQ initialisation, claim, release and handler routines
38  *
39  *	from: irqhandler.c,v 1.14 1997/04/02 21:52:19 christos Exp $
40  */
41 
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: iomd_irqhandler.c,v 1.10 2006/05/11 12:05:37 yamt Exp $");
44 
45 #include "opt_irqstats.h"
46 
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/syslog.h>
50 #include <sys/malloc.h>
51 #include <uvm/uvm_extern.h>
52 
53 #include <arm/iomd/iomdreg.h>
54 #include <arm/iomd/iomdvar.h>
55 
56 #include <machine/intr.h>
57 #include <machine/cpu.h>
58 #include <arm/arm32/katelib.h>
59 
60 irqhandler_t *irqhandlers[NIRQS];
61 
62 int current_intr_depth;
63 u_int current_mask;
64 u_int actual_mask;
65 u_int disabled_mask;
66 u_int spl_mask;
67 u_int irqmasks[IPL_LEVELS];
68 
69 extern u_int soft_interrupts;	/* Only so we can initialise it */
70 
71 extern char *_intrnames;
72 
73 /* Prototypes */
74 
75 extern void set_spl_masks	__P((void));
76 
77 /*
78  * void irq_init(void)
79  *
80  * Initialise the IRQ/FIQ sub system
81  */
82 
83 void
84 irq_init()
85 {
86 	int loop;
87 
88 	/* Clear all the IRQ handlers and the irq block masks */
89 	for (loop = 0; loop < NIRQS; ++loop) {
90 		irqhandlers[loop] = NULL;
91 	}
92 
93 	/* Clear the IRQ/FIQ masks in the IOMD */
94 	IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00);
95 	IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00);
96 
97 	switch (IOMD_ID) {
98 	case RPC600_IOMD_ID:
99 		break;
100 	case ARM7500_IOC_ID:
101 	case ARM7500FE_IOC_ID:
102 		IOMD_WRITE_BYTE(IOMD_IRQMSKC, 0x00);
103 		IOMD_WRITE_BYTE(IOMD_IRQMSKD, 0x00);
104 		break;
105 	default:
106 		printf("Unknown IOMD id (%d) found in irq_init()\n", IOMD_ID);
107 	};
108 
109 	IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
110 	IOMD_WRITE_BYTE(IOMD_DMAMSK, 0x00);
111 
112 	/*
113 	 * Setup the irqmasks for the different Interrupt Priority Levels
114 	 * We will start with no bits set and these will be updated as handlers
115 	 * are installed at different IPL's.
116 	 */
117 	for (loop = 0; loop < IPL_LEVELS; ++loop)
118 		irqmasks[loop] = 0;
119 
120 	current_intr_depth = 0;
121 	current_mask = 0x00000000;
122 	disabled_mask = 0x00000000;
123 	actual_mask = 0x00000000;
124 	spl_mask = 0x00000000;
125 	soft_interrupts = 0x00000000;
126 
127 	set_spl_masks();
128 
129 	/* Enable IRQ's and FIQ's */
130 	enable_interrupts(I32_bit | F32_bit);
131 }
132 
133 
134 /*
135  * int irq_claim(int irq, irqhandler_t *handler)
136  *
137  * Enable an IRQ and install a handler for it.
138  */
139 
140 int
141 irq_claim(irq, handler)
142 	int irq;
143 	irqhandler_t *handler;
144 {
145 	int level;
146 	u_int oldirqstate;
147 
148 #ifdef DIAGNOSTIC
149 	/* Sanity check */
150 	if (handler == NULL)
151 		panic("NULL interrupt handler");
152 	if (handler->ih_func == NULL)
153 		panic("Interrupt handler does not have a function");
154 #endif	/* DIAGNOSTIC */
155 
156 	/*
157 	 * IRQ_INSTRUCT indicates that we should get the irq number
158 	 * from the irq structure
159 	 */
160 	if (irq == IRQ_INSTRUCT)
161 		irq = handler->ih_num;
162 
163 	/* Make sure the irq number is valid */
164 	if (irq < 0 || irq >= NIRQS)
165 		return(-1);
166 
167 	/* Make sure the level is valid */
168 	if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS)
169     	        return(-1);
170 
171 	oldirqstate = disable_interrupts(I32_bit);
172 
173 	/* Attach handler at top of chain */
174 	handler->ih_next = irqhandlers[irq];
175 	irqhandlers[irq] = handler;
176 
177 	/*
178 	 * Reset the flags for this handler.
179 	 * As the handler is now in the chain mark it as active.
180 	 */
181 	handler->ih_flags = 0 | IRQ_FLAG_ACTIVE;
182 
183 	/*
184 	 * Record the interrupt number for accounting.
185 	 * Done here as the accounting number may not be the same as the
186 	 * IRQ number though for the moment they are
187 	 */
188 	handler->ih_num = irq;
189 
190 #ifdef IRQSTATS
191 	/* Get the interrupt name from the head of the list */
192 	if (handler->ih_name) {
193 		char *ptr = _intrnames + (irq * 14);
194 		strcpy(ptr, "             ");
195 		strncpy(ptr, handler->ih_name,
196 		    min(strlen(handler->ih_name), 13));
197 	} else {
198 		char *ptr = _intrnames + (irq * 14);
199 		sprintf(ptr, "irq %2d     ", irq);
200 	}
201 #endif	/* IRQSTATS */
202 
203 	/*
204 	 * Update the irq masks.
205 	 * Find the lowest interrupt priority on the irq chain.
206 	 * Interrupt is allowable at priorities lower than this.
207 	 * If ih_level is out of range then don't bother to update
208 	 * the masks.
209 	 */
210 	if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) {
211 		irqhandler_t *ptr;
212 
213 		/*
214 		 * Find the lowest interrupt priority on the irq chain.
215 		 * Interrupt is allowable at priorities lower than this.
216 		 */
217 		ptr = irqhandlers[irq];
218 		if (ptr) {
219 			int max_level;
220 
221 			level = ptr->ih_level - 1;
222 			max_level = ptr->ih_level - 1;
223 			while (ptr) {
224 				if (ptr->ih_level - 1 < level)
225 					level = ptr->ih_level - 1;
226 				else if (ptr->ih_level - 1 > max_level)
227 					max_level = ptr->ih_level - 1;
228 				ptr = ptr->ih_next;
229 			}
230 			/* Clear out any levels that we cannot now allow */
231 			while (max_level >=0 && max_level > level) {
232 				irqmasks[max_level] &= ~(1 << irq);
233 				--max_level;
234 			}
235 			while (level >= 0) {
236 				irqmasks[level] |= (1 << irq);
237 				--level;
238 			}
239 		}
240 
241 #include "sl.h"
242 #include "ppp.h"
243 #if NSL > 0 || NPPP > 0
244 		/* In the presence of SLIP or PPP, splimp > spltty. */
245 		irqmasks[IPL_NET] &= irqmasks[IPL_TTY];
246 #endif
247 	}
248 
249 	enable_irq(irq);
250 	set_spl_masks();
251 	restore_interrupts(oldirqstate);
252 
253 	return(0);
254 }
255 
256 
257 /*
258  * int irq_release(int irq, irqhandler_t *handler)
259  *
260  * Disable an IRQ and remove a handler for it.
261  */
262 
263 int
264 irq_release(irq, handler)
265 	int irq;
266 	irqhandler_t *handler;
267 {
268 	int level;
269 	irqhandler_t *irqhand;
270 	irqhandler_t **prehand;
271 #ifdef IRQSTATS
272 	extern char *_intrnames;
273 #endif
274 
275 	/*
276 	 * IRQ_INSTRUCT indicates that we should get the irq number
277 	 * from the irq structure
278 	 */
279 	if (irq == IRQ_INSTRUCT)
280 		irq = handler->ih_num;
281 
282 	/* Make sure the irq number is valid */
283 	if (irq < 0 || irq >= NIRQS)
284 		return(-1);
285 
286 	/* Locate the handler */
287 	irqhand = irqhandlers[irq];
288 	prehand = &irqhandlers[irq];
289 
290 	while (irqhand && handler != irqhand) {
291 		prehand = &irqhand->ih_next;
292 		irqhand = irqhand->ih_next;
293 	}
294 
295 	/* Remove the handler if located */
296 	if (irqhand)
297 		*prehand = irqhand->ih_next;
298 	else
299 		return(-1);
300 
301 	/* Now the handler has been removed from the chain mark is as inactive */
302 	irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE;
303 
304 	/* Make sure the head of the handler list is active */
305 	if (irqhandlers[irq])
306 		irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE;
307 
308 #ifdef IRQSTATS
309 	/* Get the interrupt name from the head of the list */
310 	if (irqhandlers[irq] && irqhandlers[irq]->ih_name) {
311 		char *ptr = _intrnames + (irq * 14);
312 		strcpy(ptr, "             ");
313 		strncpy(ptr, irqhandlers[irq]->ih_name,
314 		    min(strlen(irqhandlers[irq]->ih_name), 13));
315 	} else {
316 		char *ptr = _intrnames + (irq * 14);
317 		sprintf(ptr, "irq %2d     ", irq);
318 	}
319 #endif	/* IRQSTATS */
320 
321 	/*
322 	 * Update the irq masks.
323 	 * If ih_level is out of range then don't bother to update
324 	 * the masks.
325 	 */
326 	if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) {
327 		irqhandler_t *ptr;
328 
329 		/* Clean the bit from all the masks */
330 		for (level = 0; level < IPL_LEVELS; ++level)
331 			irqmasks[level] &= ~(1 << irq);
332 
333 		/*
334 		 * Find the lowest interrupt priority on the irq chain.
335 		 * Interrupt is allowable at priorities lower than this.
336 		 */
337 		ptr = irqhandlers[irq];
338 		if (ptr) {
339 			level = ptr->ih_level - 1;
340 			while (ptr) {
341 				if (ptr->ih_level - 1 < level)
342 					level = ptr->ih_level - 1;
343 				ptr = ptr->ih_next;
344 			}
345 			while (level >= 0) {
346 				irqmasks[level] |= (1 << irq);
347 				--level;
348 			}
349 		}
350 	}
351 
352 	/*
353 	 * Disable the appropriate mask bit if there are no handlers left for
354 	 * this IRQ.
355 	 */
356 	if (irqhandlers[irq] == NULL)
357 		disable_irq(irq);
358 
359 	set_spl_masks();
360 
361 	return(0);
362 }
363 
364 
365 void *
366 intr_claim(irq, level, name, ih_func, ih_arg)
367 	int irq;
368 	int level;
369 	const char *name;
370 	int (*ih_func) __P((void *));
371 	void *ih_arg;
372 {
373 	irqhandler_t *ih;
374 
375 	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
376 	if (!ih)
377 		panic("intr_claim(): Cannot malloc handler memory");
378 
379 	ih->ih_level = level;
380 	ih->ih_name = name;
381 	ih->ih_func = ih_func;
382 	ih->ih_arg = ih_arg;
383 	ih->ih_flags = 0;
384 
385 	if (irq_claim(irq, ih) != 0)
386 		return(NULL);
387 	return(ih);
388 }
389 
390 
391 int
392 intr_release(arg)
393 	void *arg;
394 {
395 	irqhandler_t *ih = (irqhandler_t *)arg;
396 
397 	if (irq_release(ih->ih_num, ih) == 0) {
398 		free(ih, M_DEVBUF);
399 		return(0);
400 	}
401 	return(1);
402 }
403 
404 #if 0
405 u_int
406 disable_interrupts(mask)
407 	u_int mask;
408 {
409 	u_int cpsr;
410 
411 	cpsr = SetCPSR(mask, mask);
412 	return(cpsr);
413 }
414 
415 
416 u_int
417 restore_interrupts(old_cpsr)
418 	u_int old_cpsr;
419 {
420 	int mask = I32_bit | F32_bit;
421 	return(SetCPSR(mask, old_cpsr & mask));
422 }
423 
424 
425 u_int
426 enable_interrupts(mask)
427 	u_int mask;
428 {
429 	return(SetCPSR(mask, 0));
430 }
431 #endif
432 
433 /*
434  * void disable_irq(int irq)
435  *
436  * Disables a specific irq. The irq is removed from the master irq mask
437  */
438 
439 void
440 disable_irq(irq)
441 	int irq;
442 {
443 	u_int oldirqstate;
444 
445 	oldirqstate = disable_interrupts(I32_bit);
446 	current_mask &= ~(1 << irq);
447 	irq_setmasks();
448 	restore_interrupts(oldirqstate);
449 }
450 
451 
452 /*
453  * void enable_irq(int irq)
454  *
455  * Enables a specific irq. The irq is added to the master irq mask
456  * This routine should be used with caution. A handler should already
457  * be installed.
458  */
459 
460 void
461 enable_irq(irq)
462 	int irq;
463 {
464 	u_int oldirqstate;
465 
466 	oldirqstate = disable_interrupts(I32_bit);
467 	current_mask |= (1 << irq);
468 	irq_setmasks();
469 	restore_interrupts(oldirqstate);
470 }
471 
472 
473 /*
474  * void stray_irqhandler(u_int mask)
475  *
476  * Handler for stray interrupts. This gets called if a handler cannot be
477  * found for an interrupt.
478  */
479 
480 void
481 stray_irqhandler(mask)
482 	u_int mask;
483 {
484 	static u_int stray_irqs = 0;
485 
486 	if (++stray_irqs <= 8)
487 		log(LOG_ERR, "Stray interrupt %08x%s\n", mask,
488 		    stray_irqs >= 8 ? ": stopped logging" : "");
489 }
490