1 /* $NetBSD: iomd_irqhandler.c,v 1.8 2004/01/03 13:11:47 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * IRQ/FIQ initialisation, claim, release and handler routines 38 * 39 * from: irqhandler.c,v 1.14 1997/04/02 21:52:19 christos Exp $ 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: iomd_irqhandler.c,v 1.8 2004/01/03 13:11:47 chris Exp $"); 44 45 #include "opt_irqstats.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <uvm/uvm_extern.h> 52 53 #include <arm/iomd/iomdreg.h> 54 #include <arm/iomd/iomdvar.h> 55 56 #include <machine/intr.h> 57 #include <machine/cpu.h> 58 #include <arm/arm32/katelib.h> 59 60 irqhandler_t *irqhandlers[NIRQS]; 61 62 int current_intr_depth; 63 u_int current_mask; 64 u_int actual_mask; 65 u_int disabled_mask; 66 u_int spl_mask; 67 u_int irqmasks[IPL_LEVELS]; 68 u_int irqblock[NIRQS]; 69 70 extern u_int soft_interrupts; /* Only so we can initialise it */ 71 72 extern char *_intrnames; 73 74 /* Prototypes */ 75 76 extern void set_spl_masks __P((void)); 77 78 /* 79 * void irq_init(void) 80 * 81 * Initialise the IRQ/FIQ sub system 82 */ 83 84 void 85 irq_init() 86 { 87 int loop; 88 89 /* Clear all the IRQ handlers and the irq block masks */ 90 for (loop = 0; loop < NIRQS; ++loop) { 91 irqhandlers[loop] = NULL; 92 irqblock[loop] = 0; 93 } 94 95 /* Clear the IRQ/FIQ masks in the IOMD */ 96 IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00); 97 IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00); 98 99 switch (IOMD_ID) { 100 case RPC600_IOMD_ID: 101 break; 102 case ARM7500_IOC_ID: 103 case ARM7500FE_IOC_ID: 104 IOMD_WRITE_BYTE(IOMD_IRQMSKC, 0x00); 105 IOMD_WRITE_BYTE(IOMD_IRQMSKD, 0x00); 106 break; 107 default: 108 printf("Unknown IOMD id (%d) found in irq_init()\n", IOMD_ID); 109 }; 110 111 IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00); 112 IOMD_WRITE_BYTE(IOMD_DMAMSK, 0x00); 113 114 /* 115 * Setup the irqmasks for the different Interrupt Priority Levels 116 * We will start with no bits set and these will be updated as handlers 117 * are installed at different IPL's. 118 */ 119 for (loop = 0; loop < IPL_LEVELS; ++loop) 120 irqmasks[loop] = 0; 121 122 current_intr_depth = 0; 123 current_mask = 0x00000000; 124 disabled_mask = 0x00000000; 125 actual_mask = 0x00000000; 126 spl_mask = 0x00000000; 127 soft_interrupts = 0x00000000; 128 129 set_spl_masks(); 130 131 /* Enable IRQ's and FIQ's */ 132 enable_interrupts(I32_bit | F32_bit); 133 } 134 135 136 /* 137 * int irq_claim(int irq, irqhandler_t *handler) 138 * 139 * Enable an IRQ and install a handler for it. 140 */ 141 142 int 143 irq_claim(irq, handler) 144 int irq; 145 irqhandler_t *handler; 146 { 147 int level; 148 int loop; 149 u_int oldirqstate; 150 151 #ifdef DIAGNOSTIC 152 /* Sanity check */ 153 if (handler == NULL) 154 panic("NULL interrupt handler"); 155 if (handler->ih_func == NULL) 156 panic("Interrupt handler does not have a function"); 157 #endif /* DIAGNOSTIC */ 158 159 /* 160 * IRQ_INSTRUCT indicates that we should get the irq number 161 * from the irq structure 162 */ 163 if (irq == IRQ_INSTRUCT) 164 irq = handler->ih_num; 165 166 /* Make sure the irq number is valid */ 167 if (irq < 0 || irq >= NIRQS) 168 return(-1); 169 170 /* Make sure the level is valid */ 171 if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS) 172 return(-1); 173 174 oldirqstate = disable_interrupts(I32_bit); 175 176 /* Attach handler at top of chain */ 177 handler->ih_next = irqhandlers[irq]; 178 irqhandlers[irq] = handler; 179 180 /* 181 * Reset the flags for this handler. 182 * As the handler is now in the chain mark it as active. 183 */ 184 handler->ih_flags = 0 | IRQ_FLAG_ACTIVE; 185 186 /* 187 * Record the interrupt number for accounting. 188 * Done here as the accounting number may not be the same as the 189 * IRQ number though for the moment they are 190 */ 191 handler->ih_num = irq; 192 193 #ifdef IRQSTATS 194 /* Get the interrupt name from the head of the list */ 195 if (handler->ih_name) { 196 char *ptr = _intrnames + (irq * 14); 197 strcpy(ptr, " "); 198 strncpy(ptr, handler->ih_name, 199 min(strlen(handler->ih_name), 13)); 200 } else { 201 char *ptr = _intrnames + (irq * 14); 202 sprintf(ptr, "irq %2d ", irq); 203 } 204 #endif /* IRQSTATS */ 205 206 /* 207 * Update the irq masks. 208 * Find the lowest interrupt priority on the irq chain. 209 * Interrupt is allowable at priorities lower than this. 210 * If ih_level is out of range then don't bother to update 211 * the masks. 212 */ 213 if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 214 irqhandler_t *ptr; 215 216 /* 217 * Find the lowest interrupt priority on the irq chain. 218 * Interrupt is allowable at priorities lower than this. 219 */ 220 ptr = irqhandlers[irq]; 221 if (ptr) { 222 int max_level; 223 224 level = ptr->ih_level - 1; 225 max_level = ptr->ih_level - 1; 226 while (ptr) { 227 if (ptr->ih_level - 1 < level) 228 level = ptr->ih_level - 1; 229 else if (ptr->ih_level - 1 > max_level) 230 max_level = ptr->ih_level - 1; 231 ptr = ptr->ih_next; 232 } 233 /* Clear out any levels that we cannot now allow */ 234 while (max_level >=0 && max_level > level) { 235 irqmasks[max_level] &= ~(1 << irq); 236 --max_level; 237 } 238 while (level >= 0) { 239 irqmasks[level] |= (1 << irq); 240 --level; 241 } 242 } 243 244 #include "sl.h" 245 #include "ppp.h" 246 #if NSL > 0 || NPPP > 0 247 /* In the presence of SLIP or PPP, splimp > spltty. */ 248 irqmasks[IPL_NET] &= irqmasks[IPL_TTY]; 249 #endif 250 } 251 252 /* 253 * We now need to update the irqblock array. This array indicates 254 * what other interrupts should be blocked when interrupt is asserted 255 * This basically emulates hardware interrupt priorities e.g. by 256 * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 257 * is asserted. For each interrupt we find the highest IPL and set 258 * the block mask to the interrupt mask for that level. 259 */ 260 for (loop = 0; loop < NIRQS; ++loop) { 261 irqhandler_t *ptr; 262 263 ptr = irqhandlers[loop]; 264 if (ptr) { 265 /* There is at least 1 handler so scan the chain */ 266 level = ptr->ih_level; 267 while (ptr) { 268 if (ptr->ih_level > level) 269 level = ptr->ih_level; 270 ptr = ptr->ih_next; 271 } 272 irqblock[loop] = ~irqmasks[level]; 273 } else 274 /* No handlers for this irq so nothing to block */ 275 irqblock[loop] = 0; 276 } 277 278 enable_irq(irq); 279 set_spl_masks(); 280 restore_interrupts(oldirqstate); 281 282 return(0); 283 } 284 285 286 /* 287 * int irq_release(int irq, irqhandler_t *handler) 288 * 289 * Disable an IRQ and remove a handler for it. 290 */ 291 292 int 293 irq_release(irq, handler) 294 int irq; 295 irqhandler_t *handler; 296 { 297 int level; 298 int loop; 299 irqhandler_t *irqhand; 300 irqhandler_t **prehand; 301 #ifdef IRQSTATS 302 extern char *_intrnames; 303 #endif 304 305 /* 306 * IRQ_INSTRUCT indicates that we should get the irq number 307 * from the irq structure 308 */ 309 if (irq == IRQ_INSTRUCT) 310 irq = handler->ih_num; 311 312 /* Make sure the irq number is valid */ 313 if (irq < 0 || irq >= NIRQS) 314 return(-1); 315 316 /* Locate the handler */ 317 irqhand = irqhandlers[irq]; 318 prehand = &irqhandlers[irq]; 319 320 while (irqhand && handler != irqhand) { 321 prehand = &irqhand->ih_next; 322 irqhand = irqhand->ih_next; 323 } 324 325 /* Remove the handler if located */ 326 if (irqhand) 327 *prehand = irqhand->ih_next; 328 else 329 return(-1); 330 331 /* Now the handler has been removed from the chain mark is as inactive */ 332 irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE; 333 334 /* Make sure the head of the handler list is active */ 335 if (irqhandlers[irq]) 336 irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE; 337 338 #ifdef IRQSTATS 339 /* Get the interrupt name from the head of the list */ 340 if (irqhandlers[irq] && irqhandlers[irq]->ih_name) { 341 char *ptr = _intrnames + (irq * 14); 342 strcpy(ptr, " "); 343 strncpy(ptr, irqhandlers[irq]->ih_name, 344 min(strlen(irqhandlers[irq]->ih_name), 13)); 345 } else { 346 char *ptr = _intrnames + (irq * 14); 347 sprintf(ptr, "irq %2d ", irq); 348 } 349 #endif /* IRQSTATS */ 350 351 /* 352 * Update the irq masks. 353 * If ih_level is out of range then don't bother to update 354 * the masks. 355 */ 356 if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 357 irqhandler_t *ptr; 358 359 /* Clean the bit from all the masks */ 360 for (level = 0; level < IPL_LEVELS; ++level) 361 irqmasks[level] &= ~(1 << irq); 362 363 /* 364 * Find the lowest interrupt priority on the irq chain. 365 * Interrupt is allowable at priorities lower than this. 366 */ 367 ptr = irqhandlers[irq]; 368 if (ptr) { 369 level = ptr->ih_level - 1; 370 while (ptr) { 371 if (ptr->ih_level - 1 < level) 372 level = ptr->ih_level - 1; 373 ptr = ptr->ih_next; 374 } 375 while (level >= 0) { 376 irqmasks[level] |= (1 << irq); 377 --level; 378 } 379 } 380 } 381 382 /* 383 * We now need to update the irqblock array. This array indicates 384 * what other interrupts should be blocked when interrupt is asserted 385 * This basically emulates hardware interrupt priorities e.g. by 386 * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 387 * is asserted. For each interrupt we find the highest IPL and set 388 * the block mask to the interrupt mask for that level. 389 */ 390 for (loop = 0; loop < NIRQS; ++loop) { 391 irqhandler_t *ptr; 392 393 ptr = irqhandlers[loop]; 394 if (ptr) { 395 /* There is at least 1 handler so scan the chain */ 396 level = ptr->ih_level; 397 while (ptr) { 398 if (ptr->ih_level > level) 399 level = ptr->ih_level; 400 ptr = ptr->ih_next; 401 } 402 irqblock[loop] = ~irqmasks[level]; 403 } else 404 /* No handlers for this irq so nothing to block */ 405 irqblock[loop] = 0; 406 } 407 408 /* 409 * Disable the appropriate mask bit if there are no handlers left for 410 * this IRQ. 411 */ 412 if (irqhandlers[irq] == NULL) 413 disable_irq(irq); 414 415 set_spl_masks(); 416 417 return(0); 418 } 419 420 421 void * 422 intr_claim(irq, level, name, ih_func, ih_arg) 423 int irq; 424 int level; 425 const char *name; 426 int (*ih_func) __P((void *)); 427 void *ih_arg; 428 { 429 irqhandler_t *ih; 430 431 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 432 if (!ih) 433 panic("intr_claim(): Cannot malloc handler memory"); 434 435 ih->ih_level = level; 436 ih->ih_name = name; 437 ih->ih_func = ih_func; 438 ih->ih_arg = ih_arg; 439 ih->ih_flags = 0; 440 441 if (irq_claim(irq, ih) != 0) 442 return(NULL); 443 return(ih); 444 } 445 446 447 int 448 intr_release(arg) 449 void *arg; 450 { 451 irqhandler_t *ih = (irqhandler_t *)arg; 452 453 if (irq_release(ih->ih_num, ih) == 0) { 454 free(ih, M_DEVBUF); 455 return(0); 456 } 457 return(1); 458 } 459 460 #if 0 461 u_int 462 disable_interrupts(mask) 463 u_int mask; 464 { 465 u_int cpsr; 466 467 cpsr = SetCPSR(mask, mask); 468 return(cpsr); 469 } 470 471 472 u_int 473 restore_interrupts(old_cpsr) 474 u_int old_cpsr; 475 { 476 int mask = I32_bit | F32_bit; 477 return(SetCPSR(mask, old_cpsr & mask)); 478 } 479 480 481 u_int 482 enable_interrupts(mask) 483 u_int mask; 484 { 485 return(SetCPSR(mask, 0)); 486 } 487 #endif 488 489 /* 490 * void disable_irq(int irq) 491 * 492 * Disables a specific irq. The irq is removed from the master irq mask 493 */ 494 495 void 496 disable_irq(irq) 497 int irq; 498 { 499 u_int oldirqstate; 500 501 oldirqstate = disable_interrupts(I32_bit); 502 current_mask &= ~(1 << irq); 503 irq_setmasks(); 504 restore_interrupts(oldirqstate); 505 } 506 507 508 /* 509 * void enable_irq(int irq) 510 * 511 * Enables a specific irq. The irq is added to the master irq mask 512 * This routine should be used with caution. A handler should already 513 * be installed. 514 */ 515 516 void 517 enable_irq(irq) 518 int irq; 519 { 520 u_int oldirqstate; 521 522 oldirqstate = disable_interrupts(I32_bit); 523 current_mask |= (1 << irq); 524 irq_setmasks(); 525 restore_interrupts(oldirqstate); 526 } 527 528 529 /* 530 * void stray_irqhandler(u_int mask) 531 * 532 * Handler for stray interrupts. This gets called if a handler cannot be 533 * found for an interrupt. 534 */ 535 536 void 537 stray_irqhandler(mask) 538 u_int mask; 539 { 540 static u_int stray_irqs = 0; 541 542 if (++stray_irqs <= 8) 543 log(LOG_ERR, "Stray interrupt %08x%s\n", mask, 544 stray_irqs >= 8 ? ": stopped logging" : ""); 545 } 546