1 /* $NetBSD: iomd_irqhandler.c,v 1.3 2001/11/27 01:03:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * IRQ/FIQ initialisation, claim, release and handler routines 38 * 39 * from: irqhandler.c,v 1.14 1997/04/02 21:52:19 christos Exp $ 40 */ 41 42 #include "opt_irqstats.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <arm/iomd/iomdreg.h> 51 #include <arm/iomd/iomdvar.h> 52 53 #include <machine/intr.h> 54 #include <machine/cpu.h> 55 #include <arm/arm32/katelib.h> 56 57 irqhandler_t *irqhandlers[NIRQS]; 58 fiqhandler_t *fiqhandlers; 59 60 int current_intr_depth; 61 u_int current_mask; 62 u_int actual_mask; 63 u_int disabled_mask; 64 u_int spl_mask; 65 u_int irqmasks[IPL_LEVELS]; 66 u_int irqblock[NIRQS]; 67 68 extern u_int soft_interrupts; /* Only so we can initialise it */ 69 70 extern char *_intrnames; 71 72 /* Prototypes */ 73 74 extern void zero_page_readonly __P((void)); 75 extern void zero_page_readwrite __P((void)); 76 extern int fiq_setregs __P((fiqhandler_t *)); 77 extern int fiq_getregs __P((fiqhandler_t *)); 78 extern void set_spl_masks __P((void)); 79 80 /* 81 * void irq_init(void) 82 * 83 * Initialise the IRQ/FIQ sub system 84 */ 85 86 void 87 irq_init() 88 { 89 int loop; 90 91 /* Clear all the IRQ handlers and the irq block masks */ 92 for (loop = 0; loop < NIRQS; ++loop) { 93 irqhandlers[loop] = NULL; 94 irqblock[loop] = 0; 95 } 96 97 /* Clear the FIQ handler */ 98 fiqhandlers = NULL; 99 100 /* Clear the IRQ/FIQ masks in the IOMD */ 101 IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00); 102 IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00); 103 104 switch (IOMD_ID) { 105 case RPC600_IOMD_ID: 106 break; 107 case ARM7500_IOC_ID: 108 case ARM7500FE_IOC_ID: 109 IOMD_WRITE_BYTE(IOMD_IRQMSKC, 0x00); 110 IOMD_WRITE_BYTE(IOMD_IRQMSKD, 0x00); 111 break; 112 default: 113 printf("Unknown IOMD id (%d) found in irq_init()\n", IOMD_ID); 114 }; 115 116 IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00); 117 IOMD_WRITE_BYTE(IOMD_DMAMSK, 0x00); 118 119 /* 120 * Setup the irqmasks for the different Interrupt Priority Levels 121 * We will start with no bits set and these will be updated as handlers 122 * are installed at different IPL's. 123 */ 124 for (loop = 0; loop < IPL_LEVELS; ++loop) 125 irqmasks[loop] = 0; 126 127 current_intr_depth = 0; 128 current_mask = 0x00000000; 129 disabled_mask = 0x00000000; 130 actual_mask = 0x00000000; 131 spl_mask = 0x00000000; 132 soft_interrupts = 0x00000000; 133 134 set_spl_masks(); 135 136 /* Enable IRQ's and FIQ's */ 137 enable_interrupts(I32_bit | F32_bit); 138 } 139 140 141 /* 142 * int irq_claim(int irq, irqhandler_t *handler) 143 * 144 * Enable an IRQ and install a handler for it. 145 */ 146 147 int 148 irq_claim(irq, handler) 149 int irq; 150 irqhandler_t *handler; 151 { 152 int level; 153 int loop; 154 155 #ifdef DIAGNOSTIC 156 /* Sanity check */ 157 if (handler == NULL) 158 panic("NULL interrupt handler\n"); 159 if (handler->ih_func == NULL) 160 panic("Interrupt handler does not have a function\n"); 161 #endif /* DIAGNOSTIC */ 162 163 /* 164 * IRQ_INSTRUCT indicates that we should get the irq number 165 * from the irq structure 166 */ 167 if (irq == IRQ_INSTRUCT) 168 irq = handler->ih_num; 169 170 /* Make sure the irq number is valid */ 171 if (irq < 0 || irq >= NIRQS) 172 return(-1); 173 174 /* Make sure the level is valid */ 175 if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS) 176 return(-1); 177 178 /* Attach handler at top of chain */ 179 handler->ih_next = irqhandlers[irq]; 180 irqhandlers[irq] = handler; 181 182 /* 183 * Reset the flags for this handler. 184 * As the handler is now in the chain mark it as active. 185 */ 186 handler->ih_flags = 0 | IRQ_FLAG_ACTIVE; 187 188 /* 189 * Record the interrupt number for accounting. 190 * Done here as the accounting number may not be the same as the 191 * IRQ number though for the moment they are 192 */ 193 handler->ih_num = irq; 194 195 #ifdef IRQSTATS 196 /* Get the interrupt name from the head of the list */ 197 if (handler->ih_name) { 198 char *ptr = _intrnames + (irq * 14); 199 strcpy(ptr, " "); 200 strncpy(ptr, handler->ih_name, 201 min(strlen(handler->ih_name), 13)); 202 } else { 203 char *ptr = _intrnames + (irq * 14); 204 sprintf(ptr, "irq %2d ", irq); 205 } 206 #endif /* IRQSTATS */ 207 208 /* 209 * Update the irq masks. 210 * Find the lowest interrupt priority on the irq chain. 211 * Interrupt is allowable at priorities lower than this. 212 * If ih_level is out of range then don't bother to update 213 * the masks. 214 */ 215 if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 216 irqhandler_t *ptr; 217 218 /* 219 * Find the lowest interrupt priority on the irq chain. 220 * Interrupt is allowable at priorities lower than this. 221 */ 222 ptr = irqhandlers[irq]; 223 if (ptr) { 224 int max_level; 225 226 level = ptr->ih_level - 1; 227 max_level = ptr->ih_level - 1; 228 while (ptr) { 229 if (ptr->ih_level - 1 < level) 230 level = ptr->ih_level - 1; 231 else if (ptr->ih_level - 1 > max_level) 232 max_level = ptr->ih_level - 1; 233 ptr = ptr->ih_next; 234 } 235 /* Clear out any levels that we cannot now allow */ 236 while (max_level >=0 && max_level > level) { 237 irqmasks[max_level] &= ~(1 << irq); 238 --max_level; 239 } 240 while (level >= 0) { 241 irqmasks[level] |= (1 << irq); 242 --level; 243 } 244 } 245 246 #include "sl.h" 247 #include "ppp.h" 248 #if NSL > 0 || NPPP > 0 249 /* In the presence of SLIP or PPP, splimp > spltty. */ 250 irqmasks[IPL_NET] &= irqmasks[IPL_TTY]; 251 #endif 252 } 253 254 /* 255 * We now need to update the irqblock array. This array indicates 256 * what other interrupts should be blocked when interrupt is asserted 257 * This basically emulates hardware interrupt priorities e.g. by 258 * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 259 * is asserted. For each interrupt we find the highest IPL and set 260 * the block mask to the interrupt mask for that level. 261 */ 262 for (loop = 0; loop < NIRQS; ++loop) { 263 irqhandler_t *ptr; 264 265 ptr = irqhandlers[loop]; 266 if (ptr) { 267 /* There is at least 1 handler so scan the chain */ 268 level = ptr->ih_level; 269 while (ptr) { 270 if (ptr->ih_level > level) 271 level = ptr->ih_level; 272 ptr = ptr->ih_next; 273 } 274 irqblock[loop] = ~irqmasks[level]; 275 } else 276 /* No handlers for this irq so nothing to block */ 277 irqblock[loop] = 0; 278 } 279 280 enable_irq(irq); 281 set_spl_masks(); 282 283 return(0); 284 } 285 286 287 /* 288 * int irq_release(int irq, irqhandler_t *handler) 289 * 290 * Disable an IRQ and remove a handler for it. 291 */ 292 293 int 294 irq_release(irq, handler) 295 int irq; 296 irqhandler_t *handler; 297 { 298 int level; 299 int loop; 300 irqhandler_t *irqhand; 301 irqhandler_t **prehand; 302 #ifdef IRQSTATS 303 extern char *_intrnames; 304 #endif 305 306 /* 307 * IRQ_INSTRUCT indicates that we should get the irq number 308 * from the irq structure 309 */ 310 if (irq == IRQ_INSTRUCT) 311 irq = handler->ih_num; 312 313 /* Make sure the irq number is valid */ 314 if (irq < 0 || irq >= NIRQS) 315 return(-1); 316 317 /* Locate the handler */ 318 irqhand = irqhandlers[irq]; 319 prehand = &irqhandlers[irq]; 320 321 while (irqhand && handler != irqhand) { 322 prehand = &irqhand->ih_next; 323 irqhand = irqhand->ih_next; 324 } 325 326 /* Remove the handler if located */ 327 if (irqhand) 328 *prehand = irqhand->ih_next; 329 else 330 return(-1); 331 332 /* Now the handler has been removed from the chain mark is as inactive */ 333 irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE; 334 335 /* Make sure the head of the handler list is active */ 336 if (irqhandlers[irq]) 337 irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE; 338 339 #ifdef IRQSTATS 340 /* Get the interrupt name from the head of the list */ 341 if (irqhandlers[irq] && irqhandlers[irq]->ih_name) { 342 char *ptr = _intrnames + (irq * 14); 343 strcpy(ptr, " "); 344 strncpy(ptr, irqhandlers[irq]->ih_name, 345 min(strlen(irqhandlers[irq]->ih_name), 13)); 346 } else { 347 char *ptr = _intrnames + (irq * 14); 348 sprintf(ptr, "irq %2d ", irq); 349 } 350 #endif /* IRQSTATS */ 351 352 /* 353 * Update the irq masks. 354 * If ih_level is out of range then don't bother to update 355 * the masks. 356 */ 357 if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 358 irqhandler_t *ptr; 359 360 /* Clean the bit from all the masks */ 361 for (level = 0; level < IPL_LEVELS; ++level) 362 irqmasks[level] &= ~(1 << irq); 363 364 /* 365 * Find the lowest interrupt priority on the irq chain. 366 * Interrupt is allowable at priorities lower than this. 367 */ 368 ptr = irqhandlers[irq]; 369 if (ptr) { 370 level = ptr->ih_level - 1; 371 while (ptr) { 372 if (ptr->ih_level - 1 < level) 373 level = ptr->ih_level - 1; 374 ptr = ptr->ih_next; 375 } 376 while (level >= 0) { 377 irqmasks[level] |= (1 << irq); 378 --level; 379 } 380 } 381 } 382 383 /* 384 * We now need to update the irqblock array. This array indicates 385 * what other interrupts should be blocked when interrupt is asserted 386 * This basically emulates hardware interrupt priorities e.g. by 387 * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 388 * is asserted. For each interrupt we find the highest IPL and set 389 * the block mask to the interrupt mask for that level. 390 */ 391 for (loop = 0; loop < NIRQS; ++loop) { 392 irqhandler_t *ptr; 393 394 ptr = irqhandlers[loop]; 395 if (ptr) { 396 /* There is at least 1 handler so scan the chain */ 397 level = ptr->ih_level; 398 while (ptr) { 399 if (ptr->ih_level > level) 400 level = ptr->ih_level; 401 ptr = ptr->ih_next; 402 } 403 irqblock[loop] = ~irqmasks[level]; 404 } else 405 /* No handlers for this irq so nothing to block */ 406 irqblock[loop] = 0; 407 } 408 409 /* 410 * Disable the appropriate mask bit if there are no handlers left for 411 * this IRQ. 412 */ 413 if (irqhandlers[irq] == NULL) 414 disable_irq(irq); 415 416 set_spl_masks(); 417 418 return(0); 419 } 420 421 422 void * 423 intr_claim(irq, level, name, ih_func, ih_arg) 424 int irq; 425 int level; 426 const char *name; 427 int (*ih_func) __P((void *)); 428 void *ih_arg; 429 { 430 irqhandler_t *ih; 431 432 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 433 if (!ih) 434 panic("intr_claim(): Cannot malloc handler memory\n"); 435 436 ih->ih_level = level; 437 ih->ih_name = name; 438 ih->ih_func = ih_func; 439 ih->ih_arg = ih_arg; 440 ih->ih_flags = 0; 441 442 if (irq_claim(irq, ih) != 0) 443 return(NULL); 444 return(ih); 445 } 446 447 448 int 449 intr_release(arg) 450 void *arg; 451 { 452 irqhandler_t *ih = (irqhandler_t *)arg; 453 454 if (irq_release(ih->ih_num, ih) == 0) { 455 free(ih, M_DEVBUF); 456 return(0); 457 } 458 return(1); 459 } 460 461 #if 0 462 u_int 463 disable_interrupts(mask) 464 u_int mask; 465 { 466 u_int cpsr; 467 468 cpsr = SetCPSR(mask, mask); 469 return(cpsr); 470 } 471 472 473 u_int 474 restore_interrupts(old_cpsr) 475 u_int old_cpsr; 476 { 477 int mask = I32_bit | F32_bit; 478 return(SetCPSR(mask, old_cpsr & mask)); 479 } 480 481 482 u_int 483 enable_interrupts(mask) 484 u_int mask; 485 { 486 return(SetCPSR(mask, 0)); 487 } 488 #endif 489 490 /* 491 * void disable_irq(int irq) 492 * 493 * Disables a specific irq. The irq is removed from the master irq mask 494 */ 495 496 void 497 disable_irq(irq) 498 int irq; 499 { 500 u_int oldirqstate; 501 502 oldirqstate = disable_interrupts(I32_bit); 503 current_mask &= ~(1 << irq); 504 irq_setmasks(); 505 restore_interrupts(oldirqstate); 506 } 507 508 509 /* 510 * void enable_irq(int irq) 511 * 512 * Enables a specific irq. The irq is added to the master irq mask 513 * This routine should be used with caution. A handler should already 514 * be installed. 515 */ 516 517 void 518 enable_irq(irq) 519 int irq; 520 { 521 u_int oldirqstate; 522 523 oldirqstate = disable_interrupts(I32_bit); 524 current_mask |= (1 << irq); 525 irq_setmasks(); 526 restore_interrupts(oldirqstate); 527 } 528 529 530 /* 531 * void stray_irqhandler(u_int mask) 532 * 533 * Handler for stray interrupts. This gets called if a handler cannot be 534 * found for an interrupt. 535 */ 536 537 void 538 stray_irqhandler(mask) 539 u_int mask; 540 { 541 static u_int stray_irqs = 0; 542 543 if (++stray_irqs <= 8) 544 log(LOG_ERR, "Stray interrupt %08x%s\n", mask, 545 stray_irqs >= 8 ? ": stopped logging" : ""); 546 } 547 548 549 /* 550 * int fiq_claim(fiqhandler_t *handler) 551 * 552 * Claim FIQ's and install a handler for them. 553 */ 554 555 int 556 fiq_claim(handler) 557 fiqhandler_t *handler; 558 { 559 /* Fail if the FIQ's are already claimed */ 560 if (fiqhandlers) 561 return(-1); 562 563 if (handler->fh_size > 0xc0) 564 return(-1); 565 566 /* Install the handler */ 567 fiqhandlers = handler; 568 569 /* Now we have to actually install the FIQ handler */ 570 571 /* Eventually we will copy this down but for the moment ... */ 572 zero_page_readwrite(); 573 574 WriteWord(0x0000003c, (u_int) handler->fh_func); 575 576 zero_page_readonly(); 577 578 /* We must now set up the FIQ registers */ 579 fiq_setregs(handler); 580 581 /* Set up the FIQ mask */ 582 IOMD_WRITE_BYTE(IOMD_FIQMSK, handler->fh_mask); 583 584 /* Make sure that the FIQ's are enabled */ 585 enable_interrupts(F32_bit); 586 return(0); 587 } 588 589 590 /* 591 * int fiq_release(fiqhandler_t *handler) 592 * 593 * Release FIQ's and remove a handler for them. 594 */ 595 596 int 597 fiq_release(handler) 598 fiqhandler_t *handler; 599 { 600 /* Fail if the handler is wrong */ 601 if (fiqhandlers != handler) 602 return(-1); 603 604 /* Disable FIQ interrupts */ 605 disable_interrupts(F32_bit); 606 607 /* Clear up the FIQ mask */ 608 IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00); 609 610 /* Retrieve the FIQ registers */ 611 fiq_getregs(handler); 612 613 /* Remove the handler */ 614 fiqhandlers = NULL; 615 return(0); 616 } 617 618 /* End of irqhandler.c */ 619