1 /* $NetBSD: iomd_irqhandler.c,v 1.4 2001/12/20 01:20:24 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * IRQ/FIQ initialisation, claim, release and handler routines 38 * 39 * from: irqhandler.c,v 1.14 1997/04/02 21:52:19 christos Exp $ 40 */ 41 42 #include "opt_irqstats.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <arm/iomd/iomdreg.h> 51 #include <arm/iomd/iomdvar.h> 52 53 #include <machine/intr.h> 54 #include <machine/cpu.h> 55 #include <arm/arm32/katelib.h> 56 57 irqhandler_t *irqhandlers[NIRQS]; 58 59 int current_intr_depth; 60 u_int current_mask; 61 u_int actual_mask; 62 u_int disabled_mask; 63 u_int spl_mask; 64 u_int irqmasks[IPL_LEVELS]; 65 u_int irqblock[NIRQS]; 66 67 extern u_int soft_interrupts; /* Only so we can initialise it */ 68 69 extern char *_intrnames; 70 71 /* Prototypes */ 72 73 extern void zero_page_readonly __P((void)); 74 extern void zero_page_readwrite __P((void)); 75 extern void set_spl_masks __P((void)); 76 77 /* 78 * void irq_init(void) 79 * 80 * Initialise the IRQ/FIQ sub system 81 */ 82 83 void 84 irq_init() 85 { 86 int loop; 87 88 /* Clear all the IRQ handlers and the irq block masks */ 89 for (loop = 0; loop < NIRQS; ++loop) { 90 irqhandlers[loop] = NULL; 91 irqblock[loop] = 0; 92 } 93 94 /* Clear the IRQ/FIQ masks in the IOMD */ 95 IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00); 96 IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00); 97 98 switch (IOMD_ID) { 99 case RPC600_IOMD_ID: 100 break; 101 case ARM7500_IOC_ID: 102 case ARM7500FE_IOC_ID: 103 IOMD_WRITE_BYTE(IOMD_IRQMSKC, 0x00); 104 IOMD_WRITE_BYTE(IOMD_IRQMSKD, 0x00); 105 break; 106 default: 107 printf("Unknown IOMD id (%d) found in irq_init()\n", IOMD_ID); 108 }; 109 110 IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00); 111 IOMD_WRITE_BYTE(IOMD_DMAMSK, 0x00); 112 113 /* 114 * Setup the irqmasks for the different Interrupt Priority Levels 115 * We will start with no bits set and these will be updated as handlers 116 * are installed at different IPL's. 117 */ 118 for (loop = 0; loop < IPL_LEVELS; ++loop) 119 irqmasks[loop] = 0; 120 121 current_intr_depth = 0; 122 current_mask = 0x00000000; 123 disabled_mask = 0x00000000; 124 actual_mask = 0x00000000; 125 spl_mask = 0x00000000; 126 soft_interrupts = 0x00000000; 127 128 set_spl_masks(); 129 130 /* Enable IRQ's and FIQ's */ 131 enable_interrupts(I32_bit | F32_bit); 132 } 133 134 135 /* 136 * int irq_claim(int irq, irqhandler_t *handler) 137 * 138 * Enable an IRQ and install a handler for it. 139 */ 140 141 int 142 irq_claim(irq, handler) 143 int irq; 144 irqhandler_t *handler; 145 { 146 int level; 147 int loop; 148 149 #ifdef DIAGNOSTIC 150 /* Sanity check */ 151 if (handler == NULL) 152 panic("NULL interrupt handler\n"); 153 if (handler->ih_func == NULL) 154 panic("Interrupt handler does not have a function\n"); 155 #endif /* DIAGNOSTIC */ 156 157 /* 158 * IRQ_INSTRUCT indicates that we should get the irq number 159 * from the irq structure 160 */ 161 if (irq == IRQ_INSTRUCT) 162 irq = handler->ih_num; 163 164 /* Make sure the irq number is valid */ 165 if (irq < 0 || irq >= NIRQS) 166 return(-1); 167 168 /* Make sure the level is valid */ 169 if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS) 170 return(-1); 171 172 /* Attach handler at top of chain */ 173 handler->ih_next = irqhandlers[irq]; 174 irqhandlers[irq] = handler; 175 176 /* 177 * Reset the flags for this handler. 178 * As the handler is now in the chain mark it as active. 179 */ 180 handler->ih_flags = 0 | IRQ_FLAG_ACTIVE; 181 182 /* 183 * Record the interrupt number for accounting. 184 * Done here as the accounting number may not be the same as the 185 * IRQ number though for the moment they are 186 */ 187 handler->ih_num = irq; 188 189 #ifdef IRQSTATS 190 /* Get the interrupt name from the head of the list */ 191 if (handler->ih_name) { 192 char *ptr = _intrnames + (irq * 14); 193 strcpy(ptr, " "); 194 strncpy(ptr, handler->ih_name, 195 min(strlen(handler->ih_name), 13)); 196 } else { 197 char *ptr = _intrnames + (irq * 14); 198 sprintf(ptr, "irq %2d ", irq); 199 } 200 #endif /* IRQSTATS */ 201 202 /* 203 * Update the irq masks. 204 * Find the lowest interrupt priority on the irq chain. 205 * Interrupt is allowable at priorities lower than this. 206 * If ih_level is out of range then don't bother to update 207 * the masks. 208 */ 209 if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 210 irqhandler_t *ptr; 211 212 /* 213 * Find the lowest interrupt priority on the irq chain. 214 * Interrupt is allowable at priorities lower than this. 215 */ 216 ptr = irqhandlers[irq]; 217 if (ptr) { 218 int max_level; 219 220 level = ptr->ih_level - 1; 221 max_level = ptr->ih_level - 1; 222 while (ptr) { 223 if (ptr->ih_level - 1 < level) 224 level = ptr->ih_level - 1; 225 else if (ptr->ih_level - 1 > max_level) 226 max_level = ptr->ih_level - 1; 227 ptr = ptr->ih_next; 228 } 229 /* Clear out any levels that we cannot now allow */ 230 while (max_level >=0 && max_level > level) { 231 irqmasks[max_level] &= ~(1 << irq); 232 --max_level; 233 } 234 while (level >= 0) { 235 irqmasks[level] |= (1 << irq); 236 --level; 237 } 238 } 239 240 #include "sl.h" 241 #include "ppp.h" 242 #if NSL > 0 || NPPP > 0 243 /* In the presence of SLIP or PPP, splimp > spltty. */ 244 irqmasks[IPL_NET] &= irqmasks[IPL_TTY]; 245 #endif 246 } 247 248 /* 249 * We now need to update the irqblock array. This array indicates 250 * what other interrupts should be blocked when interrupt is asserted 251 * This basically emulates hardware interrupt priorities e.g. by 252 * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 253 * is asserted. For each interrupt we find the highest IPL and set 254 * the block mask to the interrupt mask for that level. 255 */ 256 for (loop = 0; loop < NIRQS; ++loop) { 257 irqhandler_t *ptr; 258 259 ptr = irqhandlers[loop]; 260 if (ptr) { 261 /* There is at least 1 handler so scan the chain */ 262 level = ptr->ih_level; 263 while (ptr) { 264 if (ptr->ih_level > level) 265 level = ptr->ih_level; 266 ptr = ptr->ih_next; 267 } 268 irqblock[loop] = ~irqmasks[level]; 269 } else 270 /* No handlers for this irq so nothing to block */ 271 irqblock[loop] = 0; 272 } 273 274 enable_irq(irq); 275 set_spl_masks(); 276 277 return(0); 278 } 279 280 281 /* 282 * int irq_release(int irq, irqhandler_t *handler) 283 * 284 * Disable an IRQ and remove a handler for it. 285 */ 286 287 int 288 irq_release(irq, handler) 289 int irq; 290 irqhandler_t *handler; 291 { 292 int level; 293 int loop; 294 irqhandler_t *irqhand; 295 irqhandler_t **prehand; 296 #ifdef IRQSTATS 297 extern char *_intrnames; 298 #endif 299 300 /* 301 * IRQ_INSTRUCT indicates that we should get the irq number 302 * from the irq structure 303 */ 304 if (irq == IRQ_INSTRUCT) 305 irq = handler->ih_num; 306 307 /* Make sure the irq number is valid */ 308 if (irq < 0 || irq >= NIRQS) 309 return(-1); 310 311 /* Locate the handler */ 312 irqhand = irqhandlers[irq]; 313 prehand = &irqhandlers[irq]; 314 315 while (irqhand && handler != irqhand) { 316 prehand = &irqhand->ih_next; 317 irqhand = irqhand->ih_next; 318 } 319 320 /* Remove the handler if located */ 321 if (irqhand) 322 *prehand = irqhand->ih_next; 323 else 324 return(-1); 325 326 /* Now the handler has been removed from the chain mark is as inactive */ 327 irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE; 328 329 /* Make sure the head of the handler list is active */ 330 if (irqhandlers[irq]) 331 irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE; 332 333 #ifdef IRQSTATS 334 /* Get the interrupt name from the head of the list */ 335 if (irqhandlers[irq] && irqhandlers[irq]->ih_name) { 336 char *ptr = _intrnames + (irq * 14); 337 strcpy(ptr, " "); 338 strncpy(ptr, irqhandlers[irq]->ih_name, 339 min(strlen(irqhandlers[irq]->ih_name), 13)); 340 } else { 341 char *ptr = _intrnames + (irq * 14); 342 sprintf(ptr, "irq %2d ", irq); 343 } 344 #endif /* IRQSTATS */ 345 346 /* 347 * Update the irq masks. 348 * If ih_level is out of range then don't bother to update 349 * the masks. 350 */ 351 if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 352 irqhandler_t *ptr; 353 354 /* Clean the bit from all the masks */ 355 for (level = 0; level < IPL_LEVELS; ++level) 356 irqmasks[level] &= ~(1 << irq); 357 358 /* 359 * Find the lowest interrupt priority on the irq chain. 360 * Interrupt is allowable at priorities lower than this. 361 */ 362 ptr = irqhandlers[irq]; 363 if (ptr) { 364 level = ptr->ih_level - 1; 365 while (ptr) { 366 if (ptr->ih_level - 1 < level) 367 level = ptr->ih_level - 1; 368 ptr = ptr->ih_next; 369 } 370 while (level >= 0) { 371 irqmasks[level] |= (1 << irq); 372 --level; 373 } 374 } 375 } 376 377 /* 378 * We now need to update the irqblock array. This array indicates 379 * what other interrupts should be blocked when interrupt is asserted 380 * This basically emulates hardware interrupt priorities e.g. by 381 * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 382 * is asserted. For each interrupt we find the highest IPL and set 383 * the block mask to the interrupt mask for that level. 384 */ 385 for (loop = 0; loop < NIRQS; ++loop) { 386 irqhandler_t *ptr; 387 388 ptr = irqhandlers[loop]; 389 if (ptr) { 390 /* There is at least 1 handler so scan the chain */ 391 level = ptr->ih_level; 392 while (ptr) { 393 if (ptr->ih_level > level) 394 level = ptr->ih_level; 395 ptr = ptr->ih_next; 396 } 397 irqblock[loop] = ~irqmasks[level]; 398 } else 399 /* No handlers for this irq so nothing to block */ 400 irqblock[loop] = 0; 401 } 402 403 /* 404 * Disable the appropriate mask bit if there are no handlers left for 405 * this IRQ. 406 */ 407 if (irqhandlers[irq] == NULL) 408 disable_irq(irq); 409 410 set_spl_masks(); 411 412 return(0); 413 } 414 415 416 void * 417 intr_claim(irq, level, name, ih_func, ih_arg) 418 int irq; 419 int level; 420 const char *name; 421 int (*ih_func) __P((void *)); 422 void *ih_arg; 423 { 424 irqhandler_t *ih; 425 426 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 427 if (!ih) 428 panic("intr_claim(): Cannot malloc handler memory\n"); 429 430 ih->ih_level = level; 431 ih->ih_name = name; 432 ih->ih_func = ih_func; 433 ih->ih_arg = ih_arg; 434 ih->ih_flags = 0; 435 436 if (irq_claim(irq, ih) != 0) 437 return(NULL); 438 return(ih); 439 } 440 441 442 int 443 intr_release(arg) 444 void *arg; 445 { 446 irqhandler_t *ih = (irqhandler_t *)arg; 447 448 if (irq_release(ih->ih_num, ih) == 0) { 449 free(ih, M_DEVBUF); 450 return(0); 451 } 452 return(1); 453 } 454 455 #if 0 456 u_int 457 disable_interrupts(mask) 458 u_int mask; 459 { 460 u_int cpsr; 461 462 cpsr = SetCPSR(mask, mask); 463 return(cpsr); 464 } 465 466 467 u_int 468 restore_interrupts(old_cpsr) 469 u_int old_cpsr; 470 { 471 int mask = I32_bit | F32_bit; 472 return(SetCPSR(mask, old_cpsr & mask)); 473 } 474 475 476 u_int 477 enable_interrupts(mask) 478 u_int mask; 479 { 480 return(SetCPSR(mask, 0)); 481 } 482 #endif 483 484 /* 485 * void disable_irq(int irq) 486 * 487 * Disables a specific irq. The irq is removed from the master irq mask 488 */ 489 490 void 491 disable_irq(irq) 492 int irq; 493 { 494 u_int oldirqstate; 495 496 oldirqstate = disable_interrupts(I32_bit); 497 current_mask &= ~(1 << irq); 498 irq_setmasks(); 499 restore_interrupts(oldirqstate); 500 } 501 502 503 /* 504 * void enable_irq(int irq) 505 * 506 * Enables a specific irq. The irq is added to the master irq mask 507 * This routine should be used with caution. A handler should already 508 * be installed. 509 */ 510 511 void 512 enable_irq(irq) 513 int irq; 514 { 515 u_int oldirqstate; 516 517 oldirqstate = disable_interrupts(I32_bit); 518 current_mask |= (1 << irq); 519 irq_setmasks(); 520 restore_interrupts(oldirqstate); 521 } 522 523 524 /* 525 * void stray_irqhandler(u_int mask) 526 * 527 * Handler for stray interrupts. This gets called if a handler cannot be 528 * found for an interrupt. 529 */ 530 531 void 532 stray_irqhandler(mask) 533 u_int mask; 534 { 535 static u_int stray_irqs = 0; 536 537 if (++stray_irqs <= 8) 538 log(LOG_ERR, "Stray interrupt %08x%s\n", mask, 539 stray_irqs >= 8 ? ": stopped logging" : ""); 540 } 541