1 /* $NetBSD: lock.h,v 1.24 2013/01/28 06:17:05 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Machine-dependent spin lock operations. 34 * 35 * NOTE: The SWP insn used here is available only on ARM architecture 36 * version 3 and later (as well as 2a). What we are going to do is 37 * expect that the kernel will trap and emulate the insn. That will 38 * be slow, but give us the atomicity that we need. 39 */ 40 41 #ifndef _ARM_LOCK_H_ 42 #define _ARM_LOCK_H_ 43 44 static __inline int 45 __SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr) 46 { 47 return *__ptr == __SIMPLELOCK_LOCKED; 48 } 49 50 static __inline int 51 __SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr) 52 { 53 return *__ptr == __SIMPLELOCK_UNLOCKED; 54 } 55 56 static __inline void 57 __cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr) 58 { 59 *__ptr = __SIMPLELOCK_UNLOCKED; 60 } 61 62 static __inline void 63 __cpu_simple_lock_set(__cpu_simple_lock_t *__ptr) 64 { 65 *__ptr = __SIMPLELOCK_LOCKED; 66 } 67 68 #ifdef _KERNEL 69 #include <arm/cpufunc.h> 70 71 #define mb_read drain_writebuf /* in cpufunc.h */ 72 #define mb_write drain_writebuf /* in cpufunc.h */ 73 #define mb_memory drain_writebuf /* in cpufunc.h */ 74 #endif 75 76 #if defined(_KERNEL) 77 static __inline unsigned char 78 __swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr) 79 { 80 #ifdef _ARM_ARCH_6 81 uint32_t __rv, __tmp; 82 if (sizeof(*__ptr) == 1) { 83 __asm volatile( 84 "1:\t" 85 "ldrexb\t%[__rv], [%[__ptr]]" "\n\t" 86 "cmp\t%[__rv],%[__val]" "\n\t" 87 "strexbne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t" 88 "cmpne\t%[__tmp], #0" "\n\t" 89 "bne\t1b" "\n\t" 90 #ifdef _ARM_ARCH_7 91 "dmb" 92 #else 93 "mcr\tp15, 0, %[__tmp], c7, c10, 5" 94 #endif 95 : [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp) 96 : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory"); 97 } else { 98 __asm volatile( 99 "1:\t" 100 "ldrex\t%[__rv], [%[__ptr]]" "\n\t" 101 "cmp\t%[__rv],%[__val]" "\n\t" 102 "strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t" 103 "cmpne\t%[__tmp], #0" "\n\t" 104 "bne\t1b" "\n\t" 105 #ifdef _ARM_ARCH_7 106 "nop" 107 #else 108 "mcr\tp15, 0, %[__tmp], c7, c10, 5" 109 #endif 110 : [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp) 111 : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory"); 112 } 113 return __rv; 114 #else 115 uint32_t __val32; 116 __asm volatile("swpb %0, %1, [%2]" 117 : "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory"); 118 return __val32; 119 #endif 120 } 121 #else 122 /* 123 * On Cortex-A9 (SMP), SWP no longer guarantees atomic results. Thus we pad 124 * out SWP so that when the A9 generates an undefined exception we can replace 125 * the SWP/MOV instructions with the right LDREX/STREX instructions. 126 * 127 * This is why we force the SWP into the template needed for LDREX/STREX 128 * including the extra instructions and extra register for testing the result. 129 */ 130 static __inline int 131 __swp(int __val, volatile int *__ptr) 132 { 133 int __rv, __tmp; 134 __asm volatile( 135 "1:\t" 136 #ifdef _ARM_ARCH_6 137 "ldrex\t%[__rv], [%[__ptr]]" "\n\t" 138 "cmp\t%[__rv],%[__val]" "\n\t" 139 "strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t" 140 #else 141 "swp\t%[__rv], %[__val], [%[__ptr]]" "\n\t" 142 "cmp\t%[__rv],%[__val]" "\n\t" 143 "movs\t%[__tmp], #0" "\n\t" 144 #endif 145 "cmpne\t%[__tmp], #0" "\n\t" 146 "bne\t1b" "\n\t" 147 #ifdef _ARM_ARCH_7 148 "dmb" 149 #elif defined(_ARM_ARCH_6) 150 "mcr\tp15, 0, %[__tmp], c7, c10, 5" 151 #else 152 "nop" 153 #endif 154 : [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp) 155 : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory"); 156 return __rv; 157 } 158 #endif /* _KERNEL */ 159 160 static __inline void __attribute__((__unused__)) 161 __cpu_simple_lock_init(__cpu_simple_lock_t *alp) 162 { 163 164 *alp = __SIMPLELOCK_UNLOCKED; 165 #ifdef _ARM_ARCH_7 166 __asm __volatile("dsb"); 167 #endif 168 } 169 170 static __inline void __attribute__((__unused__)) 171 __cpu_simple_lock(__cpu_simple_lock_t *alp) 172 { 173 174 while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED) 175 continue; 176 } 177 178 static __inline int __attribute__((__unused__)) 179 __cpu_simple_lock_try(__cpu_simple_lock_t *alp) 180 { 181 182 return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED); 183 } 184 185 static __inline void __attribute__((__unused__)) 186 __cpu_simple_unlock(__cpu_simple_lock_t *alp) 187 { 188 189 #ifdef _ARM_ARCH_7 190 __asm __volatile("dmb"); 191 #endif 192 *alp = __SIMPLELOCK_UNLOCKED; 193 #ifdef _ARM_ARCH_7 194 __asm __volatile("dsb"); 195 #endif 196 } 197 198 #endif /* _ARM_LOCK_H_ */ 199