1 /* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM_CPUFUNC_PROTO_H_ 43 #define _ARM_CPUFUNC_PROTO_H_ 44 45 #ifdef _KERNEL 46 47 #if !defined(_MODULE) && defined(_KERNEL_OPT) 48 # include "opt_multiprocessor.h" 49 #endif 50 51 #include <sys/types.h> 52 #include <arm/armreg.h> 53 #include <arm/cpuconf.h> 54 55 #if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) 56 void arm3_cache_flush (void); 57 #endif /* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */ 58 59 #ifdef CPU_ARM2 60 u_int arm2_id (void); 61 #endif /* CPU_ARM2 */ 62 63 #ifdef CPU_ARM250 64 u_int arm250_id (void); 65 #endif 66 67 #ifdef CPU_ARM3 68 u_int arm3_control (u_int, u_int); 69 #endif /* CPU_ARM3 */ 70 71 #if defined(CPU_ARM6) || defined(CPU_ARM7) 72 void arm67_setttb (u_int, bool); 73 void arm67_tlb_flush (void); 74 void arm67_tlb_purge (vaddr_t); 75 void arm67_cache_flush (void); 76 void arm67_context_switch (u_int); 77 #endif /* CPU_ARM6 || CPU_ARM7 */ 78 79 #ifdef CPU_ARM6 80 void arm6_setup (char *); 81 #endif /* CPU_ARM6 */ 82 83 #ifdef CPU_ARM7 84 void arm7_setup (char *); 85 #endif /* CPU_ARM7 */ 86 87 #ifdef CPU_ARM7TDMI 88 int arm7_dataabt_fixup (void *); 89 void arm7tdmi_setup (char *); 90 void arm7tdmi_setttb (u_int, bool); 91 void arm7tdmi_tlb_flushID (void); 92 void arm7tdmi_tlb_flushID_SE (vaddr_t); 93 void arm7tdmi_cache_flushID (void); 94 void arm7tdmi_context_switch (u_int); 95 #endif /* CPU_ARM7TDMI */ 96 97 #ifdef CPU_ARM8 98 void arm8_setttb (u_int, bool); 99 void arm8_tlb_flushID (void); 100 void arm8_tlb_flushID_SE (vaddr_t); 101 void arm8_cache_flushID (void); 102 void arm8_cache_flushID_E (u_int); 103 void arm8_cache_cleanID (void); 104 void arm8_cache_cleanID_E (u_int); 105 void arm8_cache_purgeID (void); 106 void arm8_cache_purgeID_E (u_int entry); 107 108 void arm8_cache_syncI (void); 109 void arm8_cache_cleanID_rng (vaddr_t, vsize_t); 110 void arm8_cache_cleanD_rng (vaddr_t, vsize_t); 111 void arm8_cache_purgeID_rng (vaddr_t, vsize_t); 112 void arm8_cache_purgeD_rng (vaddr_t, vsize_t); 113 void arm8_cache_syncI_rng (vaddr_t, vsize_t); 114 115 void arm8_context_switch (u_int); 116 117 void arm8_setup (char *); 118 119 u_int arm8_clock_config (u_int, u_int); 120 #endif 121 122 #ifdef CPU_FA526 123 void fa526_setup (char *); 124 void fa526_setttb (u_int, bool); 125 void fa526_context_switch (u_int); 126 void fa526_cpu_sleep (int); 127 void fa526_tlb_flushI_SE (vaddr_t); 128 void fa526_tlb_flushID_SE (vaddr_t); 129 void fa526_flush_prefetchbuf (void); 130 void fa526_flush_brnchtgt_E (u_int); 131 132 void fa526_icache_sync_all (void); 133 void fa526_icache_sync_range(vaddr_t, vsize_t); 134 void fa526_dcache_wbinv_all (void); 135 void fa526_dcache_wbinv_range(vaddr_t, vsize_t); 136 void fa526_dcache_inv_range (vaddr_t, vsize_t); 137 void fa526_dcache_wb_range (vaddr_t, vsize_t); 138 void fa526_idcache_wbinv_all(void); 139 void fa526_idcache_wbinv_range(vaddr_t, vsize_t); 140 #endif 141 142 #ifdef CPU_SA110 143 void sa110_setup (char *); 144 void sa110_context_switch (u_int); 145 #endif /* CPU_SA110 */ 146 147 #if defined(CPU_SA1100) || defined(CPU_SA1110) 148 void sa11x0_drain_readbuf (void); 149 150 void sa11x0_context_switch (u_int); 151 void sa11x0_cpu_sleep (int); 152 153 void sa11x0_setup (char *); 154 #endif 155 156 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 157 void sa1_setttb (u_int, bool); 158 159 void sa1_tlb_flushID_SE (vaddr_t); 160 161 void sa1_cache_flushID (void); 162 void sa1_cache_flushI (void); 163 void sa1_cache_flushD (void); 164 void sa1_cache_flushD_SE (vaddr_t); 165 166 void sa1_cache_cleanID (void); 167 void sa1_cache_cleanD (void); 168 void sa1_cache_cleanD_E (u_int); 169 170 void sa1_cache_purgeID (void); 171 void sa1_cache_purgeID_E (u_int); 172 void sa1_cache_purgeD (void); 173 void sa1_cache_purgeD_E (u_int); 174 175 void sa1_cache_syncI (void); 176 void sa1_cache_cleanID_rng (vaddr_t, vsize_t); 177 void sa1_cache_cleanD_rng (vaddr_t, vsize_t); 178 void sa1_cache_purgeID_rng (vaddr_t, vsize_t); 179 void sa1_cache_purgeD_rng (vaddr_t, vsize_t); 180 void sa1_cache_syncI_rng (vaddr_t, vsize_t); 181 182 #endif 183 184 #ifdef CPU_ARM9 185 void arm9_setttb (u_int, bool); 186 187 void arm9_tlb_flushID_SE (vaddr_t); 188 189 void arm9_icache_sync_all (void); 190 void arm9_icache_sync_range (vaddr_t, vsize_t); 191 192 void arm9_dcache_wbinv_all (void); 193 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 194 void arm9_dcache_inv_range (vaddr_t, vsize_t); 195 void arm9_dcache_wb_range (vaddr_t, vsize_t); 196 197 void arm9_idcache_wbinv_all (void); 198 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 199 200 void arm9_context_switch (u_int); 201 202 void arm9_setup (char *); 203 204 extern unsigned arm9_dcache_sets_max; 205 extern unsigned arm9_dcache_sets_inc; 206 extern unsigned arm9_dcache_index_max; 207 extern unsigned arm9_dcache_index_inc; 208 #endif 209 210 #if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA) 211 void arm10_tlb_flushID_SE (vaddr_t); 212 void arm10_tlb_flushI_SE (vaddr_t); 213 214 void arm10_context_switch (u_int); 215 216 void arm10_setup (char *); 217 #endif 218 219 #if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA) 220 void armv5_ec_setttb (u_int, bool); 221 222 void armv5_ec_icache_sync_all (void); 223 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 224 225 void armv5_ec_dcache_wbinv_all (void); 226 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 227 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 228 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 229 230 void armv5_ec_idcache_wbinv_all (void); 231 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 232 #endif 233 234 #if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE) 235 void armv5_setttb (u_int, bool); 236 237 void armv5_icache_sync_all (void); 238 void armv5_icache_sync_range (vaddr_t, vsize_t); 239 240 void armv5_dcache_wbinv_all (void); 241 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 242 void armv5_dcache_inv_range (vaddr_t, vsize_t); 243 void armv5_dcache_wb_range (vaddr_t, vsize_t); 244 245 void armv5_idcache_wbinv_all (void); 246 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 247 248 extern unsigned armv5_dcache_sets_max; 249 extern unsigned armv5_dcache_sets_inc; 250 extern unsigned armv5_dcache_index_max; 251 extern unsigned armv5_dcache_index_inc; 252 #endif 253 254 #if defined(CPU_ARM11MPCORE) 255 void arm11mpcore_setup (char *); 256 #endif 257 258 #if defined(CPU_ARM11) 259 #if defined(ARM_MMU_EXTENDED) 260 void arm11_setttb (u_int, tlb_asid_t); 261 void arm11_context_switch (u_int, tlb_asid_t); 262 #else 263 void arm11_setttb (u_int, bool); 264 void arm11_context_switch (u_int); 265 #endif 266 267 void arm11_cpu_sleep (int); 268 void arm11_setup (char *string); 269 void arm11_tlb_flushID (void); 270 void arm11_tlb_flushI (void); 271 void arm11_tlb_flushD (void); 272 void arm11_tlb_flushID_SE (vaddr_t); 273 void arm11_tlb_flushI_SE (vaddr_t); 274 void arm11_tlb_flushD_SE (vaddr_t); 275 276 void armv11_dcache_wbinv_all (void); 277 void armv11_idcache_wbinv_all(void); 278 279 void arm11_drain_writebuf (void); 280 void arm11_sleep (int); 281 282 void armv6_setttb (u_int, bool); 283 284 void armv6_icache_sync_all (void); 285 void armv6_icache_sync_range (vaddr_t, vsize_t); 286 287 void armv6_dcache_wbinv_all (void); 288 void armv6_dcache_wbinv_range (vaddr_t, vsize_t); 289 void armv6_dcache_inv_range (vaddr_t, vsize_t); 290 void armv6_dcache_wb_range (vaddr_t, vsize_t); 291 292 void armv6_idcache_wbinv_all (void); 293 void armv6_idcache_wbinv_range (vaddr_t, vsize_t); 294 #endif 295 296 #if defined(CPU_ARMV7) 297 #if defined(ARM_MMU_EXTENDED) 298 void armv7_setttb(u_int, tlb_asid_t); 299 void armv7_context_switch(u_int, tlb_asid_t); 300 #else 301 void armv7_setttb(u_int, bool); 302 void armv7_context_switch(u_int); 303 #endif 304 305 void armv7_icache_sync_range(vaddr_t, vsize_t); 306 void armv7_icache_sync_all(void); 307 308 void armv7_dcache_inv_range(vaddr_t, vsize_t); 309 void armv7_dcache_wb_range(vaddr_t, vsize_t); 310 void armv7_dcache_wbinv_range(vaddr_t, vsize_t); 311 void armv7_dcache_wbinv_all(void); 312 313 void armv7_idcache_wbinv_range(vaddr_t, vsize_t); 314 void armv7_idcache_wbinv_all(void); 315 316 void armv7up_tlb_flushID(void); 317 void armv7up_tlb_flushI(void); 318 void armv7up_tlb_flushD(void); 319 320 void armv7up_tlb_flushID_SE(vaddr_t); 321 void armv7up_tlb_flushI_SE(vaddr_t); 322 void armv7up_tlb_flushD_SE(vaddr_t); 323 324 #ifdef MULTIPROCESSOR 325 void armv7mp_tlb_flushID(void); 326 void armv7mp_tlb_flushI(void); 327 void armv7mp_tlb_flushD(void); 328 329 void armv7mp_tlb_flushID_SE(vaddr_t); 330 void armv7mp_tlb_flushI_SE(vaddr_t); 331 void armv7mp_tlb_flushD_SE(vaddr_t); 332 #endif 333 334 void armv7_cpu_sleep(int); 335 void armv7_drain_writebuf(void); 336 void armv7_setup(char *string); 337 #endif /* CPU_ARMV7 */ 338 339 #if defined(CPU_PJ4B) 340 void pj4b_cpu_sleep(int); 341 void pj4bv7_setup(char *string); 342 void pj4b_config(void); 343 void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); 344 void pj4b_dcache_cfu_inv_range(vaddr_t, vsize_t); 345 void pj4b_dcache_cfu_wb_range(vaddr_t, vsize_t); 346 void pj4b_dcache_cfu_wbinv_range(vaddr_t, vsize_t); 347 #endif /* CPU_PJ4B */ 348 349 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) 350 void arm11x6_idcache_wbinv_all (void); 351 void arm11x6_dcache_wbinv_all (void); 352 void arm11x6_icache_sync_all (void); 353 void arm11x6_flush_prefetchbuf (void); 354 void arm11x6_icache_sync_range (vaddr_t, vsize_t); 355 void arm11x6_idcache_wbinv_range (vaddr_t, vsize_t); 356 void arm11x6_setup (char *string); 357 void arm11x6_sleep (int); /* no ref. for errata */ 358 #endif 359 #if defined(CPU_ARM1136) 360 void arm1136_sleep_rev0 (int); /* for errata 336501 */ 361 #endif 362 363 364 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 365 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 366 defined(CPU_FA526) || defined(CPU_XSCALE) || defined(CPU_SHEEVA) 367 368 void armv4_tlb_flushID (void); 369 void armv4_tlb_flushI (void); 370 void armv4_tlb_flushD (void); 371 void armv4_tlb_flushD_SE (vaddr_t); 372 373 void armv4_drain_writebuf (void); 374 #endif 375 376 #if defined(CPU_IXP12X0) 377 void ixp12x0_drain_readbuf (void); 378 void ixp12x0_context_switch (u_int); 379 void ixp12x0_setup (char *); 380 #endif 381 382 #if defined(CPU_XSCALE) 383 void xscale_cpwait (void); 384 385 void xscale_cpu_sleep (int); 386 387 u_int xscale_control (u_int, u_int); 388 389 void xscale_setttb (u_int, bool); 390 391 void xscale_tlb_flushID_SE (vaddr_t); 392 393 void xscale_cache_flushID (void); 394 void xscale_cache_flushI (void); 395 void xscale_cache_flushD (void); 396 void xscale_cache_flushD_SE (vaddr_t); 397 398 void xscale_cache_cleanID (void); 399 void xscale_cache_cleanD (void); 400 void xscale_cache_cleanD_E (u_int); 401 402 void xscale_cache_clean_minidata (void); 403 404 void xscale_cache_purgeID (void); 405 void xscale_cache_purgeID_E (u_int); 406 void xscale_cache_purgeD (void); 407 void xscale_cache_purgeD_E (u_int); 408 409 void xscale_cache_syncI (void); 410 void xscale_cache_cleanID_rng (vaddr_t, vsize_t); 411 void xscale_cache_cleanD_rng (vaddr_t, vsize_t); 412 void xscale_cache_purgeID_rng (vaddr_t, vsize_t); 413 void xscale_cache_purgeD_rng (vaddr_t, vsize_t); 414 void xscale_cache_syncI_rng (vaddr_t, vsize_t); 415 void xscale_cache_flushD_rng (vaddr_t, vsize_t); 416 417 void xscale_context_switch (u_int); 418 419 void xscale_setup (char *); 420 #endif /* CPU_XSCALE */ 421 422 #if defined(CPU_SHEEVA) 423 void sheeva_dcache_wbinv_range (vaddr_t, vsize_t); 424 void sheeva_dcache_inv_range (vaddr_t, vsize_t); 425 void sheeva_dcache_wb_range (vaddr_t, vsize_t); 426 void sheeva_idcache_wbinv_range (vaddr_t, vsize_t); 427 void sheeva_setup(char *); 428 void sheeva_cpu_sleep(int); 429 430 void sheeva_sdcache_inv_range(vaddr_t, paddr_t, vsize_t); 431 void sheeva_sdcache_wb_range(vaddr_t, paddr_t, vsize_t); 432 void sheeva_sdcache_wbinv_range(vaddr_t, paddr_t, vsize_t); 433 void sheeva_sdcache_wbinv_all(void); 434 #endif 435 436 #endif /* _KERNEL */ 437 438 #endif /* _ARM_CPUFUNC_PROTO_H_ */ 439