1 /* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM_CPUFUNC_H_ 43 #define _ARM_CPUFUNC_H_ 44 45 #ifdef __arm__ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 51 #include <arm/armreg.h> 52 #include <arm/cpuconf.h> 53 #include <arm/cpufunc_proto.h> 54 55 struct cpu_functions { 56 57 /* CPU functions */ 58 59 u_int (*cf_id) (void); 60 void (*cf_cpwait) (void); 61 62 /* MMU functions */ 63 64 u_int (*cf_control) (u_int, u_int); 65 void (*cf_domains) (u_int); 66 #if defined(ARM_MMU_EXTENDED) 67 void (*cf_setttb) (u_int, tlb_asid_t); 68 #else 69 void (*cf_setttb) (u_int, bool); 70 #endif 71 u_int (*cf_faultstatus) (void); 72 u_int (*cf_faultaddress) (void); 73 74 /* TLB functions */ 75 76 void (*cf_tlb_flushID) (void); 77 void (*cf_tlb_flushID_SE) (vaddr_t); 78 void (*cf_tlb_flushI) (void); 79 void (*cf_tlb_flushI_SE) (vaddr_t); 80 void (*cf_tlb_flushD) (void); 81 void (*cf_tlb_flushD_SE) (vaddr_t); 82 83 /* 84 * Cache operations: 85 * 86 * We define the following primitives: 87 * 88 * icache_sync_all Synchronize I-cache 89 * icache_sync_range Synchronize I-cache range 90 * 91 * dcache_wbinv_all Write-back and Invalidate D-cache 92 * dcache_wbinv_range Write-back and Invalidate D-cache range 93 * dcache_inv_range Invalidate D-cache range 94 * dcache_wb_range Write-back D-cache range 95 * 96 * idcache_wbinv_all Write-back and Invalidate D-cache, 97 * Invalidate I-cache 98 * idcache_wbinv_range Write-back and Invalidate D-cache, 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * 107 * I-cache Synch (all or range): 108 * The goal is to synchronize the instruction stream, 109 * so you may beed to write-back dirty D-cache blocks 110 * first. If a range is requested, and you can't 111 * synchronize just a range, you have to hit the whole 112 * thing. 113 * 114 * D-cache Write-Back and Invalidate range: 115 * If you can't WB-Inv a range, you must WB-Inv the 116 * entire D-cache. 117 * 118 * D-cache Invalidate: 119 * If you can't Inv the D-cache, you must Write-Back 120 * and Invalidate. Code that uses this operation 121 * MUST NOT assume that the D-cache will not be written 122 * back to memory. 123 * 124 * D-cache Write-Back: 125 * If you can't Write-back without doing an Inv, 126 * that's fine. Then treat this as a WB-Inv. 127 * Skipping the invalidate is merely an optimization. 128 * 129 * All operations: 130 * Valid virtual addresses must be passed to each 131 * cache operation. 132 */ 133 void (*cf_icache_sync_all) (void); 134 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 135 136 void (*cf_dcache_wbinv_all) (void); 137 void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t); 138 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 139 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 140 141 void (*cf_sdcache_wbinv_range)(vaddr_t, paddr_t, psize_t); 142 void (*cf_sdcache_inv_range) (vaddr_t, paddr_t, psize_t); 143 void (*cf_sdcache_wb_range) (vaddr_t, paddr_t, psize_t); 144 145 void (*cf_idcache_wbinv_all) (void); 146 void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t); 147 148 /* Other functions */ 149 150 void (*cf_flush_prefetchbuf) (void); 151 void (*cf_drain_writebuf) (void); 152 void (*cf_flush_brnchtgt_C) (void); 153 void (*cf_flush_brnchtgt_E) (u_int); 154 155 void (*cf_sleep) (int mode); 156 157 /* Soft functions */ 158 159 int (*cf_dataabt_fixup) (void *); 160 int (*cf_prefetchabt_fixup) (void *); 161 162 #if defined(ARM_MMU_EXTENDED) 163 void (*cf_context_switch) (u_int, tlb_asid_t); 164 #else 165 void (*cf_context_switch) (u_int); 166 #endif 167 168 void (*cf_setup) (char *); 169 }; 170 171 extern struct cpu_functions cpufuncs; 172 extern u_int cputype; 173 174 #define cpu_idnum() cpufuncs.cf_id() 175 176 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 177 #define cpu_domains(d) cpufuncs.cf_domains(d) 178 #define cpu_setttb(t, f) cpufuncs.cf_setttb(t, f) 179 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 180 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 181 182 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 183 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 184 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 185 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 186 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 187 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 188 189 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 190 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 191 192 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 193 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 194 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 195 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 196 197 #define cpu_sdcache_wbinv_range(a, b, s) cpufuncs.cf_sdcache_wbinv_range((a), (b), (s)) 198 #define cpu_sdcache_inv_range(a, b, s) cpufuncs.cf_sdcache_inv_range((a), (b), (s)) 199 #define cpu_sdcache_wb_range(a, b, s) cpufuncs.cf_sdcache_wb_range((a), (b), (s)) 200 201 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 202 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 203 204 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 205 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 206 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 207 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 208 209 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 210 211 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 212 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 213 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 214 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 215 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 216 217 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 218 #define cpu_setup(a) cpufuncs.cf_setup(a) 219 220 int set_cpufuncs (void); 221 int set_cpufuncs_id (u_int); 222 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 223 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 224 225 void cpufunc_nullop (void); 226 int cpufunc_null_fixup (void *); 227 int early_abort_fixup (void *); 228 int late_abort_fixup (void *); 229 u_int cpufunc_id (void); 230 u_int cpufunc_control (u_int, u_int); 231 void cpufunc_domains (u_int); 232 u_int cpufunc_faultstatus (void); 233 u_int cpufunc_faultaddress (void); 234 235 #define setttb cpu_setttb 236 #define drain_writebuf cpu_drain_writebuf 237 238 239 #if defined(CPU_XSCALE) 240 #define cpu_cpwait() cpufuncs.cf_cpwait() 241 #endif 242 243 #ifndef cpu_cpwait 244 #define cpu_cpwait() 245 #endif 246 247 /* 248 * Macros for manipulating CPU interrupts 249 */ 250 static __inline uint32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__)); 251 static __inline uint32_t disable_interrupts(uint32_t mask) __attribute__((__unused__)); 252 static __inline uint32_t enable_interrupts(uint32_t mask) __attribute__((__unused__)); 253 254 static __inline uint32_t 255 __set_cpsr_c(uint32_t bic, uint32_t eor) 256 { 257 uint32_t tmp, ret; 258 259 __asm volatile( 260 "mrs %0, cpsr\n" /* Get the CPSR */ 261 "bic %1, %0, %2\n" /* Clear bits */ 262 "eor %1, %1, %3\n" /* XOR bits */ 263 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 264 : "=&r" (ret), "=&r" (tmp) 265 : "r" (bic), "r" (eor) : "memory"); 266 267 return ret; 268 } 269 270 static __inline uint32_t 271 disable_interrupts(uint32_t mask) 272 { 273 uint32_t tmp, ret; 274 mask &= (I32_bit | F32_bit); 275 276 __asm volatile( 277 "mrs %0, cpsr\n" /* Get the CPSR */ 278 "orr %1, %0, %2\n" /* set bits */ 279 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 280 : "=&r" (ret), "=&r" (tmp) 281 : "r" (mask) 282 : "memory"); 283 284 return ret; 285 } 286 287 static __inline uint32_t 288 enable_interrupts(uint32_t mask) 289 { 290 uint32_t ret; 291 mask &= (I32_bit | F32_bit); 292 293 /* Get the CPSR */ 294 __asm __volatile("mrs\t%0, cpsr\n" : "=r"(ret)); 295 #ifdef _ARM_ARCH_6 296 if (__builtin_constant_p(mask)) { 297 switch (mask) { 298 case I32_bit | F32_bit: 299 __asm __volatile("cpsie\tif"); 300 break; 301 case I32_bit: 302 __asm __volatile("cpsie\ti"); 303 break; 304 case F32_bit: 305 __asm __volatile("cpsie\tf"); 306 break; 307 default: 308 break; 309 } 310 return ret; 311 } 312 #endif /* _ARM_ARCH_6 */ 313 314 /* Set the control field of CPSR */ 315 __asm volatile("msr\tcpsr_c, %0" :: "r"(ret & ~mask)); 316 317 return ret; 318 } 319 320 #define restore_interrupts(old_cpsr) \ 321 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 322 323 static inline void cpsie(register_t psw) __attribute__((__unused__)); 324 static inline register_t cpsid(register_t psw) __attribute__((__unused__)); 325 326 static inline void 327 cpsie(register_t psw) 328 { 329 #ifdef _ARM_ARCH_6 330 if (!__builtin_constant_p(psw)) { 331 enable_interrupts(psw); 332 return; 333 } 334 switch (psw & (I32_bit|F32_bit)) { 335 case I32_bit: __asm("cpsie\ti"); break; 336 case F32_bit: __asm("cpsie\tf"); break; 337 case I32_bit|F32_bit: __asm("cpsie\tif"); break; 338 } 339 #else 340 enable_interrupts(psw); 341 #endif 342 } 343 344 static inline register_t 345 cpsid(register_t psw) 346 { 347 #ifdef _ARM_ARCH_6 348 register_t oldpsw; 349 if (!__builtin_constant_p(psw)) 350 return disable_interrupts(psw); 351 352 __asm("mrs %0, cpsr" : "=r"(oldpsw)); 353 switch (psw & (I32_bit|F32_bit)) { 354 case I32_bit: __asm("cpsid\ti"); break; 355 case F32_bit: __asm("cpsid\tf"); break; 356 case I32_bit|F32_bit: __asm("cpsid\tif"); break; 357 } 358 return oldpsw; 359 #else 360 return disable_interrupts(psw); 361 #endif 362 } 363 364 365 /* Functions to manipulate the CPSR. */ 366 u_int SetCPSR(u_int, u_int); 367 u_int GetCPSR(void); 368 369 370 /* 371 * CPU functions from locore.S 372 */ 373 374 void cpu_reset (void) __dead; 375 376 /* 377 * Cache info variables. 378 */ 379 #define CACHE_TYPE_VIVT 0 380 #define CACHE_TYPE_xxPT 1 381 #define CACHE_TYPE_VIPT 1 382 #define CACHE_TYPE_PIxx 2 383 #define CACHE_TYPE_PIPT 3 384 385 /* PRIMARY CACHE VARIABLES */ 386 struct arm_cache_info { 387 u_int icache_size; 388 u_int icache_line_size; 389 u_int icache_ways; 390 u_int icache_way_size; 391 u_int icache_sets; 392 393 u_int dcache_size; 394 u_int dcache_line_size; 395 u_int dcache_ways; 396 u_int dcache_way_size; 397 u_int dcache_sets; 398 399 uint8_t cache_type; 400 bool cache_unified; 401 uint8_t icache_type; 402 uint8_t dcache_type; 403 }; 404 405 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 406 extern u_int arm_cache_prefer_mask; 407 #endif 408 extern u_int arm_dcache_align; 409 extern u_int arm_dcache_align_mask; 410 411 extern struct arm_cache_info arm_pcache; 412 extern struct arm_cache_info arm_scache; 413 414 extern uint32_t cpu_ttb; 415 416 #endif /* _KERNEL */ 417 418 #if defined(_KERNEL) || defined(_KMEMUSER) 419 /* 420 * Miscellany 421 */ 422 423 int get_pc_str_offset (void); 424 425 bool cpu_gtmr_exists_p(void); 426 u_int cpu_clusterid(void); 427 bool cpu_earlydevice_va_p(void); 428 429 /* 430 * Functions to manipulate cpu r13 431 * (in arm/arm32/setstack.S) 432 */ 433 434 void set_stackptr (u_int, u_int); 435 u_int get_stackptr (u_int); 436 437 #endif /* _KERNEL || _KMEMUSER */ 438 439 #elif defined(__aarch64__) 440 441 #include <aarch64/cpufunc.h> 442 443 #endif /* __arm__/__aarch64__ */ 444 445 #endif /* _ARM_CPUFUNC_H_ */ 446 447 /* End of cpufunc.h */ 448