1 /* $NetBSD: cpufunc.h,v 1.14 2001/11/29 02:24:59 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #include <sys/types.h> 46 47 #ifdef _KERNEL 48 #ifndef _LKM 49 #include "opt_cputypes.h" 50 #endif 51 52 struct cpu_functions { 53 54 /* CPU functions */ 55 56 u_int (*cf_id) __P((void)); 57 void (*cf_cpwait) __P((void)); 58 59 /* MMU functions */ 60 61 u_int (*cf_control) __P((u_int bic, u_int eor)); 62 void (*cf_domains) __P((u_int domains)); 63 void (*cf_setttb) __P((u_int ttb)); 64 u_int (*cf_faultstatus) __P((void)); 65 u_int (*cf_faultaddress) __P((void)); 66 67 /* TLB functions */ 68 69 void (*cf_tlb_flushID) __P((void)); 70 void (*cf_tlb_flushID_SE) __P((u_int va)); 71 void (*cf_tlb_flushI) __P((void)); 72 void (*cf_tlb_flushI_SE) __P((u_int va)); 73 void (*cf_tlb_flushD) __P((void)); 74 void (*cf_tlb_flushD_SE) __P((u_int va)); 75 76 /* Cache functions */ 77 78 void (*cf_cache_flushID) __P((void)); 79 void (*cf_cache_flushID_SE) __P((u_int va)); 80 void (*cf_cache_flushI) __P((void)); 81 void (*cf_cache_flushI_SE) __P((u_int va)); 82 void (*cf_cache_flushD) __P((void)); 83 void (*cf_cache_flushD_SE) __P((u_int va)); 84 85 void (*cf_cache_cleanID) __P((void)); 86 void (*cf_cache_cleanID_E) __P((u_int imp)); 87 void (*cf_cache_cleanD) __P((void)); 88 void (*cf_cache_cleanD_E) __P((u_int imp)); 89 90 void (*cf_cache_purgeID) __P((void)); 91 void (*cf_cache_purgeID_E) __P((u_int imp)); 92 void (*cf_cache_purgeD) __P((void)); 93 void (*cf_cache_purgeD_E) __P((u_int imp)); 94 95 /* Other functions */ 96 97 void (*cf_flush_prefetchbuf) __P((void)); 98 void (*cf_drain_writebuf) __P((void)); 99 void (*cf_flush_brnchtgt_C) __P((void)); 100 void (*cf_flush_brnchtgt_E) __P((u_int va)); 101 102 void (*cf_sleep) __P((int mode)); 103 104 /* Soft functions */ 105 106 void (*cf_cache_syncI) __P((void)); 107 void (*cf_cache_cleanID_rng) __P((u_int start, u_int len)); 108 void (*cf_cache_cleanD_rng) __P((u_int start, u_int len)); 109 void (*cf_cache_purgeID_rng) __P((u_int start, u_int len)); 110 void (*cf_cache_purgeD_rng) __P((u_int start, u_int len)); 111 void (*cf_cache_syncI_rng) __P((u_int start, u_int len)); 112 113 int (*cf_dataabt_fixup) __P((void *arg)); 114 int (*cf_prefetchabt_fixup) __P((void *arg)); 115 116 void (*cf_context_switch) __P((void)); 117 118 void (*cf_setup) __P((char *string)); 119 }; 120 121 extern struct cpu_functions cpufuncs; 122 extern u_int cputype; 123 124 #define cpu_id() cpufuncs.cf_id() 125 #define cpu_cpwait() cpufuncs.cf_cpwait() 126 127 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 128 #define cpu_domains(d) cpufuncs.cf_domains(d) 129 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 130 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 131 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 132 133 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 134 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 135 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 136 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 137 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 138 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 139 140 #define cpu_cache_flushID() cpufuncs.cf_cache_flushID() 141 #define cpu_cache_flushID_SE(e) cpufuncs.cf_cache_flushID_SE(e) 142 #define cpu_cache_flushI() cpufuncs.cf_cache_flushI() 143 #define cpu_cache_flushI_SE(e) cpufuncs.cf_cache_flushI_SE(e) 144 #define cpu_cache_flushD() cpufuncs.cf_cache_flushD() 145 #define cpu_cache_flushD_SE(e) cpufuncs.cf_cache_flushD_SE(e) 146 #define cpu_cache_cleanID() cpufuncs.cf_cache_cleanID() 147 #define cpu_cache_cleanID_E(e) cpufuncs.cf_cache_cleanID_E(e) 148 #define cpu_cache_cleanD() cpufuncs.cf_cache_cleanD() 149 #define cpu_cache_cleanD_E(e) cpufuncs.cf_cache_cleanD_E(e) 150 #define cpu_cache_purgeID() cpufuncs.cf_cache_purgeID() 151 #define cpu_cache_purgeID_E(e) cpufuncs.cf_cache_purgeID_E(e) 152 #define cpu_cache_purgeD() cpufuncs.cf_cache_purgeD() 153 #define cpu_cache_purgeD_E(e) cpufuncs.cf_cache_purgeD_E(e) 154 155 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 156 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 157 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 158 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 159 160 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 161 162 #define cpu_cache_syncI() cpufuncs.cf_cache_syncI() 163 #define cpu_cache_cleanID_rng(s,l) cpufuncs.cf_cache_cleanID_rng(s,l) 164 #define cpu_cache_cleanD_rng(s,l) cpufuncs.cf_cache_cleanD_rng(s,l) 165 #define cpu_cache_purgeID_rng(s,l) cpufuncs.cf_cache_purgeID_rng(s,l) 166 #define cpu_cache_purgeD_rng(s,l) cpufuncs.cf_cache_purgeD_rng(s,l) 167 #define cpu_cache_syncI_rng(s,l) cpufuncs.cf_cache_syncI_rng(s,l) 168 169 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 170 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 171 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 172 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 173 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 174 175 #define cpu_setup(a) cpufuncs.cf_setup(a) 176 177 int set_cpufuncs __P((void)); 178 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 179 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 180 181 void cpufunc_nullop __P((void)); 182 int cpufunc_null_fixup __P((void *)); 183 int early_abort_fixup __P((void *)); 184 int late_abort_fixup __P((void *)); 185 u_int cpufunc_id __P((void)); 186 u_int cpufunc_control __P((u_int clear, u_int bic)); 187 void cpufunc_domains __P((u_int domains)); 188 u_int cpufunc_faultstatus __P((void)); 189 u_int cpufunc_faultaddress __P((void)); 190 191 #ifdef CPU_ARM3 192 u_int arm3_control __P((u_int clear, u_int bic)); 193 void arm3_cache_flush __P((void)); 194 #endif /* CPU_ARM3 */ 195 196 #if defined(CPU_ARM6) || defined(CPU_ARM7) 197 void arm67_setttb __P((u_int ttb)); 198 void arm67_tlb_flush __P((void)); 199 void arm67_tlb_purge __P((u_int va)); 200 void arm67_cache_flush __P((void)); 201 void arm67_context_switch __P((void)); 202 #endif /* CPU_ARM6 || CPU_ARM7 */ 203 204 #ifdef CPU_ARM6 205 void arm6_setup __P((char *string)); 206 #endif /* CPU_ARM6 */ 207 208 #ifdef CPU_ARM7 209 void arm7_setup __P((char *string)); 210 #endif /* CPU_ARM7 */ 211 212 #ifdef CPU_ARM7TDMI 213 int arm7_dataabt_fixup __P((void *arg)); 214 void arm7tdmi_setup __P((char *string)); 215 void arm7tdmi_setttb __P((u_int ttb)); 216 void arm7tdmi_tlb_flushID __P((void)); 217 void arm7tdmi_tlb_flushID_SE __P((u_int va)); 218 void arm7tdmi_cache_flushID __P((void)); 219 void arm7tdmi_context_switch __P((void)); 220 #endif /* CPU_ARM7TDMI */ 221 222 #ifdef CPU_ARM8 223 void arm8_setttb __P((u_int ttb)); 224 void arm8_tlb_flushID __P((void)); 225 void arm8_tlb_flushID_SE __P((u_int va)); 226 void arm8_cache_flushID __P((void)); 227 void arm8_cache_flushID_E __P((u_int entry)); 228 void arm8_cache_cleanID __P((void)); 229 void arm8_cache_cleanID_E __P((u_int entry)); 230 void arm8_cache_purgeID __P((void)); 231 void arm8_cache_purgeID_E __P((u_int entry)); 232 233 void arm8_cache_syncI __P((void)); 234 void arm8_cache_cleanID_rng __P((u_int start, u_int end)); 235 void arm8_cache_cleanD_rng __P((u_int start, u_int end)); 236 void arm8_cache_purgeID_rng __P((u_int start, u_int end)); 237 void arm8_cache_purgeD_rng __P((u_int start, u_int end)); 238 void arm8_cache_syncI_rng __P((u_int start, u_int end)); 239 240 void arm8_context_switch __P((void)); 241 242 void arm8_setup __P((char *string)); 243 244 u_int arm8_clock_config __P((u_int, u_int)); 245 #endif 246 247 #ifdef CPU_ARM9 248 void arm9_setttb __P((u_int)); 249 250 void arm9_tlb_flushID_SE __P((u_int va)); 251 252 void arm9_cache_flushID __P((void)); 253 void arm9_cache_flushID_SE __P((u_int)); 254 void arm9_cache_flushI __P((void)); 255 void arm9_cache_flushI_SE __P((u_int)); 256 void arm9_cache_flushD __P((void)); 257 void arm9_cache_flushD_SE __P((u_int)); 258 259 void arm9_cache_cleanID __P((void)); 260 261 void arm9_cache_syncI __P((void)); 262 void arm9_cache_flushID_rng __P((u_int, u_int)); 263 void arm9_cache_flushD_rng __P((u_int, u_int)); 264 void arm9_cache_syncI_rng __P((u_int, u_int)); 265 266 void arm9_context_switch __P((void)); 267 268 void arm9_setup __P((char *string)); 269 #endif 270 271 #if defined(CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE) 272 void armv4_tlb_flushID __P((void)); 273 void armv4_tlb_flushI __P((void)); 274 void armv4_tlb_flushD __P((void)); 275 void armv4_tlb_flushD_SE __P((u_int va)); 276 277 void armv4_drain_writebuf __P((void)); 278 #endif 279 280 #ifdef CPU_SA110 281 void sa110_setttb __P((u_int ttb)); 282 283 void sa110_tlb_flushID_SE __P((u_int va)); 284 285 void sa110_cache_flushID __P((void)); 286 void sa110_cache_flushI __P((void)); 287 void sa110_cache_flushD __P((void)); 288 void sa110_cache_flushD_SE __P((u_int entry)); 289 290 void sa110_cache_cleanID __P((void)); 291 void sa110_cache_cleanD __P((void)); 292 void sa110_cache_cleanD_E __P((u_int entry)); 293 294 void sa110_cache_purgeID __P((void)); 295 void sa110_cache_purgeID_E __P((u_int entry)); 296 void sa110_cache_purgeD __P((void)); 297 void sa110_cache_purgeD_E __P((u_int entry)); 298 299 void sa110_cache_syncI __P((void)); 300 void sa110_cache_cleanID_rng __P((u_int start, u_int end)); 301 void sa110_cache_cleanD_rng __P((u_int start, u_int end)); 302 void sa110_cache_purgeID_rng __P((u_int start, u_int end)); 303 void sa110_cache_purgeD_rng __P((u_int start, u_int end)); 304 void sa110_cache_syncI_rng __P((u_int start, u_int end)); 305 306 void sa110_context_switch __P((void)); 307 308 void sa110_setup __P((char *string)); 309 #endif /* CPU_SA110 */ 310 311 #ifdef CPU_XSCALE 312 void xscale_cpwait __P((void)); 313 314 u_int xscale_control __P((u_int clear, u_int bic)); 315 316 void xscale_setttb __P((u_int ttb)); 317 318 void xscale_tlb_flushID_SE __P((u_int va)); 319 320 void xscale_cache_flushID __P((void)); 321 void xscale_cache_flushI __P((void)); 322 void xscale_cache_flushD __P((void)); 323 void xscale_cache_flushD_SE __P((u_int entry)); 324 325 void xscale_cache_cleanID __P((void)); 326 void xscale_cache_cleanD __P((void)); 327 void xscale_cache_cleanD_E __P((u_int entry)); 328 329 void xscale_cache_purgeID __P((void)); 330 void xscale_cache_purgeID_E __P((u_int entry)); 331 void xscale_cache_purgeD __P((void)); 332 void xscale_cache_purgeD_E __P((u_int entry)); 333 334 void xscale_cache_syncI __P((void)); 335 void xscale_cache_cleanID_rng __P((u_int start, u_int end)); 336 void xscale_cache_cleanD_rng __P((u_int start, u_int end)); 337 void xscale_cache_purgeID_rng __P((u_int start, u_int end)); 338 void xscale_cache_purgeD_rng __P((u_int start, u_int end)); 339 void xscale_cache_syncI_rng __P((u_int start, u_int end)); 340 341 /* Used in write-through mode. */ 342 void xscale_cache_flushID_rng __P((u_int start, u_int end)); 343 void xscale_cache_flushD_rng __P((u_int start, u_int end)); 344 void xscale_cache_flushI_rng __P((u_int start, u_int end)); 345 346 void xscale_context_switch __P((void)); 347 348 void xscale_setup __P((char *string)); 349 #endif /* CPU_XSCALE */ 350 351 #define tlb_flush cpu_tlb_flushID 352 #define setttb cpu_setttb 353 #define cache_clean cpu_cache_purgeID 354 #define sync_caches cpu_cache_syncI 355 #define sync_icache cpu_cache_syncI 356 #define drain_writebuf cpu_drain_writebuf 357 358 /* 359 * Macros for manipulating CPU interrupts 360 */ 361 362 #define disable_interrupts(mask) \ 363 (SetCPSR((mask) & (I32_bit | F32_bit), (mask) & (I32_bit | F32_bit))) 364 365 #define enable_interrupts(mask) \ 366 (SetCPSR((mask) & (I32_bit | F32_bit), 0)) 367 368 #define restore_interrupts(old_cpsr) \ 369 (SetCPSR((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 370 371 /* 372 * Functions to manipulate the CPSR 373 * (in arm/arm32/setcpsr.S) 374 */ 375 376 u_int SetCPSR __P((u_int bic, u_int eor)); 377 u_int GetCPSR __P((void)); 378 379 /* 380 * Functions to manipulate cpu r13 381 * (in arm/arm32/setstack.S) 382 */ 383 384 void set_stackptr __P((u_int mode, u_int address)); 385 u_int get_stackptr __P((u_int mode)); 386 387 /* 388 * Miscellany 389 */ 390 391 int get_pc_str_offset __P((void)); 392 393 /* 394 * CPU functions from locore.S 395 */ 396 397 void cpu_reset __P((void)) __attribute__((__noreturn__)); 398 399 /* 400 * Cache info variables. 401 */ 402 403 /* PRIMARY CACHE VARIABLES */ 404 int arm_picache_size; 405 int arm_picache_line_size; 406 int arm_picache_ways; 407 408 int arm_pdcache_size; /* and unified */ 409 int arm_pdcache_line_size; 410 int arm_pdcache_ways; 411 412 int arm_pcache_type; 413 int arm_pcache_unified; 414 415 int arm_dcache_align; 416 int arm_dcache_align_mask; 417 418 #endif /* _KERNEL */ 419 #endif /* _ARM32_CPUFUNC_H_ */ 420 421 /* End of cpufunc.h */ 422