xref: /netbsd-src/sys/arch/arm/include/cpuconf.h (revision e5548b402ae4c44fb816de42c7bba9581ce23ef5)
1 /*	$NetBSD: cpuconf.h,v 1.12 2005/12/11 12:16:46 christos Exp $	*/
2 
3 /*
4  * Copyright (c) 2002 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef _ARM_CPUCONF_H_
39 #define	_ARM_CPUCONF_H_
40 
41 #if defined(_KERNEL_OPT)
42 #include "opt_cputypes.h"
43 #endif /* _KERNEL_OPT */
44 
45 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
46 #define	__CPU_XSCALE_PXA2XX
47 #endif
48 
49 #ifdef CPU_XSCALE_PXA2X0
50 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
51 #endif
52 
53 /*
54  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
55  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
56  * YOU ARE ADDING SUPPORT FOR.
57  */
58 
59 /*
60  * Step 1: Count the number of CPU types configured into the kernel.
61  */
62 #if defined(_KERNEL_OPT)
63 #define	CPU_NTYPES	(defined(CPU_ARM2) + defined(CPU_ARM250) +	\
64 			 defined(CPU_ARM3) +				\
65 			 defined(CPU_ARM6) + defined(CPU_ARM7) +	\
66 			 defined(CPU_ARM7TDMI) +			\
67 			 defined(CPU_ARM8) + defined(CPU_ARM9) +	\
68 			 defined(CPU_ARM10) +				\
69 			 defined(CPU_ARM11) +				\
70 			 defined(CPU_SA110) + defined(CPU_SA1100) +	\
71 			 defined(CPU_SA1110) +				\
72 			 defined(CPU_IXP12X0) +				\
73 			 defined(CPU_XSCALE_80200) +			\
74 			 defined(CPU_XSCALE_80321) +			\
75 			 defined(__CPU_XSCALE_PXA2XX) +			\
76 			 defined(CPU_XSCALE_IXP425))
77 #else
78 #define	CPU_NTYPES	2
79 #endif /* _KERNEL_OPT */
80 
81 /*
82  * Step 2: Determine which ARM architecture versions are configured.
83  */
84 #if !defined(_KERNEL_OPT) ||						\
85     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
86 #define	ARM_ARCH_2	1
87 #else
88 #define	ARM_ARCH_2	0
89 #endif
90 
91 #if !defined(_KERNEL_OPT) ||						\
92     (defined(CPU_ARM6) || defined(CPU_ARM7))
93 #define	ARM_ARCH_3	1
94 #else
95 #define	ARM_ARCH_3	0
96 #endif
97 
98 #if !defined(_KERNEL_OPT) ||						\
99     (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) ||	\
100      defined(CPU_SA110) || defined(CPU_SA1100) || \
101      defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
102 #define	ARM_ARCH_4	1
103 #else
104 #define	ARM_ARCH_4	0
105 #endif
106 
107 #if !defined(_KERNEL_OPT) ||						\
108     (defined(CPU_ARM10) || defined(CPU_XSCALE_80200) ||			\
109      defined(CPU_XSCALE_80321) || defined(__CPU_XSCALE_PXA2XX))
110 #define	ARM_ARCH_5	1
111 #else
112 #define	ARM_ARCH_5	0
113 #endif
114 
115 #if defined(CPU_ARM11)
116 #define ARM_ARCH_6	1
117 #else
118 #define ARM_ARCH_6	0
119 #endif
120 
121 #define	ARM_NARCH	(ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
122 			 ARM_ARCH_5 + ARM_ARCH_6)
123 #if ARM_NARCH == 0
124 #error ARM_NARCH is 0
125 #endif
126 
127 #if ARM_ARCH_5 || ARM_ARCH_6
128 /*
129  * We could support Thumb code on v4T, but the lack of clean interworking
130  * makes that hard.
131  */
132 #define THUMB_CODE
133 #endif
134 
135 /*
136  * Step 3: Define which MMU classes are configured:
137  *
138  *	ARM_MMU_MEMC		Prehistoric, external memory controller
139  *				and MMU for ARMv2 CPUs.
140  *
141  *	ARM_MMU_GENERIC		Generic ARM MMU, compatible with ARM6.
142  *
143  *	ARM_MMU_SA1		StrongARM SA-1 MMU.  Compatible with generic
144  *				ARM MMU, but has no write-through cache mode.
145  *
146  *	ARM_MMU_XSCALE		XScale MMU.  Compatible with generic ARM
147  *				MMU, but also has several extensions which
148  *				require different PTE layout to use.
149  */
150 #if !defined(_KERNEL_OPT) ||						\
151     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
152 #define	ARM_MMU_MEMC		1
153 #else
154 #define	ARM_MMU_MEMC		0
155 #endif
156 
157 #if !defined(_KERNEL_OPT) ||						\
158     (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) ||	\
159      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM10) ||	\
160      defined(CPU_ARM11))
161 #define	ARM_MMU_GENERIC		1
162 #else
163 #define	ARM_MMU_GENERIC		0
164 #endif
165 
166 #if !defined(_KERNEL_OPT) ||						\
167     (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
168      defined(CPU_IXP12X0))
169 #define	ARM_MMU_SA1		1
170 #else
171 #define	ARM_MMU_SA1		0
172 #endif
173 
174 #if !defined(_KERNEL_OPT) ||						\
175     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
176      defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
177 #define	ARM_MMU_XSCALE		1
178 #else
179 #define	ARM_MMU_XSCALE		0
180 #endif
181 
182 #define	ARM_NMMUS		(ARM_MMU_MEMC + ARM_MMU_GENERIC +	\
183 				 ARM_MMU_SA1 + ARM_MMU_XSCALE)
184 #if ARM_NMMUS == 0
185 #error ARM_NMMUS is 0
186 #endif
187 
188 /*
189  * Step 4: Define features that may be present on a subset of CPUs
190  *
191  *	ARM_XSCALE_PMU		Performance Monitoring Unit on 80200 and 80321
192  */
193 
194 #if !defined(_KERNEL_OPT) ||						\
195     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
196 #define ARM_XSCALE_PMU	1
197 #else
198 #define ARM_XSCALE_PMU	0
199 #endif
200 
201 #endif /* _ARM_CPUCONF_H_ */
202