1 /* $NetBSD: cpuconf.h,v 1.19 2010/10/02 05:37:58 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #endif /* _KERNEL_OPT */ 44 45 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 46 #define __CPU_XSCALE_PXA2XX 47 #endif 48 49 #ifdef CPU_XSCALE_PXA2X0 50 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270. 51 #endif 52 53 /* 54 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 55 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 56 * YOU ARE ADDING SUPPORT FOR. 57 */ 58 59 #if 0 60 /* 61 * Step 1: Count the number of CPU types configured into the kernel. 62 */ 63 #if defined(_KERNEL_OPT) 64 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 65 defined(CPU_ARM3) + \ 66 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 67 defined(CPU_ARM7TDMI) + \ 68 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 69 defined(CPU_ARM9E) + \ 70 defined(CPU_ARM10) + \ 71 defined(CPU_ARM11) + \ 72 defined(CPU_ARM1136) + \ 73 defined(CPU_ARM1176) + \ 74 defined(CPU_CORTEX) + \ 75 defined(CPU_CORTEXA8) + \ 76 defined(CPU_CORTEXA9) + \ 77 defined(CPU_SA110) + defined(CPU_SA1100) + \ 78 defined(CPU_SA1110) + \ 79 defined(CPU_FA526) + \ 80 defined(CPU_IXP12X0) + \ 81 defined(CPU_XSCALE_80200) + \ 82 defined(CPU_XSCALE_80321) + \ 83 defined(__CPU_XSCALE_PXA2XX) + \ 84 defined(CPU_XSCALE_IXP425)) + \ 85 defined(CPU_SHEEVA)) 86 #else 87 #define CPU_NTYPES 2 88 #endif /* _KERNEL_OPT */ 89 #endif 90 91 /* 92 * Step 2: Determine which ARM architecture versions are configured. 93 */ 94 #if !defined(_KERNEL_OPT) || \ 95 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 96 #define ARM_ARCH_2 1 97 #else 98 #define ARM_ARCH_2 0 99 #endif 100 101 #if !defined(_KERNEL_OPT) || \ 102 (defined(CPU_ARM6) || defined(CPU_ARM7)) 103 #define ARM_ARCH_3 1 104 #else 105 #define ARM_ARCH_3 0 106 #endif 107 108 #if !defined(_KERNEL_OPT) || \ 109 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 110 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \ 111 defined(CPU_SA1110) || defined(CPU_IXP12X0)) 112 #define ARM_ARCH_4 1 113 #else 114 #define ARM_ARCH_4 0 115 #endif 116 117 #if !defined(_KERNEL_OPT) || \ 118 (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 119 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 120 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) || \ 121 defined(CPU_SHEEVA) 122 #define ARM_ARCH_5 1 123 #else 124 #define ARM_ARCH_5 0 125 #endif 126 127 #if defined(CPU_ARM11) || defined(CPU_CORTEXA8) 128 #define ARM_ARCH_6 1 129 #else 130 #define ARM_ARCH_6 0 131 #endif 132 133 #if defined(CPU_CORTEX) 134 #define ARM_ARCH_7 1 135 #else 136 #define ARM_ARCH_7 0 137 #endif 138 139 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \ 140 ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) 141 #if ARM_NARCH == 0 142 #error ARM_NARCH is 0 143 #endif 144 145 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7 146 /* 147 * We could support Thumb code on v4T, but the lack of clean interworking 148 * makes that hard. 149 */ 150 #define THUMB_CODE 151 #endif 152 153 /* 154 * Step 3: Define which MMU classes are configured: 155 * 156 * ARM_MMU_MEMC Prehistoric, external memory controller 157 * and MMU for ARMv2 CPUs. 158 * 159 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 160 * 161 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 162 * ARM MMU, but has no write-through cache mode. 163 * 164 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 165 * MMU, but also has several extensions which 166 * require different PTE layout to use. 167 * 168 * ARM_MMU_V6 ARM v6 MMU. Compatible with generic ARM 169 * MMU, but also has several extensions which 170 * require different PTE layouts to use. 171 */ 172 #if !defined(_KERNEL_OPT) || \ 173 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 174 #define ARM_MMU_MEMC 1 175 #else 176 #define ARM_MMU_MEMC 0 177 #endif 178 179 #if !defined(_KERNEL_OPT) || \ 180 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 181 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 182 defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA) 183 #define ARM_MMU_GENERIC 1 184 #else 185 #define ARM_MMU_GENERIC 0 186 #endif 187 188 #if !defined(_KERNEL_OPT) || \ 189 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 190 defined(CPU_IXP12X0)) 191 #define ARM_MMU_SA1 1 192 #else 193 #define ARM_MMU_SA1 0 194 #endif 195 196 #if !defined(_KERNEL_OPT) || \ 197 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 198 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) 199 #define ARM_MMU_XSCALE 1 200 #else 201 #define ARM_MMU_XSCALE 0 202 #endif 203 204 #if !defined(_KERNEL_OPT) || \ 205 defined(CPU_ARM11) 206 #define ARM_MMU_V6 1 207 #else 208 #define ARM_MMU_V6 0 209 #endif 210 211 #if !defined(_KERNEL_OPT) || \ 212 defined(CPU_CORTEX) 213 #define ARM_MMU_V7 1 214 #else 215 #define ARM_MMU_V7 0 216 #endif 217 218 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 219 ARM_MMU_SA1 + ARM_MMU_XSCALE + \ 220 ARM_MMU_V6 + ARM_MMU_V7) 221 #if ARM_NMMUS == 0 222 #error ARM_NMMUS is 0 223 #endif 224 225 /* 226 * Step 4: Define features that may be present on a subset of CPUs 227 * 228 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 229 */ 230 231 #if !defined(_KERNEL_OPT) || \ 232 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 233 #define ARM_XSCALE_PMU 1 234 #else 235 #define ARM_XSCALE_PMU 0 236 #endif 237 238 #endif /* _ARM_CPUCONF_H_ */ 239