xref: /netbsd-src/sys/arch/arm/include/cpu.h (revision 8ac07aec990b9d2e483062509d0a9fa5b4f57cf2)
1 /*	$NetBSD: cpu.h,v 1.53 2008/03/15 10:16:43 rearnsha Exp $	*/
2 
3 /*
4  * Copyright (c) 1994-1996 Mark Brinicombe.
5  * Copyright (c) 1994 Brini.
6  * All rights reserved.
7  *
8  * This code is derived from software written for Brini by Mark Brinicombe
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by Brini.
21  * 4. The name of the company nor the name of the author may be used to
22  *    endorse or promote products derived from this software without specific
23  *    prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35  * SUCH DAMAGE.
36  *
37  * RiscBSD kernel project
38  *
39  * cpu.h
40  *
41  * CPU specific symbols
42  *
43  * Created      : 18/09/94
44  *
45  * Based on kate/katelib/arm6.h
46  */
47 
48 #ifndef _ARM_CPU_H_
49 #define _ARM_CPU_H_
50 
51 /*
52  * User-visible definitions
53  */
54 
55 /*  CTL_MACHDEP definitions. */
56 #define	CPU_DEBUG		1	/* int: misc kernel debug control */
57 #define	CPU_BOOTED_DEVICE	2	/* string: device we booted from */
58 #define	CPU_BOOTED_KERNEL	3	/* string: kernel we booted */
59 #define	CPU_CONSDEV		4	/* struct: dev_t of our console */
60 #define	CPU_POWERSAVE		5	/* int: use CPU powersave mode */
61 #define	CPU_MAXID		6	/* number of valid machdep ids */
62 
63 #ifdef _KERNEL
64 
65 /*
66  * Kernel-only definitions
67  */
68 
69 #ifndef _LKM
70 #include "opt_multiprocessor.h"
71 #include "opt_lockdebug.h"
72 #include "opt_cputypes.h"
73 #endif /* !_LKM */
74 
75 #include <arm/cpuconf.h>
76 
77 #include <machine/intr.h>
78 #ifndef _LOCORE
79 #include <sys/user.h>
80 #include <machine/frame.h>
81 #include <machine/pcb.h>
82 #ifdef FPU_VFP
83 #include <arm/vfpvar.h>
84 #endif
85 #endif	/* !_LOCORE */
86 
87 #include <arm/armreg.h>
88 
89 
90 #ifndef _LOCORE
91 /* 1 == use cpu_sleep(), 0 == don't */
92 extern int cpu_do_powersave;
93 #endif
94 
95 #ifdef __PROG32
96 #ifdef _LOCORE
97 #define IRQdisable \
98 	stmfd	sp!, {r0} ; \
99 	mrs	r0, cpsr ; \
100 	orr	r0, r0, #(I32_bit) ; \
101 	msr	cpsr_c, r0 ; \
102 	ldmfd	sp!, {r0}
103 
104 #define IRQenable \
105 	stmfd	sp!, {r0} ; \
106 	mrs	r0, cpsr ; \
107 	bic	r0, r0, #(I32_bit) ; \
108 	msr	cpsr_c, r0 ; \
109 	ldmfd	sp!, {r0}
110 
111 #else
112 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
113 #define IRQenable __set_cpsr_c(I32_bit, 0);
114 #endif	/* _LOCORE */
115 #else
116 #define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE);
117 #define IRQenable set_r15(R15_IRQ_DISABLE, 0);
118 #endif
119 
120 #ifndef _LOCORE
121 
122 /* All the CLKF_* macros take a struct clockframe * as an argument. */
123 
124 /*
125  * CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the
126  * frame came from USR mode or not.
127  */
128 #ifdef __PROG32
129 #define CLKF_USERMODE(frame)	((frame->cf_if.if_spsr & PSR_MODE) == PSR_USR32_MODE)
130 #else
131 #define CLKF_USERMODE(frame)	((frame->cf_if.if_r15 & R15_MODE) == R15_MODE_USR)
132 #endif
133 
134 /*
135  * CLKF_INTR: True if we took the interrupt from inside another
136  * interrupt handler.
137  */
138 #ifdef __PROG32
139 /* Hack to treat FPE time as interrupt time so we can measure it */
140 #define CLKF_INTR(frame)						\
141 	((curcpu()->ci_idepth > 1) ||					\
142 	    (frame->cf_if.if_spsr & PSR_MODE) == PSR_UND32_MODE)
143 #else
144 #define CLKF_INTR(frame)	(curcpu()->ci_idepth > 1)
145 #endif
146 
147 /*
148  * CLKF_PC: Extract the program counter from a clockframe
149  */
150 #ifdef __PROG32
151 #define CLKF_PC(frame)		(frame->cf_if.if_pc)
152 #else
153 #define CLKF_PC(frame)		(frame->cf_if.if_r15 & R15_PC)
154 #endif
155 
156 /*
157  * LWP_PC: Find out the program counter for the given lwp.
158  */
159 #ifdef __PROG32
160 #define LWP_PC(l)	((l)->l_addr->u_pcb.pcb_tf->tf_pc)
161 #else
162 #define LWP_PC(l)	((l)->l_addr->u_pcb.pcb_tf->tf_r15 & R15_PC)
163 #endif
164 
165 /*
166  * Validate a PC or PSR for a user process.  Used by various system calls
167  * that take a context passed by the user and restore it.
168  */
169 
170 #ifdef __PROG32
171 #define VALID_R15_PSR(r15,psr)						\
172 	(((psr) & PSR_MODE) == PSR_USR32_MODE &&			\
173 		((psr) & (I32_bit | F32_bit)) == 0)
174 #else
175 #define VALID_R15_PSR(r15,psr)						\
176 	(((r15) & R15_MODE) == R15_MODE_USR &&				\
177 		((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
178 #endif
179 
180 
181 
182 /* The address of the vector page. */
183 extern vaddr_t vector_page;
184 #ifdef __PROG32
185 void	arm32_vector_init(vaddr_t, int);
186 
187 #define	ARM_VEC_RESET			(1 << 0)
188 #define	ARM_VEC_UNDEFINED		(1 << 1)
189 #define	ARM_VEC_SWI			(1 << 2)
190 #define	ARM_VEC_PREFETCH_ABORT		(1 << 3)
191 #define	ARM_VEC_DATA_ABORT		(1 << 4)
192 #define	ARM_VEC_ADDRESS_EXCEPTION	(1 << 5)
193 #define	ARM_VEC_IRQ			(1 << 6)
194 #define	ARM_VEC_FIQ			(1 << 7)
195 
196 #define	ARM_NVEC			8
197 #define	ARM_VEC_ALL			0xffffffff
198 #endif
199 
200 /*
201  * Per-CPU information.  For now we assume one CPU.
202  */
203 
204 #include <sys/device.h>
205 #include <sys/cpu_data.h>
206 struct cpu_info {
207 	struct cpu_data ci_data;	/* MI per-cpu data */
208 	struct device *ci_dev;		/* Device corresponding to this CPU */
209 	cpuid_t ci_cpuid;
210 	u_int32_t ci_arm_cpuid;		/* aggregate CPU id */
211 	u_int32_t ci_arm_cputype;	/* CPU type */
212 	u_int32_t ci_arm_cpurev;	/* CPU revision */
213 	u_int32_t ci_ctrl;		/* The CPU control register */
214 	struct evcnt ci_arm700bugcount;
215 	int32_t ci_mtx_count;
216 	int ci_mtx_oldspl;
217 	int ci_want_resched;
218 	int ci_idepth;
219 #ifdef MULTIPROCESSOR
220 	MP_CPU_INFO_MEMBERS
221 #endif
222 #ifdef FPU_VFP
223 	struct vfp_info ci_vfp;
224 #endif
225 };
226 
227 #ifndef MULTIPROCESSOR
228 extern struct cpu_info cpu_info_store;
229 #define	curcpu()	(&cpu_info_store)
230 #define cpu_number()	0
231 #endif
232 
233 #ifdef __PROG32
234 void	cpu_proc_fork(struct proc *, struct proc *);
235 #else
236 #define	cpu_proc_fork(p1, p2)
237 #endif
238 
239 /*
240  * Scheduling glue
241  */
242 
243 extern int astpending;
244 #define setsoftast() (astpending = 1)
245 
246 /*
247  * Notify the current process (p) that it has a signal pending,
248  * process as soon as possible.
249  */
250 
251 #define cpu_signotify(l)            setsoftast()
252 
253 /*
254  * Give a profiling tick to the current process when the user profiling
255  * buffer pages are invalid.  On the i386, request an ast to send us
256  * through trap(), marking the proc as needing a profiling tick.
257  */
258 #define	cpu_need_proftick(l)	((l)->l_pflag |= LP_OWEUPC, setsoftast())
259 
260 #ifndef acorn26
261 /*
262  * cpu device glue (belongs in cpuvar.h)
263  */
264 
265 struct device;
266 void	cpu_attach(struct device *);
267 #endif
268 
269 /*
270  * Random cruft
271  */
272 
273 struct lwp;
274 
275 /* locore.S */
276 void atomic_set_bit(u_int *, u_int);
277 void atomic_clear_bit(u_int *, u_int);
278 
279 /* cpuswitch.S */
280 struct pcb;
281 void	savectx(struct pcb *);
282 
283 /* ast.c */
284 void userret(register struct lwp *);
285 
286 /* machdep.h */
287 void bootsync(void);
288 
289 /* fault.c */
290 int badaddr_read(void *, size_t, void *);
291 
292 /* syscall.c */
293 void swi_handler(trapframe_t *);
294 
295 #endif	/* !_LOCORE */
296 
297 #endif /* _KERNEL */
298 
299 #endif /* !_ARM_CPU_H_ */
300 
301 /* End of cpu.h */
302