1 /* $NetBSD: pte.h,v 1.7 2003/05/21 18:04:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_PTE_H_ 39 #define _ARM_PTE_H_ 40 41 /* 42 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 43 * architecture versions used an optional off-CPU memory controller 44 * to perform address translation). 45 * 46 * The ARM MMU consists of a TLB and translation table walking logic. 47 * There is typically one TLB per memory interface (or, put another 48 * way, one TLB per software-visible cache). 49 * 50 * The ARM MMU is capable of mapping memory in the following chunks: 51 * 52 * 1M Sections (L1 table) 53 * 54 * 64K Large Pages (L2 table) 55 * 56 * 4K Small Pages (L2 table) 57 * 58 * 1K Tiny Pages (L2 table) 59 * 60 * There are two types of L2 tables: Coarse Tables and Fine Tables. 61 * Coarse Tables can map Large and Small Pages. Fine Tables can 62 * map Tiny Pages. 63 * 64 * Coarse Tables can define 4 Subpages within Large and Small pages. 65 * Subpages define different permissions for each Subpage within 66 * a Page. 67 * 68 * Coarse Tables are 1K in length. Fine tables are 4K in length. 69 * 70 * The Translation Table Base register holds the pointer to the 71 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 72 * aligned to a 16K boundary. Each entry in the L1 Table maps 73 * 1M of virtual address space, either via a Section mapping or 74 * via an L2 Table. 75 * 76 * In addition, the Fast Context Switching Extension (FCSE) is available 77 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 78 * TLB/cache flushes on context switch by use of a smaller address space 79 * and a "process ID" that modifies the virtual address before being 80 * presented to the translation logic. 81 */ 82 83 #ifndef _LOCORE 84 typedef uint32_t pd_entry_t; /* L1 table entry */ 85 typedef uint32_t pt_entry_t; /* L2 table entry */ 86 #endif /* _LOCORE */ 87 88 #define L1_S_SIZE 0x00100000 /* 1M */ 89 #define L1_S_OFFSET (L1_S_SIZE - 1) 90 #define L1_S_FRAME (~L1_S_OFFSET) 91 #define L1_S_SHIFT 20 92 93 #define L2_L_SIZE 0x00010000 /* 64K */ 94 #define L2_L_OFFSET (L2_L_SIZE - 1) 95 #define L2_L_FRAME (~L2_L_OFFSET) 96 #define L2_L_SHIFT 16 97 98 #define L2_S_SIZE 0x00001000 /* 4K */ 99 #define L2_S_OFFSET (L2_S_SIZE - 1) 100 #define L2_S_FRAME (~L2_S_OFFSET) 101 #define L2_S_SHIFT 12 102 103 #define L2_T_SIZE 0x00000400 /* 1K */ 104 #define L2_T_OFFSET (L2_T_SIZE - 1) 105 #define L2_T_FRAME (~L2_T_OFFSET) 106 #define L2_T_SHIFT 10 107 108 /* 109 * The NetBSD VM implementation only works on whole pages (4K), 110 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 111 * (16K L1 table, 1K L2 table). 112 * 113 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 114 * table. 115 */ 116 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 117 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 118 119 #define L1_TABLE_SIZE 0x4000 /* 16K */ 120 #define L2_TABLE_SIZE 0x1000 /* 4K */ 121 /* 122 * The new pmap deals with the 1KB coarse L2 tables by 123 * allocating them from a pool. Until every port has been converted, 124 * keep the old L2_TABLE_SIZE define lying around. Converted ports 125 * should use L2_TABLE_SIZE_REAL until then. 126 */ 127 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 128 129 /* 130 * ARM L1 Descriptors 131 */ 132 133 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 134 #define L1_TYPE_C 0x01 /* Coarse L2 */ 135 #define L1_TYPE_S 0x02 /* Section */ 136 #define L1_TYPE_F 0x03 /* Fine L2 */ 137 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 138 139 /* L1 Section Descriptor */ 140 #define L1_S_B 0x00000004 /* bufferable Section */ 141 #define L1_S_C 0x00000008 /* cacheable Section */ 142 #define L1_S_IMP 0x00000010 /* implementation defined */ 143 #define L1_S_DOM(x) ((x) << 5) /* domain */ 144 #define L1_S_DOM_MASK L1_S_DOM(0xf) 145 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 146 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 147 148 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 149 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 150 151 /* L1 Coarse Descriptor */ 152 #define L1_C_IMP0 0x00000004 /* implementation defined */ 153 #define L1_C_IMP1 0x00000008 /* implementation defined */ 154 #define L1_C_IMP2 0x00000010 /* implementation defined */ 155 #define L1_C_DOM(x) ((x) << 5) /* domain */ 156 #define L1_C_DOM_MASK L1_C_DOM(0xf) 157 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 158 159 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 160 161 /* L1 Fine Descriptor */ 162 #define L1_F_IMP0 0x00000004 /* implementation defined */ 163 #define L1_F_IMP1 0x00000008 /* implementation defined */ 164 #define L1_F_IMP2 0x00000010 /* implementation defined */ 165 #define L1_F_DOM(x) ((x) << 5) /* domain */ 166 #define L1_F_DOM_MASK L1_F_DOM(0xf) 167 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 168 169 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 170 171 /* 172 * ARM L2 Descriptors 173 */ 174 175 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 176 #define L2_TYPE_L 0x01 /* Large Page */ 177 #define L2_TYPE_S 0x02 /* Small Page */ 178 #define L2_TYPE_T 0x03 /* Tiny Page */ 179 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 180 181 /* 182 * This L2 Descriptor type is available on XScale processors 183 * when using a Coarse L1 Descriptor. The Extended Small 184 * Descriptor has the same format as the XScale Tiny Descriptor, 185 * but describes a 4K page, rather than a 1K page. 186 */ 187 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 188 189 #define L2_B 0x00000004 /* Bufferable page */ 190 #define L2_C 0x00000008 /* Cacheable page */ 191 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 192 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 193 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 194 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 195 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 196 197 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 198 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 199 200 /* 201 * Access Permissions for L1 and L2 Descriptors. 202 */ 203 #define AP_W 0x01 /* writable */ 204 #define AP_U 0x02 /* user */ 205 206 /* 207 * Short-hand for common AP_* constants. 208 * 209 * Note: These values assume the S (System) bit is set and 210 * the R (ROM) bit is clear in CP15 register 1. 211 */ 212 #define AP_KR 0x00 /* kernel read */ 213 #define AP_KRW 0x01 /* kernel read/write */ 214 #define AP_KRWUR 0x02 /* kernel read/write usr read */ 215 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 216 217 /* 218 * Domain Types for the Domain Access Control Register. 219 */ 220 #define DOMAIN_FAULT 0x00 /* no access */ 221 #define DOMAIN_CLIENT 0x01 /* client */ 222 #define DOMAIN_RESERVED 0x02 /* reserved */ 223 #define DOMAIN_MANAGER 0x03 /* manager */ 224 225 /* 226 * Type Extension bits for XScale processors. 227 * 228 * Behavior of C and B when X == 0: 229 * 230 * C B Cacheable Bufferable Write Policy Line Allocate Policy 231 * 0 0 N N - - 232 * 0 1 N Y - - 233 * 1 0 Y Y Write-through Read Allocate 234 * 1 1 Y Y Write-back Read Allocate 235 * 236 * Behavior of C and B when X == 1: 237 * C B Cacheable Bufferable Write Policy Line Allocate Policy 238 * 0 0 - - - - DO NOT USE 239 * 0 1 N Y - - 240 * 1 0 Mini-Data - - - 241 * 1 1 Y Y Write-back R/W Allocate 242 */ 243 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 244 245 #endif /* _ARM_PTE_H_ */ 246