xref: /netbsd-src/sys/arch/arm/include/arm32/pmap.h (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55)
1 /*	$NetBSD: pmap.h,v 1.133 2014/06/15 03:27:46 ozaki-r Exp $	*/
2 
3 /*
4  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Copyright (c) 1994,1995 Mark Brinicombe.
40  * All rights reserved.
41  *
42  * Redistribution and use in source and binary forms, with or without
43  * modification, are permitted provided that the following conditions
44  * are met:
45  * 1. Redistributions of source code must retain the above copyright
46  *    notice, this list of conditions and the following disclaimer.
47  * 2. Redistributions in binary form must reproduce the above copyright
48  *    notice, this list of conditions and the following disclaimer in the
49  *    documentation and/or other materials provided with the distribution.
50  * 3. All advertising materials mentioning features or use of this software
51  *    must display the following acknowledgement:
52  *	This product includes software developed by Mark Brinicombe
53  * 4. The name of the author may not be used to endorse or promote products
54  *    derived from this software without specific prior written permission.
55  *
56  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
57  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
58  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
60  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
61  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
62  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
63  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
64  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
65  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66  */
67 
68 #ifndef	_ARM32_PMAP_H_
69 #define	_ARM32_PMAP_H_
70 
71 #ifdef _KERNEL
72 
73 #include <arm/cpuconf.h>
74 #include <arm/arm32/pte.h>
75 #ifndef _LOCORE
76 #if defined(_KERNEL_OPT)
77 #include "opt_arm32_pmap.h"
78 #endif
79 #include <arm/cpufunc.h>
80 #include <uvm/uvm_object.h>
81 #endif
82 
83 #ifdef ARM_MMU_EXTENDED
84 #define PMAP_TLB_MAX			1
85 #define PMAP_TLB_HWPAGEWALKER		1
86 #if PMAP_TLB_MAX > 1
87 #define PMAP_NEED_TLB_SHOOTDOWN		1
88 #endif
89 #define PMAP_TLB_FLUSH_ASID_ON_RESET	(arm_has_tlbiasid_p)
90 #define PMAP_TLB_NUM_PIDS		256
91 #define cpu_set_tlb_info(ci, ti)        ((void)((ci)->ci_tlb_info = (ti)))
92 #if PMAP_TLB_MAX > 1
93 #define cpu_tlb_info(ci)		((ci)->ci_tlb_info)
94 #else
95 #define cpu_tlb_info(ci)		(&pmap_tlb0_info)
96 #endif
97 #define pmap_md_tlb_asid_max()		(PMAP_TLB_NUM_PIDS - 1)
98 #include <uvm/pmap/tlb.h>
99 #include <uvm/pmap/pmap_tlb.h>
100 
101 /*
102  * If we have an EXTENDED MMU and the address space is split evenly between
103  * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for
104  * user and kernel address spaces.
105  */
106 #if (KERNEL_BASE & 0x80000000) == 0
107 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000
108 #endif
109 #endif  /* ARM_MMU_EXTENDED */
110 
111 /*
112  * a pmap describes a processes' 4GB virtual address space.  this
113  * virtual address space can be broken up into 4096 1MB regions which
114  * are described by L1 PTEs in the L1 table.
115  *
116  * There is a line drawn at KERNEL_BASE.  Everything below that line
117  * changes when the VM context is switched.  Everything above that line
118  * is the same no matter which VM context is running.  This is achieved
119  * by making the L1 PTEs for those slots above KERNEL_BASE reference
120  * kernel L2 tables.
121  *
122  * The basic layout of the virtual address space thus looks like this:
123  *
124  *	0xffffffff
125  *	.
126  *	.
127  *	.
128  *	KERNEL_BASE
129  *	--------------------
130  *	.
131  *	.
132  *	.
133  *	0x00000000
134  */
135 
136 /*
137  * The number of L2 descriptor tables which can be tracked by an l2_dtable.
138  * A bucket size of 16 provides for 16MB of contiguous virtual address
139  * space per l2_dtable. Most processes will, therefore, require only two or
140  * three of these to map their whole working set.
141  */
142 #define	L2_BUCKET_XLOG2	(L1_S_SHIFT)
143 #define L2_BUCKET_XSIZE	(1 << L2_BUCKET_XLOG2)
144 #define	L2_BUCKET_LOG2	4
145 #define	L2_BUCKET_SIZE	(1 << L2_BUCKET_LOG2)
146 
147 /*
148  * Given the above "L2-descriptors-per-l2_dtable" constant, the number
149  * of l2_dtable structures required to track all possible page descriptors
150  * mappable by an L1 translation table is given by the following constants:
151  */
152 #define	L2_LOG2		(32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2))
153 #define	L2_SIZE		(1 << L2_LOG2)
154 
155 /*
156  * tell MI code that the cache is virtually-indexed.
157  * ARMv6 is physically-tagged but all others are virtually-tagged.
158  */
159 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
160 #define PMAP_CACHE_VIPT
161 #else
162 #define PMAP_CACHE_VIVT
163 #endif
164 
165 #ifndef _LOCORE
166 
167 #ifndef PMAP_MMU_EXTENDED
168 struct l1_ttable;
169 struct l2_dtable;
170 
171 /*
172  * Track cache/tlb occupancy using the following structure
173  */
174 union pmap_cache_state {
175 	struct {
176 		union {
177 			uint8_t csu_cache_b[2];
178 			uint16_t csu_cache;
179 		} cs_cache_u;
180 
181 		union {
182 			uint8_t csu_tlb_b[2];
183 			uint16_t csu_tlb;
184 		} cs_tlb_u;
185 	} cs_s;
186 	uint32_t cs_all;
187 };
188 #define	cs_cache_id	cs_s.cs_cache_u.csu_cache_b[0]
189 #define	cs_cache_d	cs_s.cs_cache_u.csu_cache_b[1]
190 #define	cs_cache	cs_s.cs_cache_u.csu_cache
191 #define	cs_tlb_id	cs_s.cs_tlb_u.csu_tlb_b[0]
192 #define	cs_tlb_d	cs_s.cs_tlb_u.csu_tlb_b[1]
193 #define	cs_tlb		cs_s.cs_tlb_u.csu_tlb
194 
195 /*
196  * Assigned to cs_all to force cacheops to work for a particular pmap
197  */
198 #define	PMAP_CACHE_STATE_ALL	0xffffffffu
199 #endif /* !ARM_MMU_EXTENDED */
200 
201 /*
202  * This structure is used by machine-dependent code to describe
203  * static mappings of devices, created at bootstrap time.
204  */
205 struct pmap_devmap {
206 	vaddr_t		pd_va;		/* virtual address */
207 	paddr_t		pd_pa;		/* physical address */
208 	psize_t		pd_size;	/* size of region */
209 	vm_prot_t	pd_prot;	/* protection code */
210 	int		pd_cache;	/* cache attributes */
211 };
212 
213 /*
214  * The pmap structure itself
215  */
216 struct pmap {
217 	struct uvm_object	pm_obj;
218 	kmutex_t		pm_obj_lock;
219 #define	pm_lock pm_obj.vmobjlock
220 #ifndef ARM_HAS_VBAR
221 	pd_entry_t		*pm_pl1vec;
222 	pd_entry_t		pm_l1vec;
223 #endif
224 	struct l2_dtable	*pm_l2[L2_SIZE];
225 	struct pmap_statistics	pm_stats;
226 	LIST_ENTRY(pmap)	pm_list;
227 #ifdef ARM_MMU_EXTENDED
228 	pd_entry_t		*pm_l1;
229 	paddr_t			pm_l1_pa;
230 	bool			pm_remove_all;
231 #ifdef MULTIPROCESSOR
232 	kcpuset_t		*pm_onproc;
233 	kcpuset_t		*pm_active;
234 #if PMAP_TLB_MAX > 1
235 	u_int			pm_shootdown_pending;
236 #endif
237 #endif
238 	struct pmap_asid_info	pm_pai[PMAP_TLB_MAX];
239 #else
240 	struct l1_ttable	*pm_l1;
241 	union pmap_cache_state	pm_cstate;
242 	uint8_t			pm_domain;
243 	bool			pm_activated;
244 	bool			pm_remove_all;
245 #endif
246 };
247 
248 struct pmap_kernel {
249 	struct pmap		kernel_pmap;
250 };
251 
252 /*
253  * Physical / virtual address structure. In a number of places (particularly
254  * during bootstrapping) we need to keep track of the physical and virtual
255  * addresses of various pages
256  */
257 typedef struct pv_addr {
258 	SLIST_ENTRY(pv_addr) pv_list;
259 	paddr_t pv_pa;
260 	vaddr_t pv_va;
261 	vsize_t pv_size;
262 	uint8_t pv_cache;
263 	uint8_t pv_prot;
264 } pv_addr_t;
265 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t;
266 
267 extern pv_addrqh_t pmap_freeq;
268 extern pv_addr_t kernelstack;
269 extern pv_addr_t abtstack;
270 extern pv_addr_t fiqstack;
271 extern pv_addr_t irqstack;
272 extern pv_addr_t undstack;
273 extern pv_addr_t idlestack;
274 extern pv_addr_t systempage;
275 extern pv_addr_t kernel_l1pt;
276 
277 #ifdef ARM_MMU_EXTENDED
278 extern bool arm_has_tlbiasid_p;	/* also in <arm/locore.h> */
279 #endif
280 
281 /*
282  * Determine various modes for PTEs (user vs. kernel, cacheable
283  * vs. non-cacheable).
284  */
285 #define	PTE_KERNEL	0
286 #define	PTE_USER	1
287 #define	PTE_NOCACHE	0
288 #define	PTE_CACHE	1
289 #define	PTE_PAGETABLE	2
290 
291 /*
292  * Flags that indicate attributes of pages or mappings of pages.
293  *
294  * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
295  * page.  PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
296  * pv_entry's for each page.  They live in the same "namespace" so
297  * that we can clear multiple attributes at a time.
298  *
299  * Note the "non-cacheable" flag generally means the page has
300  * multiple mappings in a given address space.
301  */
302 #define	PVF_MOD		0x01		/* page is modified */
303 #define	PVF_REF		0x02		/* page is referenced */
304 #define	PVF_WIRED	0x04		/* mapping is wired */
305 #define	PVF_WRITE	0x08		/* mapping is writable */
306 #define	PVF_EXEC	0x10		/* mapping is executable */
307 #ifdef PMAP_CACHE_VIVT
308 #define	PVF_UNC		0x20		/* mapping is 'user' non-cacheable */
309 #define	PVF_KNC		0x40		/* mapping is 'kernel' non-cacheable */
310 #define	PVF_NC		(PVF_UNC|PVF_KNC)
311 #endif
312 #ifdef PMAP_CACHE_VIPT
313 #define	PVF_NC		0x20		/* mapping is 'kernel' non-cacheable */
314 #define	PVF_MULTCLR	0x40		/* mapping is multi-colored */
315 #endif
316 #define	PVF_COLORED	0x80		/* page has or had a color */
317 #define	PVF_KENTRY	0x0100		/* page entered via pmap_kenter_pa */
318 #define	PVF_KMPAGE	0x0200		/* page is used for kmem */
319 #define	PVF_DIRTY	0x0400		/* page may have dirty cache lines */
320 #define	PVF_KMOD	0x0800		/* unmanaged page is modified  */
321 #define	PVF_KWRITE	(PVF_KENTRY|PVF_WRITE)
322 #define	PVF_DMOD	(PVF_MOD|PVF_KMOD|PVF_KMPAGE)
323 
324 /*
325  * Commonly referenced structures
326  */
327 extern int		pmap_debug_level; /* Only exists if PMAP_DEBUG */
328 extern int		arm_poolpage_vmfreelist;
329 
330 /*
331  * Macros that we need to export
332  */
333 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
334 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
335 
336 #define	pmap_is_modified(pg)	\
337 	(((pg)->mdpage.pvh_attrs & PVF_MOD) != 0)
338 #define	pmap_is_referenced(pg)	\
339 	(((pg)->mdpage.pvh_attrs & PVF_REF) != 0)
340 #define	pmap_is_page_colored_p(md)	\
341 	(((md)->pvh_attrs & PVF_COLORED) != 0)
342 
343 #define	pmap_copy(dp, sp, da, l, sa)	/* nothing */
344 
345 #define pmap_phys_address(ppn)		(arm_ptob((ppn)))
346 u_int arm32_mmap_flags(paddr_t);
347 #define ARM32_MMAP_WRITECOMBINE	0x40000000
348 #define ARM32_MMAP_CACHEABLE		0x20000000
349 #define pmap_mmap_flags(ppn)			arm32_mmap_flags(ppn)
350 
351 #define	PMAP_PTE			0x10000000 /* kenter_pa */
352 
353 /*
354  * Functions that we need to export
355  */
356 void	pmap_procwr(struct proc *, vaddr_t, int);
357 void	pmap_remove_all(pmap_t);
358 bool	pmap_extract(pmap_t, vaddr_t, paddr_t *);
359 
360 #define	PMAP_NEED_PROCWR
361 #define PMAP_GROWKERNEL		/* turn on pmap_growkernel interface */
362 #define	PMAP_ENABLE_PMAP_KMPAGE	/* enable the PMAP_KMPAGE flag */
363 
364 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
365 #define	PMAP_PREFER(hint, vap, sz, td)	pmap_prefer((hint), (vap), (td))
366 void	pmap_prefer(vaddr_t, vaddr_t *, int);
367 #endif
368 
369 void	pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
370 
371 /* Functions we use internally. */
372 #ifdef PMAP_STEAL_MEMORY
373 void	pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *);
374 void	pmap_boot_pageadd(pv_addr_t *);
375 vaddr_t	pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *);
376 #endif
377 void	pmap_bootstrap(vaddr_t, vaddr_t);
378 
379 void	pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
380 int	pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
381 int	pmap_prefetchabt_fixup(void *);
382 bool	pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
383 bool	pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
384 struct pcb;
385 void	pmap_set_pcb_pagedir(pmap_t, struct pcb *);
386 
387 void	pmap_debug(int);
388 void	pmap_postinit(void);
389 
390 void	vector_page_setprot(int);
391 
392 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
393 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
394 
395 /* Bootstrapping routines. */
396 void	pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
397 void	pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
398 vsize_t	pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
399 void	pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
400 void	pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
401 void	pmap_devmap_register(const struct pmap_devmap *);
402 
403 /*
404  * Special page zero routine for use by the idle loop (no cache cleans).
405  */
406 bool	pmap_pageidlezero(paddr_t);
407 #define PMAP_PAGEIDLEZERO(pa)	pmap_pageidlezero((pa))
408 
409 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
410 /*
411  * For the pmap, this is a more useful way to map a direct mapped page.
412  * It returns either the direct-mapped VA or the VA supplied if it can't
413  * be direct mapped.
414  */
415 vaddr_t	pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t);
416 #endif
417 
418 /*
419  * used by dumpsys to record the PA of the L1 table
420  */
421 uint32_t pmap_kernel_L1_addr(void);
422 /*
423  * The current top of kernel VM
424  */
425 extern vaddr_t	pmap_curmaxkvaddr;
426 
427 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
428 /*
429  * Starting VA of direct mapped memory (usually KERNEL_BASE).
430  */
431 extern vaddr_t pmap_directbase;
432 #endif
433 
434 /*
435  * Useful macros and constants
436  */
437 
438 /* Virtual address to page table entry */
439 static inline pt_entry_t *
440 vtopte(vaddr_t va)
441 {
442 	pd_entry_t *pdep;
443 	pt_entry_t *ptep;
444 
445 	KASSERT(trunc_page(va) == va);
446 
447 	if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false)
448 		return (NULL);
449 	return (ptep);
450 }
451 
452 /*
453  * Virtual address to physical address
454  */
455 static inline paddr_t
456 vtophys(vaddr_t va)
457 {
458 	paddr_t pa;
459 
460 	if (pmap_extract(pmap_kernel(), va, &pa) == false)
461 		return (0);	/* XXXSCW: Panic? */
462 
463 	return (pa);
464 }
465 
466 /*
467  * The new pmap ensures that page-tables are always mapping Write-Thru.
468  * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
469  * on every change.
470  *
471  * Unfortunately, not all CPUs have a write-through cache mode.  So we
472  * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
473  * and if there is the chance for PTE syncs to be needed, we define
474  * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
475  * the code.
476  */
477 extern int pmap_needs_pte_sync;
478 #if defined(_KERNEL_OPT)
479 /*
480  * StrongARM SA-1 caches do not have a write-through mode.  So, on these,
481  * we need to do PTE syncs.  If only SA-1 is configured, then evaluate
482  * this at compile time.
483  */
484 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
485 #define	PMAP_INCLUDE_PTE_SYNC
486 #if (ARM_MMU_V6 > 0)
487 #define	PMAP_NEEDS_PTE_SYNC	1
488 #elif (ARM_MMU_SA1 == 0)
489 #define	PMAP_NEEDS_PTE_SYNC	0
490 #endif
491 #endif
492 #endif /* _KERNEL_OPT */
493 
494 /*
495  * Provide a fallback in case we were not able to determine it at
496  * compile-time.
497  */
498 #ifndef PMAP_NEEDS_PTE_SYNC
499 #define	PMAP_NEEDS_PTE_SYNC	pmap_needs_pte_sync
500 #define	PMAP_INCLUDE_PTE_SYNC
501 #endif
502 
503 static inline void
504 pmap_ptesync(pt_entry_t *ptep, size_t cnt)
505 {
506 	if (PMAP_NEEDS_PTE_SYNC) {
507 		cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
508 #ifdef SHEEVA_L2_CACHE
509 		cpu_sdcache_wb_range((vaddr_t)ptep, -1,
510 		    cnt * sizeof(pt_entry_t));
511 #endif
512 	}
513 #if ARM_MMU_V7 > 0
514 	__asm("dsb");
515 #endif
516 }
517 
518 #define	PDE_SYNC(pdep)			pmap_ptesync((pdep), 1)
519 #define	PDE_SYNC_RANGE(pdep, cnt)	pmap_ptesync((pdep), (cnt))
520 #define	PTE_SYNC(ptep)			pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE)
521 #define	PTE_SYNC_RANGE(ptep, cnt)	pmap_ptesync((ptep), (cnt))
522 
523 #define l1pte_valid_p(pde)	((pde) != 0)
524 #define l1pte_section_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_S)
525 #define l1pte_supersection_p(pde) (l1pte_section_p(pde)	\
526 				&& ((pde) & L1_S_V6_SUPER) != 0)
527 #define l1pte_page_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_C)
528 #define l1pte_fpage_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_F)
529 #define l1pte_pa(pde)		((pde) & L1_C_ADDR_MASK)
530 #define l1pte_index(v)		((vaddr_t)(v) >> L1_S_SHIFT)
531 #define l1pte_pgindex(v)	l1pte_index((v) & L1_ADDR_BITS \
532 		& ~(PAGE_SIZE * PAGE_SIZE / sizeof(pt_entry_t) - 1))
533 
534 static inline void
535 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde)
536 {
537 	*pdep = pde;
538 }
539 
540 static inline void
541 l1pte_set(pt_entry_t *pdep, pt_entry_t pde)
542 {
543 	*pdep = pde;
544 	if (l1pte_page_p(pde)) {
545 		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep);
546 		for (size_t k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) {
547 			pde += L2_T_SIZE;
548 			pdep[k] = pde;
549 		}
550 	} else if (l1pte_supersection_p(pde)) {
551 		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep);
552 		for (size_t k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) {
553 			pdep[k] = pde;
554 		}
555 	}
556 }
557 
558 #define l2pte_index(v)		((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT))
559 #define l2pte_valid_p(pte)	(((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
560 #define l2pte_pa(pte)		((pte) & L2_S_FRAME)
561 #define l1pte_lpage_p(pte)	(((pte) & L2_TYPE_MASK) == L2_TYPE_L)
562 #define l2pte_minidata_p(pte)	(((pte) & \
563 				 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
564 				 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
565 
566 static inline void
567 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
568 {
569 	if (l1pte_lpage_p(pte)) {
570 		for (size_t k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) {
571 			*ptep++ = pte;
572 		}
573 	} else {
574 		for (size_t k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) {
575 			KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte);
576 			*ptep++ = pte;
577 			pte += L2_S_SIZE;
578 			if (opte)
579 				opte += L2_S_SIZE;
580 		}
581 	}
582 }
583 
584 static inline void
585 l2pte_reset(pt_entry_t *ptep)
586 {
587 	*ptep = 0;
588 	for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
589 		ptep[k] = 0;
590 	}
591 }
592 
593 /* L1 and L2 page table macros */
594 #define pmap_pde_v(pde)		l1pte_valid(*(pde))
595 #define pmap_pde_section(pde)	l1pte_section_p(*(pde))
596 #define pmap_pde_supersection(pde)	l1pte_supersection_p(*(pde))
597 #define pmap_pde_page(pde)	l1pte_page_p(*(pde))
598 #define pmap_pde_fpage(pde)	l1pte_fpage_p(*(pde))
599 
600 #define	pmap_pte_v(pte)		l2pte_valid_p(*(pte))
601 #define	pmap_pte_pa(pte)	l2pte_pa(*(pte))
602 
603 /* Size of the kernel part of the L1 page table */
604 #define KERNEL_PD_SIZE	\
605 	(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
606 
607 void	bzero_page(vaddr_t);
608 void	bcopy_page(vaddr_t, vaddr_t);
609 
610 #ifdef FPU_VFP
611 void	bzero_page_vfp(vaddr_t);
612 void	bcopy_page_vfp(vaddr_t, vaddr_t);
613 #endif
614 
615 /************************* ARM MMU configuration *****************************/
616 
617 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0
618 void	pmap_copy_page_generic(paddr_t, paddr_t);
619 void	pmap_zero_page_generic(paddr_t);
620 
621 void	pmap_pte_init_generic(void);
622 #if defined(CPU_ARM8)
623 void	pmap_pte_init_arm8(void);
624 #endif
625 #if defined(CPU_ARM9)
626 void	pmap_pte_init_arm9(void);
627 #endif /* CPU_ARM9 */
628 #if defined(CPU_ARM10)
629 void	pmap_pte_init_arm10(void);
630 #endif /* CPU_ARM10 */
631 #if defined(CPU_ARM11)	/* ARM_MMU_V6 */
632 void	pmap_pte_init_arm11(void);
633 #endif /* CPU_ARM11 */
634 #if defined(CPU_ARM11MPCORE)	/* ARM_MMU_V6 */
635 void	pmap_pte_init_arm11mpcore(void);
636 #endif
637 #if ARM_MMU_V7 == 1
638 void	pmap_pte_init_armv7(void);
639 #endif /* ARM_MMU_V7 */
640 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
641 
642 #if ARM_MMU_SA1 == 1
643 void	pmap_pte_init_sa1(void);
644 #endif /* ARM_MMU_SA1 == 1 */
645 
646 #if ARM_MMU_XSCALE == 1
647 void	pmap_copy_page_xscale(paddr_t, paddr_t);
648 void	pmap_zero_page_xscale(paddr_t);
649 
650 void	pmap_pte_init_xscale(void);
651 
652 void	xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
653 
654 #define	PMAP_UAREA(va)		pmap_uarea(va)
655 void	pmap_uarea(vaddr_t);
656 #endif /* ARM_MMU_XSCALE == 1 */
657 
658 extern pt_entry_t		pte_l1_s_cache_mode;
659 extern pt_entry_t		pte_l1_s_cache_mask;
660 
661 extern pt_entry_t		pte_l2_l_cache_mode;
662 extern pt_entry_t		pte_l2_l_cache_mask;
663 
664 extern pt_entry_t		pte_l2_s_cache_mode;
665 extern pt_entry_t		pte_l2_s_cache_mask;
666 
667 extern pt_entry_t		pte_l1_s_cache_mode_pt;
668 extern pt_entry_t		pte_l2_l_cache_mode_pt;
669 extern pt_entry_t		pte_l2_s_cache_mode_pt;
670 
671 extern pt_entry_t		pte_l1_s_wc_mode;
672 extern pt_entry_t		pte_l2_l_wc_mode;
673 extern pt_entry_t		pte_l2_s_wc_mode;
674 
675 extern pt_entry_t		pte_l1_s_prot_u;
676 extern pt_entry_t		pte_l1_s_prot_w;
677 extern pt_entry_t		pte_l1_s_prot_ro;
678 extern pt_entry_t		pte_l1_s_prot_mask;
679 
680 extern pt_entry_t		pte_l2_s_prot_u;
681 extern pt_entry_t		pte_l2_s_prot_w;
682 extern pt_entry_t		pte_l2_s_prot_ro;
683 extern pt_entry_t		pte_l2_s_prot_mask;
684 
685 extern pt_entry_t		pte_l2_l_prot_u;
686 extern pt_entry_t		pte_l2_l_prot_w;
687 extern pt_entry_t		pte_l2_l_prot_ro;
688 extern pt_entry_t		pte_l2_l_prot_mask;
689 
690 extern pt_entry_t		pte_l1_ss_proto;
691 extern pt_entry_t		pte_l1_s_proto;
692 extern pt_entry_t		pte_l1_c_proto;
693 extern pt_entry_t		pte_l2_s_proto;
694 
695 extern void (*pmap_copy_page_func)(paddr_t, paddr_t);
696 extern void (*pmap_zero_page_func)(paddr_t);
697 
698 #endif /* !_LOCORE */
699 
700 /*****************************************************************************/
701 
702 #define	KERNEL_PID		0	/* The kernel uses ASID 0 */
703 
704 /*
705  * Definitions for MMU domains
706  */
707 #define	PMAP_DOMAINS		15	/* 15 'user' domains (1-15) */
708 #define	PMAP_DOMAIN_KERNEL	0	/* The kernel pmap uses domain #0 */
709 #ifdef ARM_MMU_EXTENDED
710 #define	PMAP_DOMAIN_USER	1	/* User pmaps use domain #1 */
711 #endif
712 
713 /*
714  * These macros define the various bit masks in the PTE.
715  *
716  * We use these macros since we use different bits on different processor
717  * models.
718  */
719 #define	L1_S_PROT_U_generic	(L1_S_AP(AP_U))
720 #define	L1_S_PROT_W_generic	(L1_S_AP(AP_W))
721 #define	L1_S_PROT_RO_generic	(0)
722 #define	L1_S_PROT_MASK_generic	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
723 
724 #define	L1_S_PROT_U_xscale	(L1_S_AP(AP_U))
725 #define	L1_S_PROT_W_xscale	(L1_S_AP(AP_W))
726 #define	L1_S_PROT_RO_xscale	(0)
727 #define	L1_S_PROT_MASK_xscale	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
728 
729 #define	L1_S_PROT_U_armv6	(L1_S_AP(AP_R) | L1_S_AP(AP_U))
730 #define	L1_S_PROT_W_armv6	(L1_S_AP(AP_W))
731 #define	L1_S_PROT_RO_armv6	(L1_S_AP(AP_R) | L1_S_AP(AP_RO))
732 #define	L1_S_PROT_MASK_armv6	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
733 
734 #define	L1_S_PROT_U_armv7	(L1_S_AP(AP_R) | L1_S_AP(AP_U))
735 #define	L1_S_PROT_W_armv7	(L1_S_AP(AP_W))
736 #define	L1_S_PROT_RO_armv7	(L1_S_AP(AP_R) | L1_S_AP(AP_RO))
737 #define	L1_S_PROT_MASK_armv7	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
738 
739 #define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
740 #define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))
741 #define	L1_S_CACHE_MASK_armv6	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))
742 #define	L1_S_CACHE_MASK_armv7	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
743 
744 #define	L2_L_PROT_U_generic	(L2_AP(AP_U))
745 #define	L2_L_PROT_W_generic	(L2_AP(AP_W))
746 #define	L2_L_PROT_RO_generic	(0)
747 #define	L2_L_PROT_MASK_generic	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
748 
749 #define	L2_L_PROT_U_xscale	(L2_AP(AP_U))
750 #define	L2_L_PROT_W_xscale	(L2_AP(AP_W))
751 #define	L2_L_PROT_RO_xscale	(0)
752 #define	L2_L_PROT_MASK_xscale	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
753 
754 #define	L2_L_PROT_U_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_U))
755 #define	L2_L_PROT_W_armv6n	(L2_AP0(AP_W))
756 #define	L2_L_PROT_RO_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_RO))
757 #define	L2_L_PROT_MASK_armv6n	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
758 
759 #define	L2_L_PROT_U_armv7	(L2_AP0(AP_R) | L2_AP0(AP_U))
760 #define	L2_L_PROT_W_armv7	(L2_AP0(AP_W))
761 #define	L2_L_PROT_RO_armv7	(L2_AP0(AP_R) | L2_AP0(AP_RO))
762 #define	L2_L_PROT_MASK_armv7	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
763 
764 #define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
765 #define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X))
766 #define	L2_L_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX))
767 #define	L2_L_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
768 
769 #define	L2_S_PROT_U_generic	(L2_AP(AP_U))
770 #define	L2_S_PROT_W_generic	(L2_AP(AP_W))
771 #define	L2_S_PROT_RO_generic	(0)
772 #define	L2_S_PROT_MASK_generic	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
773 
774 #define	L2_S_PROT_U_xscale	(L2_AP0(AP_U))
775 #define	L2_S_PROT_W_xscale	(L2_AP0(AP_W))
776 #define	L2_S_PROT_RO_xscale	(0)
777 #define	L2_S_PROT_MASK_xscale	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
778 
779 #define	L2_S_PROT_U_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_U))
780 #define	L2_S_PROT_W_armv6n	(L2_AP0(AP_W))
781 #define	L2_S_PROT_RO_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_RO))
782 #define	L2_S_PROT_MASK_armv6n	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
783 
784 #define	L2_S_PROT_U_armv7	(L2_AP0(AP_R) | L2_AP0(AP_U))
785 #define	L2_S_PROT_W_armv7	(L2_AP0(AP_W))
786 #define	L2_S_PROT_RO_armv7	(L2_AP0(AP_R) | L2_AP0(AP_RO))
787 #define	L2_S_PROT_MASK_armv7	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
788 
789 #define	L2_S_CACHE_MASK_generic	(L2_B|L2_C)
790 #define	L2_S_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X))
791 #define	L2_XS_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX))
792 #define	L2_S_CACHE_MASK_armv6n	L2_XS_CACHE_MASK_armv6
793 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
794 #define	L2_S_CACHE_MASK_armv6c	L2_XS_CACHE_MASK_armv6
795 #else
796 #define	L2_S_CACHE_MASK_armv6c	L2_S_CACHE_MASK_generic
797 #endif
798 #define	L2_S_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
799 
800 
801 #define	L1_S_PROTO_generic	(L1_TYPE_S | L1_S_IMP)
802 #define	L1_S_PROTO_xscale	(L1_TYPE_S)
803 #define	L1_S_PROTO_armv6	(L1_TYPE_S)
804 #define	L1_S_PROTO_armv7	(L1_TYPE_S)
805 
806 #define	L1_SS_PROTO_generic	0
807 #define	L1_SS_PROTO_xscale	0
808 #define	L1_SS_PROTO_armv6	(L1_TYPE_S | L1_S_V6_SS)
809 #define	L1_SS_PROTO_armv7	(L1_TYPE_S | L1_S_V6_SS)
810 
811 #define	L1_C_PROTO_generic	(L1_TYPE_C | L1_C_IMP2)
812 #define	L1_C_PROTO_xscale	(L1_TYPE_C)
813 #define	L1_C_PROTO_armv6	(L1_TYPE_C)
814 #define	L1_C_PROTO_armv7	(L1_TYPE_C)
815 
816 #define	L2_L_PROTO		(L2_TYPE_L)
817 
818 #define	L2_S_PROTO_generic	(L2_TYPE_S)
819 #define	L2_S_PROTO_xscale	(L2_TYPE_XS)
820 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
821 #define	L2_S_PROTO_armv6c	(L2_TYPE_XS)    /* XP=0, extended small page */
822 #else
823 #define	L2_S_PROTO_armv6c	(L2_TYPE_S)	/* XP=0, subpage APs */
824 #endif
825 #define	L2_S_PROTO_armv6n	(L2_TYPE_S)	/* with XP=1 */
826 #ifdef ARM_MMU_EXTENDED
827 #define	L2_S_PROTO_armv7	(L2_TYPE_S|L2_XS_XN)
828 #else
829 #define	L2_S_PROTO_armv7	(L2_TYPE_S)
830 #endif
831 
832 /*
833  * User-visible names for the ones that vary with MMU class.
834  */
835 
836 #if ARM_NMMUS > 1
837 /* More than one MMU class configured; use variables. */
838 #define	L1_S_PROT_U		pte_l1_s_prot_u
839 #define	L1_S_PROT_W		pte_l1_s_prot_w
840 #define	L1_S_PROT_RO		pte_l1_s_prot_ro
841 #define	L1_S_PROT_MASK		pte_l1_s_prot_mask
842 
843 #define	L2_S_PROT_U		pte_l2_s_prot_u
844 #define	L2_S_PROT_W		pte_l2_s_prot_w
845 #define	L2_S_PROT_RO		pte_l2_s_prot_ro
846 #define	L2_S_PROT_MASK		pte_l2_s_prot_mask
847 
848 #define	L2_L_PROT_U		pte_l2_l_prot_u
849 #define	L2_L_PROT_W		pte_l2_l_prot_w
850 #define	L2_L_PROT_RO		pte_l2_l_prot_ro
851 #define	L2_L_PROT_MASK		pte_l2_l_prot_mask
852 
853 #define	L1_S_CACHE_MASK		pte_l1_s_cache_mask
854 #define	L2_L_CACHE_MASK		pte_l2_l_cache_mask
855 #define	L2_S_CACHE_MASK		pte_l2_s_cache_mask
856 
857 #define	L1_SS_PROTO		pte_l1_ss_proto
858 #define	L1_S_PROTO		pte_l1_s_proto
859 #define	L1_C_PROTO		pte_l1_c_proto
860 #define	L2_S_PROTO		pte_l2_s_proto
861 
862 #define	pmap_copy_page(s, d)	(*pmap_copy_page_func)((s), (d))
863 #define	pmap_zero_page(d)	(*pmap_zero_page_func)((d))
864 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
865 #define	L1_S_PROT_U		L1_S_PROT_U_generic
866 #define	L1_S_PROT_W		L1_S_PROT_W_generic
867 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
868 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
869 
870 #define	L2_S_PROT_U		L2_S_PROT_U_generic
871 #define	L2_S_PROT_W		L2_S_PROT_W_generic
872 #define	L2_S_PROT_RO		L2_S_PROT_RO_generic
873 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
874 
875 #define	L2_L_PROT_U		L2_L_PROT_U_generic
876 #define	L2_L_PROT_W		L2_L_PROT_W_generic
877 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
878 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
879 
880 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
881 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
882 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
883 
884 #define	L1_SS_PROTO		L1_SS_PROTO_generic
885 #define	L1_S_PROTO		L1_S_PROTO_generic
886 #define	L1_C_PROTO		L1_C_PROTO_generic
887 #define	L2_S_PROTO		L2_S_PROTO_generic
888 
889 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
890 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
891 #elif ARM_MMU_V6N != 0
892 #define	L1_S_PROT_U		L1_S_PROT_U_armv6
893 #define	L1_S_PROT_W		L1_S_PROT_W_armv6
894 #define	L1_S_PROT_RO		L1_S_PROT_RO_armv6
895 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_armv6
896 
897 #define	L2_S_PROT_U		L2_S_PROT_U_armv6n
898 #define	L2_S_PROT_W		L2_S_PROT_W_armv6n
899 #define	L2_S_PROT_RO		L2_S_PROT_RO_armv6n
900 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_armv6n
901 
902 #define	L2_L_PROT_U		L2_L_PROT_U_armv6n
903 #define	L2_L_PROT_W		L2_L_PROT_W_armv6n
904 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv6n
905 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv6n
906 
907 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6
908 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6
909 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv6n
910 
911 /* These prototypes make writeable mappings, while the other MMU types
912  * make read-only mappings. */
913 #define	L1_SS_PROTO		L1_SS_PROTO_armv6
914 #define	L1_S_PROTO		L1_S_PROTO_armv6
915 #define	L1_C_PROTO		L1_C_PROTO_armv6
916 #define	L2_S_PROTO		L2_S_PROTO_armv6n
917 
918 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
919 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
920 #elif ARM_MMU_V6C != 0
921 #define	L1_S_PROT_U		L1_S_PROT_U_generic
922 #define	L1_S_PROT_W		L1_S_PROT_W_generic
923 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
924 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
925 
926 #define	L2_S_PROT_U		L2_S_PROT_U_generic
927 #define	L2_S_PROT_W		L2_S_PROT_W_generic
928 #define	L2_S_PROT_RO		L2_S_PROT_RO_generic
929 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
930 
931 #define	L2_L_PROT_U		L2_L_PROT_U_generic
932 #define	L2_L_PROT_W		L2_L_PROT_W_generic
933 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
934 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
935 
936 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
937 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
938 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
939 
940 #define	L1_SS_PROTO		L1_SS_PROTO_armv6
941 #define	L1_S_PROTO		L1_S_PROTO_generic
942 #define	L1_C_PROTO		L1_C_PROTO_generic
943 #define	L2_S_PROTO		L2_S_PROTO_generic
944 
945 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
946 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
947 #elif ARM_MMU_XSCALE == 1
948 #define	L1_S_PROT_U		L1_S_PROT_U_generic
949 #define	L1_S_PROT_W		L1_S_PROT_W_generic
950 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
951 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
952 
953 #define	L2_S_PROT_U		L2_S_PROT_U_xscale
954 #define	L2_S_PROT_W		L2_S_PROT_W_xscale
955 #define	L2_S_PROT_RO		L2_S_PROT_RO_xscale
956 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_xscale
957 
958 #define	L2_L_PROT_U		L2_L_PROT_U_generic
959 #define	L2_L_PROT_W		L2_L_PROT_W_generic
960 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
961 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
962 
963 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_xscale
964 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_xscale
965 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_xscale
966 
967 #define	L1_SS_PROTO		L1_SS_PROTO_xscale
968 #define	L1_S_PROTO		L1_S_PROTO_xscale
969 #define	L1_C_PROTO		L1_C_PROTO_xscale
970 #define	L2_S_PROTO		L2_S_PROTO_xscale
971 
972 #define	pmap_copy_page(s, d)	pmap_copy_page_xscale((s), (d))
973 #define	pmap_zero_page(d)	pmap_zero_page_xscale((d))
974 #elif ARM_MMU_V7 == 1
975 #define	L1_S_PROT_U		L1_S_PROT_U_armv7
976 #define	L1_S_PROT_W		L1_S_PROT_W_armv7
977 #define	L1_S_PROT_RO		L1_S_PROT_RO_armv7
978 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_armv7
979 
980 #define	L2_S_PROT_U		L2_S_PROT_U_armv7
981 #define	L2_S_PROT_W		L2_S_PROT_W_armv7
982 #define	L2_S_PROT_RO		L2_S_PROT_RO_armv7
983 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_armv7
984 
985 #define	L2_L_PROT_U		L2_L_PROT_U_armv7
986 #define	L2_L_PROT_W		L2_L_PROT_W_armv7
987 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv7
988 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv7
989 
990 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv7
991 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv7
992 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv7
993 
994 /* These prototypes make writeable mappings, while the other MMU types
995  * make read-only mappings. */
996 #define	L1_SS_PROTO		L1_SS_PROTO_armv7
997 #define	L1_S_PROTO		L1_S_PROTO_armv7
998 #define	L1_C_PROTO		L1_C_PROTO_armv7
999 #define	L2_S_PROTO		L2_S_PROTO_armv7
1000 
1001 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
1002 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
1003 #endif /* ARM_NMMUS > 1 */
1004 
1005 /*
1006  * Macros to set and query the write permission on page descriptors.
1007  */
1008 #define l1pte_set_writable(pte)	(((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W)
1009 #define l1pte_set_readonly(pte)	(((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO)
1010 #define l2pte_set_writable(pte)	(((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W)
1011 #define l2pte_set_readonly(pte)	(((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO)
1012 
1013 #define l2pte_writable_p(pte)	(((pte) & L2_S_PROT_W) == L2_S_PROT_W && \
1014 				 (L2_S_PROT_RO == 0 || \
1015 				  ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO))
1016 
1017 /*
1018  * These macros return various bits based on kernel/user and protection.
1019  * Note that the compiler will usually fold these at compile time.
1020  */
1021 #define	L1_S_PROT(ku, pr)	((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
1022 				 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO))
1023 
1024 #define	L2_L_PROT(ku, pr)	((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
1025 				 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO))
1026 
1027 #define	L2_S_PROT(ku, pr)	((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
1028 				 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO))
1029 
1030 /*
1031  * Macros to test if a mapping is mappable with an L1 SuperSection,
1032  * L1 Section, or an L2 Large Page mapping.
1033  */
1034 #define	L1_SS_MAPPABLE_P(va, pa, size)					\
1035 	((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE)
1036 
1037 #define	L1_S_MAPPABLE_P(va, pa, size)					\
1038 	((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
1039 
1040 #define	L2_L_MAPPABLE_P(va, pa, size)					\
1041 	((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
1042 
1043 #ifndef _LOCORE
1044 /*
1045  * Hooks for the pool allocator.
1046  */
1047 #define	POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
1048 extern paddr_t physical_start, physical_end;
1049 #ifdef PMAP_NEED_ALLOC_POOLPAGE
1050 struct vm_page *arm_pmap_alloc_poolpage(int);
1051 #define	PMAP_ALLOC_POOLPAGE	arm_pmap_alloc_poolpage
1052 #endif
1053 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
1054 vaddr_t	pmap_map_poolpage(paddr_t);
1055 paddr_t	pmap_unmap_poolpage(vaddr_t);
1056 #define	PMAP_MAP_POOLPAGE(pa)	pmap_map_poolpage(pa)
1057 #define PMAP_UNMAP_POOLPAGE(va)	pmap_unmap_poolpage(va)
1058 #endif
1059 
1060 /*
1061  * pmap-specific data store in the vm_page structure.
1062  */
1063 #define	__HAVE_VM_PAGE_MD
1064 struct vm_page_md {
1065 	SLIST_HEAD(,pv_entry) pvh_list;		/* pv_entry list */
1066 	int pvh_attrs;				/* page attributes */
1067 	u_int uro_mappings;
1068 	u_int urw_mappings;
1069 	union {
1070 		u_short s_mappings[2];	/* Assume kernel count <= 65535 */
1071 		u_int i_mappings;
1072 	} k_u;
1073 #define	kro_mappings	k_u.s_mappings[0]
1074 #define	krw_mappings	k_u.s_mappings[1]
1075 #define	k_mappings	k_u.i_mappings
1076 };
1077 
1078 /*
1079  * Set the default color of each page.
1080  */
1081 #if ARM_MMU_V6 > 0
1082 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
1083 	(pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask
1084 #else
1085 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
1086 	(pg)->mdpage.pvh_attrs = 0
1087 #endif
1088 
1089 #define	VM_MDPAGE_INIT(pg)						\
1090 do {									\
1091 	SLIST_INIT(&(pg)->mdpage.pvh_list);				\
1092 	VM_MDPAGE_PVH_ATTRS_INIT(pg);					\
1093 	(pg)->mdpage.uro_mappings = 0;					\
1094 	(pg)->mdpage.urw_mappings = 0;					\
1095 	(pg)->mdpage.k_mappings = 0;					\
1096 } while (/*CONSTCOND*/0)
1097 
1098 #endif /* !_LOCORE */
1099 
1100 #endif /* _KERNEL */
1101 
1102 #endif	/* _ARM32_PMAP_H_ */
1103