1 /* $NetBSD: frame.h,v 1.41 2015/04/08 18:10:08 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * Switch frame. 55 * 56 * Should be a multiple of 8 bytes for dumpsys. 57 */ 58 59 struct switchframe { 60 u_int sf_r4; 61 u_int sf_r5; 62 u_int sf_r6; 63 u_int sf_r7; 64 u_int sf_sp; 65 u_int sf_pc; 66 }; 67 68 /* 69 * System stack frames. 70 */ 71 72 struct clockframe { 73 struct trapframe cf_tf; 74 }; 75 76 /* 77 * Stack frame. Used during stack traces (db_trace.c) 78 */ 79 struct frame { 80 u_int fr_fp; 81 u_int fr_sp; 82 u_int fr_lr; 83 u_int fr_pc; 84 }; 85 86 #ifdef _KERNEL 87 void validate_trapframe(trapframe_t *, int); 88 #endif /* _KERNEL */ 89 90 #else /* _LOCORE */ 91 92 #include "opt_compat_netbsd.h" 93 #include "opt_execfmt.h" 94 #include "opt_multiprocessor.h" 95 #include "opt_cpuoptions.h" 96 #include "opt_arm_debug.h" 97 #include "opt_cputypes.h" 98 99 #include <arm/locore.h> 100 101 /* 102 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 103 * any pending softints. 104 */ 105 #ifdef _ARM_ARCH_4T 106 #define B_CF_CONTROL(rX) ;\ 107 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 108 bx ip /* branch to cpu_control */ 109 #else 110 #define B_CF_CONTROL(rX) ;\ 111 ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */ 112 #endif 113 #ifdef _ARM_ARCH_5T 114 #define BL_CF_CONTROL(rX) ;\ 115 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 116 blx ip /* call cpu_control */ 117 #else 118 #define BL_CF_CONTROL(rX) ;\ 119 mov lr, pc ;\ 120 ldr pc, [rX, #CF_CONTROL] /* call cpu_control */ 121 #endif 122 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 123 #define DO_PENDING_SOFTINTS \ 124 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 125 cmp r0, #0 /* Test for 0. */ ;\ 126 bne 10f /* skip softints if != 0 */ ;\ 127 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 128 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 129 lsrs r0, r1, r0 /* shift mask by cpl */ ;\ 130 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 131 10: 132 #else 133 #define DO_PENDING_SOFTINTS /* nothing */ 134 #endif 135 136 #ifdef _ARM_ARCH_6 137 #define GET_CPSR(rb) /* nothing */ 138 #define CPSID_I(ra,rb) cpsid i 139 #define CPSIE_I(ra,rb) cpsie i 140 #else 141 #define GET_CPSR(rb) \ 142 mrs rb, cpsr /* fetch CPSR */ 143 144 #define CPSID_I(ra,rb) \ 145 orr ra, rb, #(IF32_bits) ;\ 146 msr cpsr_c, ra /* Disable interrupts */ 147 148 #define CPSIE_I(ra,rb) \ 149 bic ra, rb, #(IF32_bits) ;\ 150 msr cpsr_c, ra /* Restore interrupts */ 151 #endif 152 153 /* 154 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 155 * These are used in order to support dynamic enabling/disabling of 156 * alignment faults when executing old a.out ARM binaries. 157 * 158 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 159 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 160 * relies on r4 being preserved. 161 */ 162 #ifdef EXEC_AOUT 163 #define AST_ALIGNMENT_FAULT_LOCALS \ 164 .Laflt_cpufuncs: ;\ 165 .word _C_LABEL(cpufuncs) 166 167 /* 168 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 169 * the top of interrupt/exception handlers. 170 * 171 * When invoked, r0 *must* contain the value of SPSR on the current 172 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 173 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 174 */ 175 #define ENABLE_ALIGNMENT_FAULTS \ 176 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 177 cmp r7, #(PSR_USR32_MODE) ;\ 178 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 179 bne 1f /* Not USR mode skip AFLT */ ;\ 180 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 181 ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\ 182 tst r1, #MDLWP_NOALIGNFLT ;\ 183 beq 1f /* AFLTs already enabled */ ;\ 184 ldr r2, .Laflt_cpufuncs ;\ 185 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 186 mov r0, #-1 ;\ 187 BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\ 188 1: /* done */ 189 190 /* 191 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 192 * PULLFRAME at the end of interrupt/exception handlers. We know that 193 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 194 * for use. 195 */ 196 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 197 DO_PENDING_SOFTINTS ;\ 198 GET_CPSR(r5) /* save CPSR */ ;\ 199 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 200 cmp r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\ 201 bne 3f /* Nope, get out now */ ;\ 202 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 203 tst r1, #0x00000001 ;\ 204 bne 2f /* Yup. Go deal with it */ ;\ 205 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 206 ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\ 207 tst r0, #MDLWP_NOALIGNFLT ;\ 208 beq 3f /* Keep AFLTs enabled */ ;\ 209 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 210 ldr r2, .Laflt_cpufuncs ;\ 211 mov r0, #-1 ;\ 212 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 213 adr lr, 3f ;\ 214 B_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\ 215 /* NOTREACHED */ \ 216 2: CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 217 mov r0, sp ;\ 218 bl _C_LABEL(ast) /* ast(frame) */ ;\ 219 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 220 b 1b /* Back around again */ ;\ 221 3: /* done */ 222 223 #else /* !EXEC_AOUT */ 224 225 #define AST_ALIGNMENT_FAULT_LOCALS 226 227 #define ENABLE_ALIGNMENT_FAULTS \ 228 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 229 GET_CURCPU(r4) /* r4 = cpuinfo */ 230 231 232 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 233 DO_PENDING_SOFTINTS ;\ 234 GET_CPSR(r5) /* save CPSR */ ;\ 235 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 236 cmp r7, #(PSR_USR32_MODE) ;\ 237 bne 2f /* Nope, get out now */ ;\ 238 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 239 tst r1, #0x00000001 ;\ 240 beq 2f /* Nope. Just bail */ ;\ 241 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 242 mov r0, sp ;\ 243 bl _C_LABEL(ast) /* ast(frame) */ ;\ 244 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 245 b 1b ;\ 246 2: /* done */ 247 #endif /* EXEC_AOUT */ 248 249 #ifndef _ARM_ARCH_6 250 #ifdef ARM_LOCK_CAS_DEBUG 251 #define LOCK_CAS_DEBUG_LOCALS \ 252 .L_lock_cas_restart: ;\ 253 .word _C_LABEL(_lock_cas_restart) 254 255 #if defined(__ARMEB__) 256 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 257 ble 99f ;\ 258 ldr r0, .L_lock_cas_restart ;\ 259 ldmia r0, {r1-r2} /* load ev_count */ ;\ 260 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 261 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 262 stmia r0, {r1-r2} /* store ev_count */ 263 #else /* __ARMEB__ */ 264 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 265 ble 99f ;\ 266 ldr r0, .L_lock_cas_restart ;\ 267 ldmia r0, {r1-r2} /* load ev_count */ ;\ 268 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 269 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 270 stmia r0, {r1-r2} /* store ev_count */ 271 #endif /* __ARMEB__ */ 272 #else /* ARM_LOCK_CAS_DEBUG */ 273 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 274 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 275 #endif /* ARM_LOCK_CAS_DEBUG */ 276 277 #define LOCK_CAS_CHECK_LOCALS \ 278 .L_lock_cas: ;\ 279 .word _C_LABEL(_lock_cas) ;\ 280 .L_lock_cas_end: ;\ 281 .word _C_LABEL(_lock_cas_end) ;\ 282 LOCK_CAS_DEBUG_LOCALS 283 284 #define LOCK_CAS_CHECK \ 285 ldr r0, [sp] /* get saved PSR */ ;\ 286 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 287 cmp r0, #(PSR_SVC32_MODE) ;\ 288 bne 99f /* nope, get out now */ ;\ 289 ldr r0, [sp, #(TF_PC)] ;\ 290 ldr r1, .L_lock_cas_end ;\ 291 cmp r0, r1 ;\ 292 bge 99f ;\ 293 ldr r1, .L_lock_cas ;\ 294 cmp r0, r1 ;\ 295 strgt r1, [sp, #(TF_PC)] ;\ 296 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 297 99: 298 299 #else 300 #define LOCK_CAS_CHECK /* nothing */ 301 #define LOCK_CAS_CHECK_LOCALS /* nothing */ 302 #endif 303 304 /* 305 * ASM macros for pushing and pulling trapframes from the stack 306 * 307 * These macros are used to handle the trapframe structure defined above. 308 */ 309 310 /* 311 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 312 * Since the current mode is used, the SVC lr field is not defined. 313 */ 314 315 #ifdef CPU_SA110 316 /* 317 * NOTE: r13 and r14 are stored separately as a work around for the 318 * SA110 rev 2 STM^ bug 319 */ 320 #define PUSHUSERREGS \ 321 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 322 add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \ 323 stmia r0, {r13-r14}^ /* Push the user mode registers */ 324 #else 325 #define PUSHUSERREGS \ 326 stmia sp, {r0-r14}^ /* Push the user mode registers */ 327 #endif 328 329 #define PUSHFRAME \ 330 str lr, [sp, #-4]!; /* Push the return address */ \ 331 sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 332 PUSHUSERREGS; /* Push the user mode registers */ \ 333 mov r0, r0; /* NOP for previous instruction */ \ 334 mrs r0, spsr; /* Get the SPSR */ \ 335 str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */ 336 337 /* 338 * Push a minimal trapframe so we can dispatch an interrupt from the 339 * idle loop. The only reason the idle loop wakes up is to dispatch 340 * interrupts so why take the avoid of a full exception when we can do 341 * something minimal. 342 */ 343 #define PUSHIDLEFRAME \ 344 str lr, [sp, #-4]!; /* save SVC32 lr */ \ 345 str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \ 346 str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \ 347 mrs r0, cpsr; /* Get the CPSR */ \ 348 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */ 349 350 /* 351 * Push a trapframe to be used by cpu_switchto 352 */ 353 #define PUSHSWITCHFRAME(rX) \ 354 mov ip, sp; \ 355 sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \ 356 push {r4-r11}; /* Push the callee saved registers */ \ 357 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 358 str ip, [sp, #TF_SVC_SP]; \ 359 str lr, [sp, #TF_SVC_LR]; \ 360 str lr, [sp, #TF_PC]; \ 361 mrs rX, cpsr; /* Get the CPSR */ \ 362 str rX, [sp, #TF_SPSR] /* save in trapframe */ 363 364 #define PUSHSWITCHFRAME1 \ 365 mov ip, sp; \ 366 sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \ 367 push {r4-r7}; /* Push some of the callee saved registers */ \ 368 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 369 str ip, [sp, #TF_SVC_SP]; \ 370 str lr, [sp, #TF_SVC_LR]; \ 371 str lr, [sp, #TF_PC] 372 373 #if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__ 374 #define PUSHSWITCHFRAME2 \ 375 strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \ 376 strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \ 377 mrs r0, cpsr; /* Get the CPSR */ \ 378 str r0, [sp, #TF_SPSR] /* save in trapframe */ 379 #else 380 #define PUSHSWITCHFRAME2 \ 381 add r0, sp, #TF_R8; /* get ptr to r8 and above */ \ 382 stmia r0, {r8-r11}; /* save rest of registers */ \ 383 mrs r0, cpsr; /* Get the CPSR */ \ 384 str r0, [sp, #TF_SPSR] /* save in trapframe */ 385 #endif 386 387 /* 388 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 389 * Since the current mode is used, the SVC lr field is ignored. 390 */ 391 392 #define PULLFRAME \ 393 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 394 msr spsr_fsxc, r0; \ 395 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 396 mov r0, r0; /* NOP for previous instruction */ \ 397 add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 398 ldr lr, [sp], #0x0004 /* Pop the return address */ 399 400 #define PULLIDLEFRAME \ 401 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 402 ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \ 403 ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \ 404 ldr lr, [sp], #4 /* Pop the return address */ 405 406 /* 407 * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1). 408 */ 409 #define PULLSWITCHFRAME \ 410 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 411 pop {r4-r11}; /* pop the callee saved registers */ \ 412 add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \ 413 ldr lr, [sp], #4; /* pop the return address */ 414 415 /* 416 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 417 * This should only be used if the processor is not currently in SVC32 418 * mode. The processor mode is switched to SVC mode and the trap frame is 419 * stored. The SVC lr field is used to store the previous value of 420 * lr in SVC mode. 421 * 422 * NOTE: r13 and r14 are stored separately as a work around for the 423 * SA110 rev 2 STM^ bug 424 */ 425 426 #ifdef _ARM_ARCH_6 427 #define SET_CPSR_MODE(tmp, mode) \ 428 cps #(mode) 429 #else 430 #define SET_CPSR_MODE(tmp, mode) \ 431 mrs tmp, cpsr; /* Get the CPSR */ \ 432 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 433 orr tmp, tmp, #(mode); \ 434 msr cpsr_c, tmp /* Punch into SVC mode */ 435 #endif 436 437 #define PUSHFRAMEINSVC \ 438 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 439 mov r0, lr; /* Save xxx32 r14 */ \ 440 mov r1, sp; /* Save xxx32 sp */ \ 441 mrs r3, spsr; /* Save xxx32 spsr */ \ 442 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 443 bic r2, sp, #7; /* Align new SVC sp */ \ 444 str r0, [r2, #-4]!; /* Push return address */ \ 445 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 446 mov sp, r2; /* Keep stack aligned */ \ 447 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 448 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 449 sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 450 PUSHUSERREGS; /* Push the user mode registers */ \ 451 mov r0, r0; /* NOP for previous instruction */ \ 452 mrs r0, spsr; /* Get the SPSR */ \ 453 str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */ 454 455 /* 456 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 457 * in SVC32 mode and restore the saved processor mode and PC. 458 * This should be used when the SVC lr register needs to be restored on 459 * exit. 460 */ 461 462 #define PULLFRAMEFROMSVCANDEXIT \ 463 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 464 msr spsr_fsxc, r0; /* restore SPSR */ \ 465 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 466 mov r0, r0; /* NOP for previous instruction */ \ 467 add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 468 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 469 470 #endif /* _LOCORE */ 471 472 #endif /* _ARM32_FRAME_H_ */ 473