1 /* $NetBSD: imxusbreg.h,v 1.1 2010/11/30 13:05:27 bsh Exp $ */ 2 /* 3 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _ARM_IMX_IMXUSBREG_H 29 #define _ARM_IMX_IMXUSBREG_H 30 31 #define IMXUSB_ID 0x0000 32 #define IMXUSB_ID_ID_MASK __BITS(5,0) 33 #define IMXUSB_ID_REVISION_SHIFT 16 34 #define IMXUSB_ID_REVISION_MASK __BITS(IMXUSB_ID_REVISION_SHIFT,23) 35 #define IMXUSB_HWGENERAL 0x0004 36 #define IMXUSB_HWHOST 0x0008 37 #define HWHOST_HC __BIT(0) 38 #define HWHOST_NPORT_SHIFT 1 39 #define HWHOST_NPORT_MASK __BITS(HWHOST_NPORT_SHIFT,3) 40 #define IMXUSB_HWDEVICE 0x000c 41 #define HWDEVICE_DC __BIT(0) 42 #define HWDEVICE_DEVEP_SHIFT 1 43 #define HWDEVICE_DEVEP_MASK __BITS(HWDEVICE_DEVEP_SHIFT,5) 44 #define IMXUSB_HWTXBUF 0x0010 45 #define IMXUSB_HWRXBUF 0x0014 46 47 #define IMXUSB_EHCIREGS 0x0100 48 49 #define IMXUSB_ULPIVIEW 0x0170 50 #define ULPI_WU __BIT(31) 51 #define ULPI_RUN __BIT(30) 52 #define ULPI_RW __BIT(29) 53 #define ULPI_SS __BIT(27) 54 #define ULPI_PORT_SHIFT 24 55 #define ULPI_PORT_MASK (0x7 << ULPI_PORT_SHIFT) 56 #define ULPI_ADDR_SHIFT 16 57 #define ULPI_ADDR_MASK (0xff << ULPI_ADDR_SHIFT) 58 #define ULPI_DATRD_SHIFT 8 59 #define ULPI_DATRD_MASK (0xff << ULPI_DATRD_SHIFT) 60 #define ULPI_DATWR_SHIFT 0 61 #define ULPI_DATWR_MASK (0xff << ULPI_DATWR_SHIFT) 62 63 #define IMXUSB_OTGSC 0x01A4 64 #define OTGSC_DPIE __BIT(30) 65 #define OTGSC_1MSE __BIT(29) 66 #define OTGSC_BSEIE __BIT(28) 67 #define OTGSC_BSVIE __BIT(27) 68 #define OTGSC_ASVIE __BIT(26) 69 #define OTGSC_AVVIE __BIT(25) 70 #define OTGSC_IDIE __BIT(24) 71 #define OTGSC_DPIS __BIT(22) 72 #define OTGSC_1MSS __BIT(21) 73 #define OTGSC_BSEIS __BIT(20) 74 #define OTGSC_BSVIS __BIT(19) 75 #define OTGSC_ASVIS __BIT(18) 76 #define OTGSC_AVVIS __BIT(17) 77 #define OTGSC_IDIS __BIT(16) 78 #define OTGSC_DPS __BIT(14) 79 #define OTGSC_1MST __BIT(13) 80 #define OTGSC_BSE __BIT(12) 81 #define OTGSC_BSV __BIT(11) 82 #define OTGSC_ASV __BIT(10) 83 #define OTGSC_AVV __BIT( 9) 84 #define OTGSC_ID __BIT( 8) 85 #define OTGSC_IDPU __BIT( 5) 86 #define OTGSC_DP __BIT( 4) 87 #define OTGSC_OT __BIT( 3) 88 #define OTGSC_VC __BIT( 1) 89 #define OTGSC_VD __BIT( 0) 90 #define IMXUSB_OTGMODE 0x01A8 91 #define USBMODE_DEVICE (0x2 << 0) 92 #define USBMODE_HOST (0x3 << 0) 93 94 #define IMXUSB_EHCI_SIZE 0x200 95 96 97 /* extension to PORTSCx register of EHCI. */ 98 #define PORTSC_PTS_SHIFT 30 99 #define PORTSC_PTS_MASK __BITS(PORTSC_PTS_SHIFT,31) 100 #define PORTSC_PTS_UTMI (0 << PORTSC_PTS_SHIFT) 101 #define PORTSC_PTS_PHILIPS (1 << PORTSC_PTS_SHIFT) /* not in i.MX51*/ 102 #define PORTSC_PTS_ULPI (2 << PORTSC_PTS_SHIFT) 103 #define PORTSC_PTS_SERIAL (3 << PORTSC_PTS_SHIFT) 104 105 #define PORTSC_STS __BIT(29) /* serial transeiver select */ 106 #define PORTSC_PTW __BIT(28) /* parallel transceiver width */ 107 #define PORTSC_PTW_8 0 108 #define PORTSC_PTW_16 PORT_SC_PTW 109 #define PORTSC_PSPD __BITS(26,27) /* port speed (RO) */ 110 #define PORTSC_PFSC __BIT(24) /* port force full speed */ 111 #define PORTSC_PHCD __BIT(23) /* PHY low power suspend */ 112 113 #endif /* _ARM_IMX_IMXUSBREG_H */ 114