xref: /netbsd-src/sys/arch/arm/imx/imxusb.c (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /*	$NetBSD: imxusb.c,v 1.13 2018/04/09 16:21:09 jakllsch Exp $	*/
2 /*
3  * Copyright (c) 2009, 2010  Genetec Corporation.  All rights reserved.
4  * Written by Hashimoto Kenichi and Hiroyuki Bessho for Genetec Corporation.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: imxusb.c,v 1.13 2018/04/09 16:21:09 jakllsch Exp $");
29 
30 #include "opt_imx.h"
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/conf.h>
35 #include <sys/kernel.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/bus.h>
39 
40 #include <dev/usb/usb.h>
41 #include <dev/usb/usbdi.h>
42 #include <dev/usb/usbdivar.h>
43 #include <dev/usb/usb_mem.h>
44 
45 #include <dev/usb/ehcireg.h>
46 #include <dev/usb/ehcivar.h>
47 
48 #include <arm/pic/picvar.h>	/* XXX: for intr_establish! */
49 
50 #include <arm/imx/imxusbreg.h>
51 #include <arm/imx/imxusbvar.h>
52 #include <arm/imx/imxgpiovar.h>
53 #include "locators.h"
54 
55 #include <dev/usb/ulpireg.h>	/* for test */
56 
57 static int	imxehci_match(device_t, cfdata_t, void *);
58 static void	imxehci_attach(device_t, device_t, void *);
59 
60 uint8_t imxusb_ulpi_read(struct imxehci_softc *sc, int addr);
61 void imxusb_ulpi_write(struct imxehci_softc *sc, int addr, uint8_t data);
62 static void ulpi_reset(struct imxehci_softc *sc);
63 
64 static void imxehci_select_interface(struct imxehci_softc *, enum imx_usb_if);
65 static void imxehci_init(struct ehci_softc *);
66 
67 /* attach structures */
68 CFATTACH_DECL_NEW(imxehci, sizeof(struct imxehci_softc),
69     imxehci_match, imxehci_attach, NULL, NULL);
70 
71 static int
72 imxehci_match(device_t parent, cfdata_t cf, void *aux)
73 {
74 	struct imxusbc_attach_args *aa = aux;
75 
76 	if (aa->aa_unit < 0 || 3 < aa->aa_unit) {
77 		return 0;
78 	}
79 
80 	return 1;
81 }
82 
83 static void
84 imxehci_attach(device_t parent, device_t self, void *aux)
85 {
86 	struct imxusbc_attach_args *aa = aux;
87 	struct imxusbc_softc *usbc = device_private(parent);
88 	struct imxehci_softc *sc = device_private(self);
89 	ehci_softc_t *hsc = &sc->sc_hsc;
90 	bus_space_tag_t iot;
91 	uint16_t hcirev;
92 	uint32_t id, hwhost, hwdevice;
93 	const char *comma;
94 
95 	sc->sc_hsc.sc_dev = self;
96 	iot = sc->sc_iot = sc->sc_hsc.iot = aa->aa_iot;
97 	sc->sc_unit = aa->aa_unit;
98 	sc->sc_usbc = usbc;
99 	hsc->sc_bus.ub_hcpriv = sc;
100 	hsc->sc_flags |= EHCIF_ETTF;
101 	hsc->sc_vendor_init = imxehci_init;
102 
103 	aprint_naive("\n");
104 	aprint_normal(": i.MX USB Controller\n");
105 
106 	if (usbc->sc_ehci_size == 0)
107 		usbc->sc_ehci_size = IMXUSB_EHCI_SIZE;	/* use default */
108 
109 	/* per unit registers */
110 	if (bus_space_subregion(iot, aa->aa_ioh,
111 		aa->aa_unit * usbc->sc_ehci_size, usbc->sc_ehci_size,
112 		&sc->sc_ioh) ||
113 	    bus_space_subregion(iot, aa->aa_ioh,
114 		aa->aa_unit * usbc->sc_ehci_size + IMXUSB_EHCIREGS,
115 		usbc->sc_ehci_size - IMXUSB_EHCIREGS,
116 		&sc->sc_hsc.ioh)) {
117 
118 		aprint_error_dev(self, "can't subregion\n");
119 		return;
120 	}
121 
122 	id = bus_space_read_4(iot, sc->sc_ioh, IMXUSB_ID);
123 	hcirev = bus_space_read_2(iot, sc->sc_hsc.ioh, EHCI_HCIVERSION);
124 
125 	aprint_normal_dev(self,
126 	    "id=%d revision=%d HCI revision=0x%x\n",
127 	    (int)__SHIFTOUT(id, IMXUSB_ID_ID),
128 	    (int)__SHIFTOUT(id, IMXUSB_ID_REVISION),
129 	    hcirev);
130 
131 	hwhost = bus_space_read_4(iot, sc->sc_ioh, IMXUSB_HWHOST);
132 	hwdevice = bus_space_read_4(iot, sc->sc_ioh, IMXUSB_HWDEVICE);
133 
134 	aprint_normal_dev(self, "");
135 
136 	comma = "";
137 	if (hwhost & HWHOST_HC) {
138 		int n_ports = 1 + __SHIFTOUT(hwhost, HWHOST_NPORT);
139 		aprint_normal("%d host port%s",
140 		    n_ports, n_ports > 1 ? "s" : "");
141 		comma = ", ";
142 	}
143 
144 	if (hwdevice & HWDEVICE_DC) {
145 		int n_endpoints = __SHIFTOUT(hwdevice, HWDEVICE_DEVEP);
146 		aprint_normal("%sdevice capable, %d endpoint%s",
147 		    comma,
148 		    n_endpoints, n_endpoints > 1 ? "s" : "");
149 	}
150 	aprint_normal("\n");
151 
152 	sc->sc_hsc.sc_bus.ub_dmatag = aa->aa_dmat;
153 
154 	sc->sc_hsc.sc_offs = bus_space_read_1(iot, sc->sc_hsc.ioh,
155 	    EHCI_CAPLENGTH);
156 
157 	/* Platform dependent setup */
158 	if (usbc->sc_init_md_hook)
159 		usbc->sc_init_md_hook(sc);
160 
161 	imxehci_reset(sc);
162 	imxehci_select_interface(sc, sc->sc_iftype);
163 
164 	if (sc->sc_iftype == IMXUSBC_IF_ULPI) {
165 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, 0);
166 
167 		aprint_normal_dev(hsc->sc_dev,
168 		    "ULPI phy VID 0x%04x PID 0x%04x\n",
169 		    (imxusb_ulpi_read(sc, ULPI_VENDOR_ID_LOW) |
170 			imxusb_ulpi_read(sc, ULPI_VENDOR_ID_HIGH) << 8),
171 		    (imxusb_ulpi_read(sc, ULPI_PRODUCT_ID_LOW) |
172 			imxusb_ulpi_read(sc, ULPI_PRODUCT_ID_HIGH) << 8));
173 
174 		ulpi_reset(sc);
175 
176 	}
177 
178 	if (usbc->sc_setup_md_hook)
179 		usbc->sc_setup_md_hook(sc, IMXUSB_HOST);
180 
181 	if (sc->sc_iftype == IMXUSBC_IF_ULPI) {
182 #if 0
183 		if(hsc->sc_bus.ub_revision == USBREV_2_0)
184 			ulpi_write(hsc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR, (1 << 0));
185 		else
186 			ulpi_write(hsc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, (1 << 2));
187 #endif
188 
189 		imxusb_ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR,
190 		    OTG_CONTROL_IDPULLUP);
191 
192 		imxusb_ulpi_write(sc, ULPI_OTG_CONTROL + ULPI_REG_SET,
193 		    OTG_CONTROL_USEEXTVBUSIND |
194 		    OTG_CONTROL_DRVVBUSEXT |
195 		    OTG_CONTROL_DRVVBUS |
196 		    OTG_CONTROL_CHRGVBUS
197 		    );
198 	}
199 
200 	/* Disable interrupts, so we don't get any spurious ones. */
201 	EOWRITE4(hsc, EHCI_USBINTR, 0);
202 
203 	intr_establish(aa->aa_irq, IPL_USB, IST_LEVEL, ehci_intr, hsc);
204 
205 	int err = ehci_init(hsc);
206 	if (err) {
207 		aprint_error_dev(self, "init failed, error=%d\n", err);
208 		return;
209 	}
210 
211 	/* Attach usb device. */
212 	hsc->sc_child = config_found(self, &hsc->sc_bus, usbctlprint);
213 }
214 
215 static void
216 imxehci_select_interface(struct imxehci_softc *sc, enum imx_usb_if interface)
217 {
218 	uint32_t reg;
219 	struct ehci_softc *hsc = &sc->sc_hsc;
220 
221 	reg = EOREAD4(hsc, EHCI_PORTSC(1));
222 	reg &= ~(PORTSC_PTS | PORTSC_PTW | PORTSC_PTS2);
223 	switch (interface) {
224 	case IMXUSBC_IF_UTMI_WIDE:
225 		reg |= PORTSC_PTW_16;
226 	case IMXUSBC_IF_UTMI:
227 		reg |= PORTSC_PTS_UTMI;
228 		break;
229 	case IMXUSBC_IF_PHILIPS:
230 		reg |= PORTSC_PTS_PHILIPS;
231 		break;
232 	case IMXUSBC_IF_ULPI:
233 		reg |= PORTSC_PTS_ULPI;
234 		break;
235 	case IMXUSBC_IF_SERIAL:
236 		reg |= PORTSC_PTS_SERIAL;
237 		break;
238 	case IMXUSBC_IF_HSIC:
239 		reg |= PORTSC_PTS2;
240 		break;
241 	}
242 	EOWRITE4(hsc, EHCI_PORTSC(1), reg);
243 }
244 
245 static uint32_t
246 ulpi_wakeup(struct imxehci_softc *sc, int tout)
247 {
248 	uint32_t ulpi_view;
249 	int i = 0;
250 	ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW);
251 
252 	if ( !(ulpi_view & ULPI_SS) ) {
253 		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
254 		    IMXUSB_ULPIVIEW, ULPI_WU);
255 		for (i = 0; (tout < 0) || (i < tout); i++) {
256 			ulpi_view = bus_space_read_4(sc->sc_iot,
257 			    sc->sc_ioh, IMXUSB_ULPIVIEW);
258 			if ( !(ulpi_view & ULPI_WU) )
259 				break;
260 			delay(1);
261 		};
262 	}
263 
264 	if ((tout > 0) && (i >= tout)) {
265 		aprint_error_dev(sc->sc_hsc.sc_dev, "%s: timeout\n", __func__);
266 	}
267 
268 	return ulpi_view;
269 }
270 
271 static uint32_t
272 ulpi_wait(struct imxehci_softc *sc, int tout)
273 {
274 	uint32_t ulpi_view;
275 	int i;
276 	ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW);
277 
278 	for (i = 0; (tout < 0) | (i < tout); i++) {
279 		ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
280 		    IMXUSB_ULPIVIEW);
281 		if (!(ulpi_view & ULPI_RUN))
282 			break;
283 		delay(1);
284 	}
285 
286 	if ((tout > 0) && (i >= tout)) {
287 		aprint_error_dev(sc->sc_hsc.sc_dev, "%s: timeout\n", __func__);
288 	}
289 
290 	return ulpi_view;
291 }
292 
293 #define	TIMEOUT	100000
294 
295 uint8_t
296 imxusb_ulpi_read(struct imxehci_softc *sc, int addr)
297 {
298 	uint32_t data;
299 
300 	ulpi_wakeup(sc, TIMEOUT);
301 
302 	data = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR);
303 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, data);
304 
305 	data = ulpi_wait(sc, TIMEOUT);
306 
307 	return __SHIFTOUT(data, ULPI_DATRD);
308 }
309 
310 void
311 imxusb_ulpi_write(struct imxehci_softc *sc, int addr, uint8_t data)
312 {
313 	uint32_t reg;
314 
315 	ulpi_wakeup(sc, TIMEOUT);
316 
317 	reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);
318 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, reg);
319 
320 	ulpi_wait(sc, TIMEOUT);
321 
322 	return;
323 }
324 
325 #if 0
326 static int
327 ulpi_scratch_test(struct imxehci_softc *sc)
328 {
329 	uint32_t ulpi_view;
330 
331 	ulpi_view = ulpi_wakeup(sc, 1000);
332 	if (ulpi_view & ULPI_WU) {
333 		return -1;
334 	}
335 
336 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW,
337 		(ULPI_RUN | ULPI_RW |
338 		 (ULPI_SCRATCH << ULPI_ADDR_SHIFT) | 0xAA));
339 
340 	ulpi_view = ulpi_wait(sc, 1000);
341 
342 	if (ulpi_view & ULPI_RUN) {
343 		return -1;
344 	}
345 
346 	return 0;
347 }
348 #endif
349 
350 static void
351 ulpi_reset(struct imxehci_softc *sc)
352 {
353 	uint8_t data;
354 	int timo = 1000 * 1000;	/* XXXX: 1sec */
355 
356 	imxusb_ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET,
357 	    FUNCTION_CONTROL_RESET /*0x20*/);
358 	do {
359 		data = imxusb_ulpi_read(sc, ULPI_FUNCTION_CONTROL);
360 		if (!(data & FUNCTION_CONTROL_RESET))
361 			break;
362 		delay(100);
363 		timo -= 100;
364 	} while (timo > 0);
365 	if (timo <= 0) {
366 		aprint_error_dev(sc->sc_hsc.sc_dev, "%s: reset failed!!\n",
367 		    __func__);
368 		return;
369 	}
370 
371 	return;
372 }
373 
374 void
375 imxehci_reset(struct imxehci_softc *sc)
376 {
377 	uint32_t reg;
378 	int i;
379 	struct ehci_softc *hsc = &sc->sc_hsc;
380 #define	RESET_TIMEOUT 100
381 
382 	reg = EOREAD4(hsc, EHCI_USBCMD);
383 	reg &= ~EHCI_CMD_RS;
384 	EOWRITE4(hsc, EHCI_USBCMD, reg);
385 
386 	for (i=0; i < RESET_TIMEOUT; ++i) {
387 		reg = EOREAD4(hsc, EHCI_USBCMD);
388 		if ((reg & EHCI_CMD_RS) == 0)
389 			break;
390 		usb_delay_ms(&hsc->sc_bus, 1);
391 	}
392 
393 	EOWRITE4(hsc, EHCI_USBCMD, reg | EHCI_CMD_HCRESET);
394 	for (i = 0; i < RESET_TIMEOUT; i++) {
395 		reg = EOREAD4(hsc, EHCI_USBCMD);
396 		if ((reg &  EHCI_CMD_HCRESET) == 0)
397 			break;
398 		usb_delay_ms(&hsc->sc_bus, 1);
399 	}
400 	if (i >= RESET_TIMEOUT) {
401 		aprint_error_dev(hsc->sc_dev, "reset timeout (%x)\n", reg);
402 	}
403 
404 	usb_delay_ms(&hsc->sc_bus, 100);
405 }
406 
407 static void
408 imxehci_init(struct ehci_softc *hsc)
409 {
410 	struct imxehci_softc *sc = device_private(hsc->sc_dev);
411 	uint32_t reg;
412 
413 	reg = EOREAD4(hsc, EHCI_PORTSC(1));
414 	reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC);
415 	reg |= EHCI_PS_PP | EHCI_PS_PE;
416 	EOWRITE4(hsc, EHCI_PORTSC(1), reg);
417 
418 	reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC);
419 	reg |= OTGSC_IDPU;
420 	/* disable IDIE not to conflict with SSP1_DETECT. */
421 	//reg |= OTGSC_DPIE | OTGSC_IDIE;
422 	reg |= OTGSC_DPIE;
423 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC, reg);
424 
425 	reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_USBMODE);
426 	reg &= ~USBMODE_CM;
427 	reg |= USBMODE_CM_HOST;
428 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_USBMODE, reg);
429 }
430