1 /* $NetBSD: imxuart.c,v 1.22 2019/11/10 21:16:23 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.22 2019/11/10 21:16:23 chs Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_ddbparam.h" 104 #include "opt_kgdb.h" 105 #include "opt_lockdebug.h" 106 #include "opt_multiprocessor.h" 107 #include "opt_ntp.h" 108 #include "opt_imxuart.h" 109 110 #ifdef RND_COM 111 #include <sys/rndsource.h> 112 #endif 113 114 #ifndef IMXUART_TOLERANCE 115 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 116 #endif 117 118 #ifndef IMXUART_FREQDIV 119 #define IMXUART_FREQDIV 2 /* XXX */ 120 #endif 121 122 #ifndef IMXUART_FREQ 123 #define IMXUART_FREQ (56900000) 124 #endif 125 126 /* 127 * Override cnmagic(9) macro before including <sys/systm.h>. 128 * We need to know if cn_check_magic triggered debugger, so set a flag. 129 * Callers of cn_check_magic must declare int cn_trapped = 0; 130 * XXX: this is *ugly*! 131 */ 132 #define cn_trap() \ 133 do { \ 134 console_debugger(); \ 135 cn_trapped = 1; \ 136 } while (/* CONSTCOND */ 0) 137 138 #include <sys/param.h> 139 #include <sys/systm.h> 140 #include <sys/ioctl.h> 141 #include <sys/select.h> 142 #include <sys/poll.h> 143 #include <sys/tty.h> 144 #include <sys/proc.h> 145 #include <sys/conf.h> 146 #include <sys/file.h> 147 #include <sys/uio.h> 148 #include <sys/kernel.h> 149 #include <sys/syslog.h> 150 #include <sys/device.h> 151 #include <sys/malloc.h> 152 #include <sys/timepps.h> 153 #include <sys/vnode.h> 154 #include <sys/kauth.h> 155 #include <sys/intr.h> 156 157 #include <sys/bus.h> 158 159 #include <arm/imx/imxuartreg.h> 160 #include <arm/imx/imxuartvar.h> 161 #include <dev/cons.h> 162 163 #ifndef IMXUART_RING_SIZE 164 #define IMXUART_RING_SIZE 2048 165 #endif 166 167 int imxuspeed(long, struct imxuart_baudrate_ratio *); 168 int imxuparam(struct tty *, struct termios *); 169 void imxustart(struct tty *); 170 int imxuhwiflow(struct tty *, int); 171 172 void imxuart_shutdown(struct imxuart_softc *); 173 void imxuart_loadchannelregs(struct imxuart_softc *); 174 void imxuart_hwiflow(struct imxuart_softc *); 175 void imxuart_break(struct imxuart_softc *, bool); 176 void imxuart_modem(struct imxuart_softc *, int); 177 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 178 int imxuart_to_tiocm(struct imxuart_softc *); 179 void imxuart_iflush(struct imxuart_softc *); 180 int imxuintr(void *); 181 182 int imxuart_common_getc(dev_t, struct imxuart_regs *); 183 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 184 185 186 int imxuart_init(struct imxuart_regs *, int, tcflag_t, int); 187 188 int imxucngetc(dev_t); 189 void imxucnputc(dev_t, int); 190 void imxucnpollc(dev_t, int); 191 192 static void imxuintr_read(struct imxuart_softc *); 193 static void imxuintr_send(struct imxuart_softc *); 194 195 static void imxuart_enable_debugport(struct imxuart_softc *); 196 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 197 static void imxuart_control_rxint(struct imxuart_softc *, bool); 198 static void imxuart_control_txint(struct imxuart_softc *, bool); 199 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 200 201 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 202 203 #define integrate static inline 204 void imxusoft(void *); 205 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 206 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 207 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 208 integrate void imxuart_schedrx(struct imxuart_softc *); 209 void imxudiag(void *); 210 static void imxuart_load_speed(struct imxuart_softc *); 211 static void imxuart_load_params(struct imxuart_softc *); 212 integrate void imxuart_load_pendings(struct imxuart_softc *); 213 214 215 extern struct cfdriver imxuart_cd; 216 217 dev_type_open(imxuopen); 218 dev_type_close(imxuclose); 219 dev_type_read(imxuread); 220 dev_type_write(imxuwrite); 221 dev_type_ioctl(imxuioctl); 222 dev_type_stop(imxustop); 223 dev_type_tty(imxutty); 224 dev_type_poll(imxupoll); 225 226 const struct cdevsw imxcom_cdevsw = { 227 .d_open = imxuopen, 228 .d_close = imxuclose, 229 .d_read = imxuread, 230 .d_write = imxuwrite, 231 .d_ioctl = imxuioctl, 232 .d_stop = imxustop, 233 .d_tty = imxutty, 234 .d_poll = imxupoll, 235 .d_mmap = nommap, 236 .d_kqfilter = ttykqfilter, 237 .d_discard = nodiscard, 238 .d_flag = D_TTY 239 }; 240 241 /* 242 * Make this an option variable one can patch. 243 * But be warned: this must be a power of 2! 244 */ 245 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 246 247 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 248 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 249 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 250 251 static struct imxuart_regs imxuconsregs; 252 static int imxuconsattached; 253 static int imxuconsrate; 254 static tcflag_t imxuconscflag; 255 static struct cnm_state imxuart_cnm_state; 256 257 u_int imxuart_freq = IMXUART_FREQ; 258 u_int imxuart_freqdiv = IMXUART_FREQDIV; 259 260 #ifdef KGDB 261 #include <sys/kgdb.h> 262 263 static struct imxuart_regs imxu_kgdb_regs; 264 static int imxu_kgdb_attached; 265 266 int imxuart_kgdb_getc(void *); 267 void imxuart_kgdb_putc(void *, int); 268 #endif /* KGDB */ 269 270 #define IMXUART_DIALOUT_MASK TTDIALOUT_MASK 271 272 #define IMXUART_UNIT(x) TTUNIT(x) 273 #define IMXUART_DIALOUT(x) TTDIALOUT(x) 274 275 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 276 device_is_active((sc)->sc_dev)) 277 278 #define BR BUS_SPACE_BARRIER_READ 279 #define BW BUS_SPACE_BARRIER_WRITE 280 #define IMXUART_BARRIER(r, f) \ 281 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 282 283 284 void 285 imxuart_attach_common(device_t parent, device_t self, 286 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 287 { 288 struct imxuart_softc *sc = device_private(self); 289 struct imxuart_regs *regsp = &sc->sc_regs; 290 bus_space_handle_t ioh; 291 292 aprint_naive("\n"); 293 aprint_normal("\n"); 294 295 sc->sc_dev = self; 296 297 if (size <= 0) 298 size = IMX_UART_SIZE; 299 300 sc->sc_intr = intr; 301 regsp->ur_iot = iot; 302 regsp->ur_iobase = iobase; 303 304 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 305 return; 306 } 307 regsp->ur_ioh = ioh; 308 309 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 310 imxuintr, sc); 311 if (sc->sc_ih == NULL) { 312 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 313 return; 314 } 315 316 imxuart_attach_subr(sc); 317 } 318 319 void 320 imxuart_attach_subr(struct imxuart_softc *sc) 321 { 322 struct imxuart_regs *regsp = &sc->sc_regs; 323 bus_space_tag_t iot = regsp->ur_iot; 324 bus_space_handle_t ioh = regsp->ur_ioh; 325 struct tty *tp; 326 327 callout_init(&sc->sc_diag_callout, 0); 328 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 329 330 if (regsp->ur_iobase != imxuconsregs.ur_iobase) 331 imxuart_init(&sc->sc_regs, TTYDEF_SPEED, TTYDEF_CFLAG, false); 332 333 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 334 sc->sc_ucr2_d = sc->sc_ucr2; 335 336 /* Disable interrupts before configuring the device. */ 337 imxuart_disable_all_interrupts(sc); 338 339 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 340 imxuconsattached = 1; 341 342 /* Make sure the console is always "hardwired". */ 343 #if 0 344 delay(10000); /* wait for output to finish */ 345 #endif 346 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 347 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 348 } 349 350 351 tp = tty_alloc(); 352 tp->t_oproc = imxustart; 353 tp->t_param = imxuparam; 354 tp->t_hwiflow = imxuhwiflow; 355 356 sc->sc_tty = tp; 357 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 358 M_DEVBUF, M_WAITOK); 359 sc->sc_rbuf_size = imxuart_rbuf_size; 360 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 361 sc->sc_txfifo_len = 32; 362 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 363 * for this many characters */ 364 365 tty_attach(tp); 366 367 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 368 int maj; 369 370 /* locate the major number */ 371 maj = cdevsw_lookup_major(&imxcom_cdevsw); 372 373 if (maj != NODEVMAJOR) { 374 tp->t_dev = cn_tab->cn_dev = makedev(maj, 375 device_unit(sc->sc_dev)); 376 377 aprint_normal_dev(sc->sc_dev, "console\n"); 378 } 379 } 380 381 #ifdef KGDB 382 /* 383 * Allow kgdb to "take over" this port. If this is 384 * not the console and is the kgdb device, it has 385 * exclusive use. If it's the console _and_ the 386 * kgdb device, it doesn't. 387 */ 388 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 389 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 390 imxu_kgdb_attached = 1; 391 392 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 393 } 394 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 395 } 396 #endif 397 398 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 399 400 #ifdef RND_COM 401 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 402 RND_TYPE_TTY, RND_FLAG_COLLECT_TIME | 403 RND_FLAG_ESTIMATE_TIME); 404 #endif 405 406 /* if there are no enable/disable functions, assume the device 407 is always enabled */ 408 if (!sc->enable) 409 sc->enabled = 1; 410 411 imxuart_enable_debugport(sc); 412 413 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 414 415 //shutdownhook_establish(imxuart_shutdownhook, sc); 416 417 418 #if 0 419 { 420 uint32_t reg; 421 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 422 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 423 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 424 } 425 #endif 426 } 427 428 /* 429 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 430 * 431 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 432 */ 433 434 static long 435 gcd(long m, long n) 436 { 437 438 if (m < n) 439 return gcd(n, m); 440 441 if (n <= 0) 442 return m; 443 return gcd(n, m % n); 444 } 445 446 int 447 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 448 { 449 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 450 long b = 16 * speed; 451 long f = imxuart_freq / imxuart_freqdiv; 452 long d; 453 int err = 0; 454 455 /* reduce b/f */ 456 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 457 f /= d; 458 b /= d; 459 } 460 461 462 while (f > (1<<16) || b > (1<<16)) { 463 f /= 2; 464 b /= 2; 465 } 466 if (f <= 0 || b <= 0) 467 return -1; 468 469 #ifdef DIAGNOSTIC 470 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 471 (uint64_t)speed * 16 * f / b) - 1000; 472 if (err < 0) 473 err = -err; 474 #endif 475 476 ratio->numerator = b-1; 477 ratio->modulator = f-1; 478 479 if (err > IMXUART_TOLERANCE) 480 return -1; 481 482 return 0; 483 #undef divrnd 484 } 485 486 #ifdef IMXUART_DEBUG 487 int imxuart_debug = 0; 488 489 void imxustatus(struct imxuart_softc *, const char *); 490 void 491 imxustatus(struct imxuart_softc *sc, const char *str) 492 { 493 struct tty *tp = sc->sc_tty; 494 495 aprint_normal_dev(sc->sc_dev, 496 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 497 str, 498 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 499 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 500 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 501 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 502 sc->sc_tx_stopped ? '+' : '-'); 503 504 aprint_normal_dev(sc->sc_dev, 505 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 506 str, 507 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 508 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 509 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 510 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 511 sc->sc_rx_flags); 512 } 513 #endif 514 515 #if 0 516 int 517 imxuart_detach(device_t self, int flags) 518 { 519 struct imxuart_softc *sc = device_private(self); 520 int maj, mn; 521 522 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 523 return EBUSY; 524 525 /* locate the major number */ 526 maj = cdevsw_lookup_major(&imxcom_cdevsw); 527 528 /* Nuke the vnodes for any open instances. */ 529 mn = device_unit(self); 530 vdevgone(maj, mn, mn, VCHR); 531 532 mn |= IMXUART_DIALOUT_MASK; 533 vdevgone(maj, mn, mn, VCHR); 534 535 if (sc->sc_rbuf == NULL) { 536 /* 537 * Ring buffer allocation failed in the imxuart_attach_subr, 538 * only the tty is allocated, and nothing else. 539 */ 540 tty_free(sc->sc_tty); 541 return 0; 542 } 543 544 /* Free the receive buffer. */ 545 free(sc->sc_rbuf, M_DEVBUF); 546 547 /* Detach and free the tty. */ 548 tty_detach(sc->sc_tty); 549 tty_free(sc->sc_tty); 550 551 /* Unhook the soft interrupt handler. */ 552 softint_disestablish(sc->sc_si); 553 554 #ifdef RND_COM 555 /* Unhook the entropy source. */ 556 rnd_detach_source(&sc->rnd_source); 557 #endif 558 callout_destroy(&sc->sc_diag_callout); 559 560 /* Destroy the lock. */ 561 mutex_destroy(&sc->sc_lock); 562 563 return (0); 564 } 565 #endif 566 567 #ifdef notyet 568 int 569 imxuart_activate(device_t self, enum devact act) 570 { 571 struct imxuart_softc *sc = device_private(self); 572 int rv = 0; 573 574 switch (act) { 575 case DVACT_ACTIVATE: 576 rv = EOPNOTSUPP; 577 break; 578 579 case DVACT_DEACTIVATE: 580 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 581 rv = EBUSY; 582 break; 583 } 584 585 if (sc->disable != NULL && sc->enabled != 0) { 586 (*sc->disable)(sc); 587 sc->enabled = 0; 588 } 589 break; 590 } 591 592 return (rv); 593 } 594 #endif 595 596 void 597 imxuart_shutdown(struct imxuart_softc *sc) 598 { 599 struct tty *tp = sc->sc_tty; 600 601 mutex_spin_enter(&sc->sc_lock); 602 603 /* If we were asserting flow control, then deassert it. */ 604 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 605 imxuart_hwiflow(sc); 606 607 /* Clear any break condition set with TIOCSBRK. */ 608 imxuart_break(sc, false); 609 610 /* 611 * Hang up if necessary. Wait a bit, so the other side has time to 612 * notice even if we immediately open the port again. 613 * Avoid tsleeping above splhigh(). 614 */ 615 if (ISSET(tp->t_cflag, HUPCL)) { 616 imxuart_modem(sc, 0); 617 mutex_spin_exit(&sc->sc_lock); 618 /* XXX will only timeout */ 619 (void) kpause(ttclos, false, hz, NULL); 620 mutex_spin_enter(&sc->sc_lock); 621 } 622 623 /* Turn off interrupts. */ 624 imxuart_disable_all_interrupts(sc); 625 /* re-enable recv interrupt for console or kgdb port */ 626 imxuart_enable_debugport(sc); 627 628 mutex_spin_exit(&sc->sc_lock); 629 630 #ifdef notyet 631 if (sc->disable) { 632 #ifdef DIAGNOSTIC 633 if (!sc->enabled) 634 panic("imxuart_shutdown: not enabled?"); 635 #endif 636 (*sc->disable)(sc); 637 sc->enabled = 0; 638 } 639 #endif 640 } 641 642 int 643 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 644 { 645 struct imxuart_softc *sc; 646 struct tty *tp; 647 int s; 648 int error; 649 650 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 651 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 652 sc->sc_rbuf == NULL) 653 return (ENXIO); 654 655 if (!device_is_active(sc->sc_dev)) 656 return (ENXIO); 657 658 #ifdef KGDB 659 /* 660 * If this is the kgdb port, no other use is permitted. 661 */ 662 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 663 return (EBUSY); 664 #endif 665 666 tp = sc->sc_tty; 667 668 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 669 return (EBUSY); 670 671 s = spltty(); 672 673 /* 674 * Do the following iff this is a first open. 675 */ 676 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 677 struct termios t; 678 679 tp->t_dev = dev; 680 681 682 #ifdef notyet 683 if (sc->enable) { 684 if ((*sc->enable)(sc)) { 685 splx(s); 686 aprint_error_dev(sc->sc_dev, 687 "device enable failed\n"); 688 return (EIO); 689 } 690 sc->enabled = 1; 691 } 692 #endif 693 694 mutex_spin_enter(&sc->sc_lock); 695 696 imxuart_disable_all_interrupts(sc); 697 698 /* Fetch the current modem control status, needed later. */ 699 700 #ifdef IMXUART_PPS 701 /* Clear PPS capture state on first open. */ 702 mutex_spin_enter(&timecounter_lock); 703 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 704 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 705 pps_init(&sc->sc_pps_state); 706 mutex_spin_exit(&timecounter_lock); 707 #endif 708 709 mutex_spin_exit(&sc->sc_lock); 710 711 /* 712 * Initialize the termios status to the defaults. Add in the 713 * sticky bits from TIOCSFLAGS. 714 */ 715 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 716 t.c_ospeed = imxuconsrate; 717 t.c_cflag = imxuconscflag; 718 } else { 719 t.c_ospeed = TTYDEF_SPEED; 720 t.c_cflag = TTYDEF_CFLAG; 721 } 722 t.c_ispeed = t.c_ospeed; 723 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 724 SET(t.c_cflag, CLOCAL); 725 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 726 SET(t.c_cflag, CRTSCTS); 727 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 728 SET(t.c_cflag, MDMBUF); 729 /* Make sure imxuparam() will do something. */ 730 tp->t_ospeed = 0; 731 (void) imxuparam(tp, &t); 732 tp->t_iflag = TTYDEF_IFLAG; 733 tp->t_oflag = TTYDEF_OFLAG; 734 tp->t_lflag = TTYDEF_LFLAG; 735 ttychars(tp); 736 ttsetwater(tp); 737 738 mutex_spin_enter(&sc->sc_lock); 739 740 /* 741 * Turn on DTR. We must always do this, even if carrier is not 742 * present, because otherwise we'd have to use TIOCSDTR 743 * immediately after setting CLOCAL, which applications do not 744 * expect. We always assert DTR while the device is open 745 * unless explicitly requested to deassert it. 746 */ 747 imxuart_modem(sc, 1); 748 749 /* Clear the input ring, and unblock. */ 750 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 751 imxuart_iflush(sc); 752 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 753 imxuart_hwiflow(sc); 754 755 /* Turn on interrupts. */ 756 imxuart_control_rxint(sc, true); 757 758 #ifdef IMXUART_DEBUG 759 if (imxuart_debug) 760 imxustatus(sc, "imxuopen "); 761 #endif 762 763 mutex_spin_exit(&sc->sc_lock); 764 } 765 766 splx(s); 767 768 #if 0 769 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 770 #else 771 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 772 #endif 773 if (error) 774 goto bad; 775 776 error = (*tp->t_linesw->l_open)(dev, tp); 777 if (error) 778 goto bad; 779 780 return (0); 781 782 bad: 783 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 784 /* 785 * We failed to open the device, and nobody else had it opened. 786 * Clean up the state as appropriate. 787 */ 788 imxuart_shutdown(sc); 789 } 790 791 return (error); 792 } 793 794 int 795 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 796 { 797 struct imxuart_softc *sc = 798 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 799 struct tty *tp = sc->sc_tty; 800 801 /* XXX This is for cons.c. */ 802 if (!ISSET(tp->t_state, TS_ISOPEN)) 803 return (0); 804 805 (*tp->t_linesw->l_close)(tp, flag); 806 ttyclose(tp); 807 808 if (IMXUART_ISALIVE(sc) == 0) 809 return (0); 810 811 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 812 /* 813 * Although we got a last close, the device may still be in 814 * use; e.g. if this was the dialout node, and there are still 815 * processes waiting for carrier on the non-dialout node. 816 */ 817 imxuart_shutdown(sc); 818 } 819 820 return (0); 821 } 822 823 int 824 imxuread(dev_t dev, struct uio *uio, int flag) 825 { 826 struct imxuart_softc *sc = 827 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 828 struct tty *tp = sc->sc_tty; 829 830 if (IMXUART_ISALIVE(sc) == 0) 831 return (EIO); 832 833 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 834 } 835 836 int 837 imxuwrite(dev_t dev, struct uio *uio, int flag) 838 { 839 struct imxuart_softc *sc = 840 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 841 struct tty *tp = sc->sc_tty; 842 843 if (IMXUART_ISALIVE(sc) == 0) 844 return (EIO); 845 846 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 847 } 848 849 int 850 imxupoll(dev_t dev, int events, struct lwp *l) 851 { 852 struct imxuart_softc *sc = 853 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 854 struct tty *tp = sc->sc_tty; 855 856 if (IMXUART_ISALIVE(sc) == 0) 857 return (POLLHUP); 858 859 return ((*tp->t_linesw->l_poll)(tp, events, l)); 860 } 861 862 struct tty * 863 imxutty(dev_t dev) 864 { 865 struct imxuart_softc *sc = 866 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 867 struct tty *tp = sc->sc_tty; 868 869 return (tp); 870 } 871 872 int 873 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 874 { 875 struct imxuart_softc *sc; 876 struct tty *tp; 877 int error; 878 879 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 880 if (sc == NULL) 881 return ENXIO; 882 if (IMXUART_ISALIVE(sc) == 0) 883 return (EIO); 884 885 tp = sc->sc_tty; 886 887 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 888 if (error != EPASSTHROUGH) 889 return (error); 890 891 error = ttioctl(tp, cmd, data, flag, l); 892 if (error != EPASSTHROUGH) 893 return (error); 894 895 error = 0; 896 switch (cmd) { 897 case TIOCSFLAGS: 898 error = kauth_authorize_device_tty(l->l_cred, 899 KAUTH_DEVICE_TTY_PRIVSET, tp); 900 break; 901 default: 902 /* nothing */ 903 break; 904 } 905 if (error) { 906 return error; 907 } 908 909 mutex_spin_enter(&sc->sc_lock); 910 911 switch (cmd) { 912 case TIOCSBRK: 913 imxuart_break(sc, true); 914 break; 915 916 case TIOCCBRK: 917 imxuart_break(sc, false); 918 break; 919 920 case TIOCSDTR: 921 imxuart_modem(sc, 1); 922 break; 923 924 case TIOCCDTR: 925 imxuart_modem(sc, 0); 926 break; 927 928 case TIOCGFLAGS: 929 *(int *)data = sc->sc_swflags; 930 break; 931 932 case TIOCSFLAGS: 933 sc->sc_swflags = *(int *)data; 934 break; 935 936 case TIOCMSET: 937 case TIOCMBIS: 938 case TIOCMBIC: 939 tiocm_to_imxu(sc, cmd, *(int *)data); 940 break; 941 942 case TIOCMGET: 943 *(int *)data = imxuart_to_tiocm(sc); 944 break; 945 946 #ifdef notyet 947 case PPS_IOC_CREATE: 948 case PPS_IOC_DESTROY: 949 case PPS_IOC_GETPARAMS: 950 case PPS_IOC_SETPARAMS: 951 case PPS_IOC_GETCAP: 952 case PPS_IOC_FETCH: 953 #ifdef PPS_SYNC 954 case PPS_IOC_KCBIND: 955 #endif 956 mutex_spin_enter(&timecounter_lock); 957 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 958 mutex_spin_exit(&timecounter_lock); 959 break; 960 961 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 962 mutex_spin_enter(&timecounter_lock); 963 #ifndef PPS_TRAILING_EDGE 964 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 965 &sc->sc_pps_state.ppsinfo.assert_timestamp); 966 #else 967 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 968 &sc->sc_pps_state.ppsinfo.clear_timestamp); 969 #endif 970 mutex_spin_exit(&timecounter_lock); 971 break; 972 #endif 973 974 default: 975 error = EPASSTHROUGH; 976 break; 977 } 978 979 mutex_spin_exit(&sc->sc_lock); 980 981 #ifdef IMXUART_DEBUG 982 if (imxuart_debug) 983 imxustatus(sc, "imxuioctl "); 984 #endif 985 986 return (error); 987 } 988 989 integrate void 990 imxuart_schedrx(struct imxuart_softc *sc) 991 { 992 sc->sc_rx_ready = 1; 993 994 /* Wake up the poller. */ 995 softint_schedule(sc->sc_si); 996 } 997 998 void 999 imxuart_break(struct imxuart_softc *sc, bool onoff) 1000 { 1001 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1002 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1003 1004 if (onoff) 1005 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1006 else 1007 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1008 1009 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1010 } 1011 1012 void 1013 imxuart_modem(struct imxuart_softc *sc, int onoff) 1014 { 1015 #ifdef notyet 1016 if (sc->sc_mcr_dtr == 0) 1017 return; 1018 1019 if (onoff) 1020 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1021 else 1022 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1023 1024 if (!sc->sc_heldchange) { 1025 if (sc->sc_tx_busy) { 1026 sc->sc_heldtbc = sc->sc_tbc; 1027 sc->sc_tbc = 0; 1028 sc->sc_heldchange = 1; 1029 } else 1030 imxuart_loadchannelregs(sc); 1031 } 1032 #endif 1033 } 1034 1035 /* 1036 * RTS output is controlled by UCR2.CTS bit. 1037 * DTR output is controlled by UCR3.DSR bit. 1038 * (i.MX reference manual uses names in DCE mode) 1039 * 1040 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1041 */ 1042 void 1043 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1044 { 1045 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1046 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1047 1048 uint32_t ucr2 = sc->sc_ucr2_d; 1049 uint32_t ucr3 = sc->sc_ucr3; 1050 1051 uint32_t ucr2_mask = 0; 1052 uint32_t ucr3_mask = 0; 1053 1054 1055 if (ISSET(ttybits, TIOCM_DTR)) 1056 ucr3_mask = IMX_UCR3_DSR; 1057 if (ISSET(ttybits, TIOCM_RTS)) 1058 ucr2_mask = IMX_UCR2_CTS; 1059 1060 switch (how) { 1061 case TIOCMBIC: 1062 CLR(ucr2, ucr2_mask); 1063 CLR(ucr3, ucr3_mask); 1064 break; 1065 1066 case TIOCMBIS: 1067 SET(ucr2, ucr2_mask); 1068 SET(ucr3, ucr3_mask); 1069 break; 1070 1071 case TIOCMSET: 1072 CLR(ucr2, ucr2_mask); 1073 CLR(ucr3, ucr3_mask); 1074 SET(ucr2, ucr2_mask); 1075 SET(ucr3, ucr3_mask); 1076 break; 1077 } 1078 1079 if (ucr3 != sc->sc_ucr3) { 1080 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1081 sc->sc_ucr3 = ucr3; 1082 } 1083 1084 if (ucr2 == sc->sc_ucr2_d) 1085 return; 1086 1087 sc->sc_ucr2_d = ucr2; 1088 /* update CTS bit only */ 1089 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1090 (ucr2 & IMX_UCR2_CTS); 1091 1092 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1093 sc->sc_ucr2 = ucr2; 1094 } 1095 1096 int 1097 imxuart_to_tiocm(struct imxuart_softc *sc) 1098 { 1099 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1100 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1101 int ttybits = 0; 1102 uint32_t usr[2]; 1103 1104 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1105 SET(ttybits, TIOCM_DTR); 1106 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1107 SET(ttybits, TIOCM_RTS); 1108 1109 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1110 1111 if (ISSET(usr[0], IMX_USR1_RTSS)) 1112 SET(ttybits, TIOCM_CTS); 1113 1114 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1115 SET(ttybits, TIOCM_CD); 1116 1117 #if 0 1118 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1119 although there are bits in UART registers to detect delta of DSR. 1120 */ 1121 if (ISSET(imxubits, MSR_DSR)) 1122 SET(ttybits, TIOCM_DSR); 1123 #endif 1124 1125 if (ISSET(usr[1], IMX_USR2_RIIN)) 1126 SET(ttybits, TIOCM_RI); 1127 1128 1129 #ifdef notyet 1130 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1131 SET(ttybits, TIOCM_LE); 1132 #endif 1133 1134 return (ttybits); 1135 } 1136 1137 static uint32_t 1138 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1139 { 1140 uint32_t val = oldval; 1141 1142 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1143 1144 switch (cflag & CSIZE) { 1145 case CS5: 1146 case CS6: 1147 /* not suppreted. use 7-bits */ 1148 case CS7: 1149 break; 1150 case CS8: 1151 SET(val, IMX_UCR2_WS); 1152 break; 1153 } 1154 1155 1156 if (ISSET(cflag, PARENB)) { 1157 SET(val, IMX_UCR2_PREN); 1158 1159 /* odd parity */ 1160 if (!ISSET(cflag, PARODD)) 1161 SET(val, IMX_UCR2_PROE); 1162 } 1163 1164 if (ISSET(cflag, CSTOPB)) 1165 SET(val, IMX_UCR2_STPB); 1166 1167 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1168 1169 return val; 1170 } 1171 1172 int 1173 imxuparam(struct tty *tp, struct termios *t) 1174 { 1175 struct imxuart_softc *sc = 1176 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1177 struct imxuart_baudrate_ratio ratio; 1178 uint32_t ucr2; 1179 bool change_speed = tp->t_ospeed != t->c_ospeed; 1180 1181 if (IMXUART_ISALIVE(sc) == 0) 1182 return (EIO); 1183 1184 /* Check requested parameters. */ 1185 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1186 return (EINVAL); 1187 1188 /* 1189 * For the console, always force CLOCAL and !HUPCL, so that the port 1190 * is always active. 1191 */ 1192 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1193 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1194 SET(t->c_cflag, CLOCAL); 1195 CLR(t->c_cflag, HUPCL); 1196 } 1197 1198 /* 1199 * If there were no changes, don't do anything. This avoids dropping 1200 * input and improves performance when all we did was frob things like 1201 * VMIN and VTIME. 1202 */ 1203 if ( !change_speed && tp->t_cflag == t->c_cflag) 1204 return (0); 1205 1206 if (change_speed) { 1207 /* calculate baudrate modulator value */ 1208 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1209 return (EINVAL); 1210 sc->sc_ratio = ratio; 1211 } 1212 1213 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1214 1215 mutex_spin_enter(&sc->sc_lock); 1216 1217 #if 0 /* flow control stuff. not yet */ 1218 /* 1219 * If we're not in a mode that assumes a connection is present, then 1220 * ignore carrier changes. 1221 */ 1222 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1223 sc->sc_msr_dcd = 0; 1224 else 1225 sc->sc_msr_dcd = MSR_DCD; 1226 /* 1227 * Set the flow control pins depending on the current flow control 1228 * mode. 1229 */ 1230 if (ISSET(t->c_cflag, CRTSCTS)) { 1231 sc->sc_mcr_dtr = MCR_DTR; 1232 sc->sc_mcr_rts = MCR_RTS; 1233 sc->sc_msr_cts = MSR_CTS; 1234 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1235 } else if (ISSET(t->c_cflag, MDMBUF)) { 1236 /* 1237 * For DTR/DCD flow control, make sure we don't toggle DTR for 1238 * carrier detection. 1239 */ 1240 sc->sc_mcr_dtr = 0; 1241 sc->sc_mcr_rts = MCR_DTR; 1242 sc->sc_msr_cts = MSR_DCD; 1243 sc->sc_efr = 0; 1244 } else { 1245 /* 1246 * If no flow control, then always set RTS. This will make 1247 * the other side happy if it mistakenly thinks we're doing 1248 * RTS/CTS flow control. 1249 */ 1250 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1251 sc->sc_mcr_rts = 0; 1252 sc->sc_msr_cts = 0; 1253 sc->sc_efr = 0; 1254 if (ISSET(sc->sc_mcr, MCR_DTR)) 1255 SET(sc->sc_mcr, MCR_RTS); 1256 else 1257 CLR(sc->sc_mcr, MCR_RTS); 1258 } 1259 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1260 #endif 1261 1262 /* And copy to tty. */ 1263 tp->t_ispeed = t->c_ospeed; 1264 tp->t_ospeed = t->c_ospeed; 1265 tp->t_cflag = t->c_cflag; 1266 1267 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1268 /* noop */ 1269 } 1270 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1271 if (ucr2 != sc->sc_ucr2_d) { 1272 sc->sc_ucr2_d = ucr2; 1273 imxuart_load_params(sc); 1274 } 1275 if (change_speed) 1276 imxuart_load_speed(sc); 1277 } 1278 else { 1279 if (!sc->sc_pending) { 1280 sc->sc_heldtbc = sc->sc_tbc; 1281 sc->sc_tbc = 0; 1282 } 1283 sc->sc_pending |= 1284 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1285 (change_speed ? 0 : IMXUART_PEND_SPEED); 1286 sc->sc_ucr2_d = ucr2; 1287 } 1288 1289 if (!ISSET(t->c_cflag, CHWFLOW)) { 1290 /* Disable the high water mark. */ 1291 sc->sc_r_hiwat = 0; 1292 sc->sc_r_lowat = 0; 1293 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1294 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1295 imxuart_schedrx(sc); 1296 } 1297 if (ISSET(sc->sc_rx_flags, 1298 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1299 CLR(sc->sc_rx_flags, 1300 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1301 imxuart_hwiflow(sc); 1302 } 1303 } else { 1304 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1305 sc->sc_r_lowat = imxuart_rbuf_lowat; 1306 } 1307 1308 mutex_spin_exit(&sc->sc_lock); 1309 1310 #if 0 1311 /* 1312 * Update the tty layer's idea of the carrier bit, in case we changed 1313 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1314 * explicit request. 1315 */ 1316 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1317 #else 1318 /* XXX: always report that we have DCD */ 1319 (void) (*tp->t_linesw->l_modem)(tp, 1); 1320 #endif 1321 1322 #ifdef IMXUART_DEBUG 1323 if (imxuart_debug) 1324 imxustatus(sc, "imxuparam "); 1325 #endif 1326 1327 if (!ISSET(t->c_cflag, CHWFLOW)) { 1328 if (sc->sc_tx_stopped) { 1329 sc->sc_tx_stopped = 0; 1330 imxustart(tp); 1331 } 1332 } 1333 1334 return (0); 1335 } 1336 1337 void 1338 imxuart_iflush(struct imxuart_softc *sc) 1339 { 1340 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1341 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1342 #ifdef DIAGNOSTIC 1343 uint32_t reg = 0xffff; 1344 #endif 1345 int timo; 1346 1347 timo = 50000; 1348 /* flush any pending I/O */ 1349 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1350 && --timo) 1351 #ifdef DIAGNOSTIC 1352 reg = 1353 #else 1354 (void) 1355 #endif 1356 bus_space_read_4(iot, ioh, IMX_URXD); 1357 #ifdef DIAGNOSTIC 1358 if (!timo) 1359 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1360 #endif 1361 } 1362 1363 int 1364 imxuhwiflow(struct tty *tp, int block) 1365 { 1366 struct imxuart_softc *sc = 1367 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1368 1369 if (IMXUART_ISALIVE(sc) == 0) 1370 return (0); 1371 1372 #ifdef notyet 1373 if (sc->sc_mcr_rts == 0) 1374 return (0); 1375 #endif 1376 1377 mutex_spin_enter(&sc->sc_lock); 1378 1379 if (block) { 1380 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1381 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1382 imxuart_hwiflow(sc); 1383 } 1384 } else { 1385 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1386 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1387 imxuart_schedrx(sc); 1388 } 1389 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1390 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1391 imxuart_hwiflow(sc); 1392 } 1393 } 1394 1395 mutex_spin_exit(&sc->sc_lock); 1396 return (1); 1397 } 1398 1399 /* 1400 * (un)block input via hw flowcontrol 1401 */ 1402 void 1403 imxuart_hwiflow(struct imxuart_softc *sc) 1404 { 1405 #ifdef notyet 1406 struct imxuart_regs *regsp= &sc->sc_regs; 1407 1408 if (sc->sc_mcr_rts == 0) 1409 return; 1410 1411 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1412 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1413 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1414 } else { 1415 SET(sc->sc_mcr, sc->sc_mcr_rts); 1416 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1417 } 1418 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1419 #endif 1420 } 1421 1422 1423 void 1424 imxustart(struct tty *tp) 1425 { 1426 struct imxuart_softc *sc = 1427 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1428 int s; 1429 u_char *tba; 1430 int tbc; 1431 u_int n; 1432 u_int space; 1433 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1434 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1435 1436 if (IMXUART_ISALIVE(sc) == 0) 1437 return; 1438 1439 s = spltty(); 1440 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1441 goto out; 1442 if (sc->sc_tx_stopped) 1443 goto out; 1444 if (!ttypull(tp)) 1445 goto out; 1446 1447 /* Grab the first contiguous region of buffer space. */ 1448 tba = tp->t_outq.c_cf; 1449 tbc = ndqb(&tp->t_outq, 0); 1450 1451 mutex_spin_enter(&sc->sc_lock); 1452 1453 sc->sc_tba = tba; 1454 sc->sc_tbc = tbc; 1455 1456 SET(tp->t_state, TS_BUSY); 1457 sc->sc_tx_busy = 1; 1458 1459 space = imxuart_txfifo_space(sc); 1460 n = MIN(sc->sc_tbc, space); 1461 1462 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1463 sc->sc_tbc -= n; 1464 sc->sc_tba += n; 1465 1466 /* Enable transmit completion interrupts */ 1467 imxuart_control_txint(sc, true); 1468 1469 mutex_spin_exit(&sc->sc_lock); 1470 out: 1471 splx(s); 1472 return; 1473 } 1474 1475 /* 1476 * Stop output on a line. 1477 */ 1478 void 1479 imxustop(struct tty *tp, int flag) 1480 { 1481 struct imxuart_softc *sc = 1482 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1483 1484 mutex_spin_enter(&sc->sc_lock); 1485 if (ISSET(tp->t_state, TS_BUSY)) { 1486 /* Stop transmitting at the next chunk. */ 1487 sc->sc_tbc = 0; 1488 sc->sc_heldtbc = 0; 1489 if (!ISSET(tp->t_state, TS_TTSTOP)) 1490 SET(tp->t_state, TS_FLUSH); 1491 } 1492 mutex_spin_exit(&sc->sc_lock); 1493 } 1494 1495 void 1496 imxudiag(void *arg) 1497 { 1498 #ifdef notyet 1499 struct imxuart_softc *sc = arg; 1500 int overflows, floods; 1501 1502 mutex_spin_enter(&sc->sc_lock); 1503 overflows = sc->sc_overflows; 1504 sc->sc_overflows = 0; 1505 floods = sc->sc_floods; 1506 sc->sc_floods = 0; 1507 sc->sc_errors = 0; 1508 mutex_spin_exit(&sc->sc_lock); 1509 1510 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1511 device_xname(sc->sc_dev), 1512 overflows, overflows == 1 ? "" : "s", 1513 floods, floods == 1 ? "" : "s"); 1514 #endif 1515 } 1516 1517 integrate void 1518 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1519 { 1520 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1521 u_int cc, scc, outp; 1522 uint16_t data; 1523 u_int code; 1524 1525 scc = cc = IMXUART_RBUF_AVAIL(sc); 1526 1527 #if 0 1528 if (cc == imxuart_rbuf_size-1) { 1529 sc->sc_floods++; 1530 if (sc->sc_errors++ == 0) 1531 callout_reset(&sc->sc_diag_callout, 60 * hz, 1532 imxudiag, sc); 1533 } 1534 #endif 1535 1536 /* If not yet open, drop the entire buffer content here */ 1537 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1538 sc->sc_rbuf_out = sc->sc_rbuf_in; 1539 cc = 0; 1540 } 1541 1542 outp = sc->sc_rbuf_out; 1543 1544 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1545 1546 while (cc) { 1547 data = sc->sc_rbuf[outp]; 1548 code = data & IMX_URXD_RX_DATA; 1549 if (ISSET(data, ERRBITS)) { 1550 if (sc->sc_errors.err == 0) 1551 callout_reset(&sc->sc_diag_callout, 1552 60 * hz, imxudiag, sc); 1553 if (ISSET(data, IMX_URXD_OVRRUN)) 1554 sc->sc_errors.ovrrun++; 1555 if (ISSET(data, IMX_URXD_BRK)) { 1556 sc->sc_errors.brk++; 1557 SET(code, TTY_FE); 1558 } 1559 if (ISSET(data, IMX_URXD_FRMERR)) { 1560 sc->sc_errors.frmerr++; 1561 SET(code, TTY_FE); 1562 } 1563 if (ISSET(data, IMX_URXD_PRERR)) { 1564 sc->sc_errors.prerr++; 1565 SET(code, TTY_PE); 1566 } 1567 } 1568 if ((*rint)(code, tp) == -1) { 1569 /* 1570 * The line discipline's buffer is out of space. 1571 */ 1572 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1573 /* 1574 * We're either not using flow control, or the 1575 * line discipline didn't tell us to block for 1576 * some reason. Either way, we have no way to 1577 * know when there's more space available, so 1578 * just drop the rest of the data. 1579 */ 1580 sc->sc_rbuf_out = sc->sc_rbuf_in; 1581 cc = 0; 1582 } else { 1583 /* 1584 * Don't schedule any more receive processing 1585 * until the line discipline tells us there's 1586 * space available (through imxuhwiflow()). 1587 * Leave the rest of the data in the input 1588 * buffer. 1589 */ 1590 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1591 } 1592 break; 1593 } 1594 outp = IMXUART_RBUF_INC(sc, outp, 1); 1595 cc--; 1596 } 1597 1598 if (cc != scc) { 1599 sc->sc_rbuf_out = outp; 1600 mutex_spin_enter(&sc->sc_lock); 1601 1602 cc = IMXUART_RBUF_SPACE(sc); 1603 1604 /* Buffers should be ok again, release possible block. */ 1605 if (cc >= sc->sc_r_lowat) { 1606 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1607 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1608 imxuart_control_rxint(sc, true); 1609 } 1610 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1611 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1612 imxuart_hwiflow(sc); 1613 } 1614 } 1615 mutex_spin_exit(&sc->sc_lock); 1616 } 1617 } 1618 1619 integrate void 1620 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1621 { 1622 1623 CLR(tp->t_state, TS_BUSY); 1624 if (ISSET(tp->t_state, TS_FLUSH)) 1625 CLR(tp->t_state, TS_FLUSH); 1626 else 1627 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1628 (*tp->t_linesw->l_start)(tp); 1629 } 1630 1631 integrate void 1632 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1633 { 1634 #ifdef notyet 1635 u_char msr, delta; 1636 1637 mutex_spin_enter(&sc->sc_lock); 1638 msr = sc->sc_msr; 1639 delta = sc->sc_msr_delta; 1640 sc->sc_msr_delta = 0; 1641 mutex_spin_exit(&sc->sc_lock); 1642 1643 if (ISSET(delta, sc->sc_msr_dcd)) { 1644 /* 1645 * Inform the tty layer that carrier detect changed. 1646 */ 1647 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1648 } 1649 1650 if (ISSET(delta, sc->sc_msr_cts)) { 1651 /* Block or unblock output according to flow control. */ 1652 if (ISSET(msr, sc->sc_msr_cts)) { 1653 sc->sc_tx_stopped = 0; 1654 (*tp->t_linesw->l_start)(tp); 1655 } else { 1656 sc->sc_tx_stopped = 1; 1657 } 1658 } 1659 1660 #endif 1661 #ifdef IMXUART_DEBUG 1662 if (imxuart_debug) 1663 imxustatus(sc, "imxuart_stsoft"); 1664 #endif 1665 } 1666 1667 void 1668 imxusoft(void *arg) 1669 { 1670 struct imxuart_softc *sc = arg; 1671 struct tty *tp; 1672 1673 if (IMXUART_ISALIVE(sc) == 0) 1674 return; 1675 1676 tp = sc->sc_tty; 1677 1678 if (sc->sc_rx_ready) { 1679 sc->sc_rx_ready = 0; 1680 imxuart_rxsoft(sc, tp); 1681 } 1682 1683 if (sc->sc_st_check) { 1684 sc->sc_st_check = 0; 1685 imxuart_stsoft(sc, tp); 1686 } 1687 1688 if (sc->sc_tx_done) { 1689 sc->sc_tx_done = 0; 1690 imxuart_txsoft(sc, tp); 1691 } 1692 } 1693 1694 int 1695 imxuintr(void *arg) 1696 { 1697 struct imxuart_softc *sc = arg; 1698 uint32_t usr1, usr2; 1699 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1700 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1701 1702 1703 if (IMXUART_ISALIVE(sc) == 0) 1704 return (0); 1705 1706 mutex_spin_enter(&sc->sc_lock); 1707 1708 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1709 1710 1711 do { 1712 bus_space_write_4(iot, ioh, IMX_USR2, 1713 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1714 if (usr2 & IMX_USR2_BRCD) { 1715 /* Break signal detected */ 1716 int cn_trapped = 0; 1717 1718 cn_check_magic(sc->sc_tty->t_dev, 1719 CNC_BREAK, imxuart_cnm_state); 1720 if (cn_trapped) 1721 continue; 1722 #if defined(KGDB) && !defined(DDB) 1723 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1724 kgdb_connect(1); 1725 continue; 1726 } 1727 #endif 1728 } 1729 1730 if (usr2 & IMX_USR2_RDR) 1731 imxuintr_read(sc); 1732 1733 #ifdef IMXUART_PPS 1734 { 1735 u_char msr, delta; 1736 1737 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1738 delta = msr ^ sc->sc_msr; 1739 sc->sc_msr = msr; 1740 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1741 (delta & MSR_DCD)) { 1742 mutex_spin_enter(&timecounter_lock); 1743 pps_capture(&sc->sc_pps_state); 1744 pps_event(&sc->sc_pps_state, 1745 (msr & MSR_DCD) ? 1746 PPS_CAPTUREASSERT : 1747 PPS_CAPTURECLEAR); 1748 mutex_spin_exit(&timecounter_lock); 1749 } 1750 } 1751 #endif 1752 1753 #ifdef notyet 1754 /* 1755 * Process normal status changes 1756 */ 1757 if (ISSET(delta, sc->sc_msr_mask)) { 1758 SET(sc->sc_msr_delta, delta); 1759 1760 /* 1761 * Stop output immediately if we lose the output 1762 * flow control signal or carrier detect. 1763 */ 1764 if (ISSET(~msr, sc->sc_msr_mask)) { 1765 sc->sc_tbc = 0; 1766 sc->sc_heldtbc = 0; 1767 #ifdef IMXUART_DEBUG 1768 if (imxuart_debug) 1769 imxustatus(sc, "imxuintr "); 1770 #endif 1771 } 1772 1773 sc->sc_st_check = 1; 1774 } 1775 #endif 1776 1777 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1778 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1779 1780 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1781 if (usr1 & IMX_USR1_TRDY) 1782 imxuintr_send(sc); 1783 1784 mutex_spin_exit(&sc->sc_lock); 1785 1786 /* Wake up the poller. */ 1787 softint_schedule(sc->sc_si); 1788 1789 #ifdef RND_COM 1790 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1791 #endif 1792 1793 return (1); 1794 } 1795 1796 1797 /* 1798 * called when there is least one character in rxfifo 1799 * 1800 */ 1801 1802 static void 1803 imxuintr_read(struct imxuart_softc *sc) 1804 { 1805 int cc; 1806 uint16_t rd; 1807 uint32_t usr2; 1808 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1809 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1810 1811 cc = IMXUART_RBUF_SPACE(sc); 1812 1813 /* clear aging timer interrupt */ 1814 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1815 1816 while (cc > 0) { 1817 int cn_trapped = 0; 1818 1819 1820 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1821 bus_space_read_4(iot, ioh, IMX_URXD); 1822 1823 cn_check_magic(sc->sc_tty->t_dev, 1824 rd & 0xff, imxuart_cnm_state); 1825 1826 if (!cn_trapped) { 1827 #if defined(DDB) && defined(DDB_KEYCODE) 1828 /* 1829 * Temporary hack so that I can force the kernel into 1830 * the debugger via the serial port 1831 */ 1832 if ((rd & 0xff) == DDB_KEYCODE) 1833 Debugger(); 1834 #endif 1835 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1836 cc--; 1837 } 1838 1839 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1840 if (!(usr2 & IMX_USR2_RDR)) 1841 break; 1842 } 1843 1844 /* 1845 * Current string of incoming characters ended because 1846 * no more data was available or we ran out of space. 1847 * Schedule a receive event if any data was received. 1848 * If we're out of space, turn off receive interrupts. 1849 */ 1850 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1851 sc->sc_rx_ready = 1; 1852 /* 1853 * See if we are in danger of overflowing a buffer. If 1854 * so, use hardware flow control to ease the pressure. 1855 */ 1856 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1857 cc < sc->sc_r_hiwat) { 1858 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1859 imxuart_hwiflow(sc); 1860 } 1861 1862 /* 1863 * If we're out of space, disable receive interrupts 1864 * until the queue has drained a bit. 1865 */ 1866 if (!cc) { 1867 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1868 imxuart_control_rxint(sc, false); 1869 } 1870 } 1871 1872 1873 1874 /* 1875 * find how many chars we can put into tx-fifo 1876 */ 1877 static u_int 1878 imxuart_txfifo_space(struct imxuart_softc *sc) 1879 { 1880 uint32_t usr1, usr2; 1881 u_int cc; 1882 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1883 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1884 1885 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1886 if (usr2 & IMX_USR2_TXFE) 1887 cc = sc->sc_txfifo_len; 1888 else { 1889 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1890 if (usr1 & IMX_USR1_TRDY) 1891 cc = sc->sc_txfifo_thresh; 1892 else 1893 cc = 0; 1894 } 1895 1896 return cc; 1897 } 1898 1899 void 1900 imxuintr_send(struct imxuart_softc *sc) 1901 { 1902 uint32_t usr2; 1903 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1904 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1905 int cc = 0; 1906 1907 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1908 1909 if (sc->sc_pending) { 1910 if (usr2 & IMX_USR2_TXFE) { 1911 imxuart_load_pendings(sc); 1912 sc->sc_tbc = sc->sc_heldtbc; 1913 sc->sc_heldtbc = 0; 1914 } 1915 else { 1916 /* wait for TX fifo empty */ 1917 imxuart_control_txint(sc, true); 1918 return; 1919 } 1920 } 1921 1922 cc = imxuart_txfifo_space(sc); 1923 cc = MIN(cc, sc->sc_tbc); 1924 1925 if (cc > 0) { 1926 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 1927 sc->sc_tbc -= cc; 1928 sc->sc_tba += cc; 1929 } 1930 1931 if (sc->sc_tbc > 0) 1932 imxuart_control_txint(sc, true); 1933 else { 1934 /* no more chars to send. 1935 we don't need tx interrupt any more. */ 1936 imxuart_control_txint(sc, false); 1937 if (sc->sc_tx_busy) { 1938 sc->sc_tx_busy = 0; 1939 sc->sc_tx_done = 1; 1940 } 1941 } 1942 } 1943 1944 static void 1945 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 1946 { 1947 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1948 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1949 1950 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 1951 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 1952 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 1953 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 1954 1955 1956 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 1957 } 1958 1959 static void 1960 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 1961 { 1962 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1963 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1964 uint32_t ucr1, ucr2; 1965 1966 ucr1 = sc->sc_ucr1; 1967 ucr2 = sc->sc_ucr2; 1968 1969 if (enable) { 1970 ucr1 |= IMX_UCR1_RRDYEN; 1971 ucr2 |= IMX_UCR2_ATEN; 1972 } 1973 else { 1974 ucr1 &= ~IMX_UCR1_RRDYEN; 1975 ucr2 &= ~IMX_UCR2_ATEN; 1976 } 1977 1978 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 1979 sc->sc_ucr1 = ucr1; 1980 sc->sc_ucr2 = ucr2; 1981 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 1982 } 1983 } 1984 1985 static void 1986 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 1987 { 1988 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1989 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1990 uint32_t ucr1; 1991 uint32_t mask; 1992 1993 /* if parameter change is pending, get interrupt when Tx fifo 1994 is completely empty. otherwise, get interrupt when txfifo 1995 has less characters than threshold */ 1996 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 1997 1998 ucr1 = sc->sc_ucr1; 1999 2000 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2001 if (enable) 2002 SET(ucr1, mask); 2003 2004 if (ucr1 != sc->sc_ucr1) { 2005 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2006 sc->sc_ucr1 = ucr1; 2007 } 2008 } 2009 2010 2011 static void 2012 imxuart_load_params(struct imxuart_softc *sc) 2013 { 2014 uint32_t ucr2; 2015 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2016 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2017 2018 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2019 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2020 2021 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2022 sc->sc_ucr2 = ucr2; 2023 } 2024 2025 static void 2026 imxuart_load_speed(struct imxuart_softc *sc) 2027 { 2028 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2029 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2030 int n, rfdiv, ufcr; 2031 2032 #ifdef notyet 2033 /* 2034 * Set the FIFO threshold based on the receive speed. 2035 * 2036 * * If it's a low speed, it's probably a mouse or some other 2037 * interactive device, so set the threshold low. 2038 * * If it's a high speed, trim the trigger level down to prevent 2039 * overflows. 2040 * * Otherwise set it a bit higher. 2041 */ 2042 if (t->c_ospeed <= 1200) 2043 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2044 else if (t->c_ospeed <= 38400) 2045 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2046 else 2047 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2048 #endif 2049 2050 n = 32 - sc->sc_txfifo_thresh; 2051 n = MAX(2, n); 2052 2053 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2054 2055 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2056 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2057 (16 << IMX_UFCR_RXTL_SHIFT); 2058 2059 /* keep DCE/DTE bit */ 2060 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2061 2062 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2063 2064 /* UBIR must updated before UBMR */ 2065 bus_space_write_4(iot, ioh, 2066 IMX_UBIR, sc->sc_ratio.numerator); 2067 bus_space_write_4(iot, ioh, 2068 IMX_UBMR, sc->sc_ratio.modulator); 2069 2070 2071 } 2072 2073 2074 static void 2075 imxuart_load_pendings(struct imxuart_softc *sc) 2076 { 2077 if (sc->sc_pending & IMXUART_PEND_PARAM) 2078 imxuart_load_params(sc); 2079 if (sc->sc_pending & IMXUART_PEND_SPEED) 2080 imxuart_load_speed(sc); 2081 sc->sc_pending = 0; 2082 } 2083 2084 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2085 2086 /* 2087 * The following functions are polled getc and putc routines, shared 2088 * by the console and kgdb glue. 2089 * 2090 * The read-ahead code is so that you can detect pending in-band 2091 * cn_magic in polled mode while doing output rather than having to 2092 * wait until the kernel decides it needs input. 2093 */ 2094 2095 #define READAHEAD_RING_LEN 16 2096 static int imxuart_readahead[READAHEAD_RING_LEN]; 2097 static int imxuart_readahead_in = 0; 2098 static int imxuart_readahead_out = 0; 2099 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2100 #define READAHEAD_IS_FULL() \ 2101 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2102 2103 int 2104 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2105 { 2106 int s = splserial(); 2107 u_char c; 2108 bus_space_tag_t iot = regsp->ur_iot; 2109 bus_space_handle_t ioh = regsp->ur_ioh; 2110 uint32_t usr2; 2111 2112 /* got a character from reading things earlier */ 2113 if (imxuart_readahead_in != imxuart_readahead_out) { 2114 2115 c = imxuart_readahead[imxuart_readahead_out]; 2116 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2117 (READAHEAD_RING_LEN-1); 2118 splx(s); 2119 return (c); 2120 } 2121 2122 /* block until a character becomes available */ 2123 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2124 ; 2125 2126 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2127 2128 { 2129 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 2130 #ifdef DDB 2131 extern int db_active; 2132 if (!db_active) 2133 #endif 2134 cn_check_magic(dev, c, imxuart_cnm_state); 2135 } 2136 splx(s); 2137 return (c); 2138 } 2139 2140 void 2141 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2142 { 2143 int s = splserial(); 2144 int cin, timo; 2145 bus_space_tag_t iot = regsp->ur_iot; 2146 bus_space_handle_t ioh = regsp->ur_ioh; 2147 uint32_t usr2; 2148 2149 if (!READAHEAD_IS_FULL() && 2150 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2151 2152 int __attribute__((__unused__))cn_trapped = 0; 2153 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2154 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2155 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2156 (READAHEAD_RING_LEN-1); 2157 } 2158 2159 /* wait for any pending transmission to finish */ 2160 timo = 150000; 2161 do { 2162 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2163 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2164 break; 2165 } 2166 } while(--timo > 0); 2167 2168 IMXUART_BARRIER(regsp, BR | BW); 2169 2170 splx(s); 2171 } 2172 #endif /* defined(IMXUARTCONSOLE) || defined(KGDB) */ 2173 2174 /* 2175 * Initialize UART 2176 */ 2177 int 2178 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag, int domap) 2179 { 2180 struct imxuart_baudrate_ratio ratio; 2181 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2182 uint32_t ufcr; 2183 int error; 2184 2185 if (domap && (error = bus_space_map(regsp->ur_iot, regsp->ur_iobase, 2186 IMX_UART_SIZE, 0, ®sp->ur_ioh)) != 0) 2187 return error; 2188 2189 if (imxuspeed(rate, &ratio) < 0) 2190 return EINVAL; 2191 2192 /* UBIR must updated before UBMR */ 2193 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2194 IMX_UBIR, ratio.numerator); 2195 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2196 IMX_UBMR, ratio.modulator); 2197 2198 2199 /* XXX: DTREN, DPEC */ 2200 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2201 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2202 2203 ufcr = (8 << IMX_UFCR_TXTL_SHIFT) | (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2204 (1 << IMX_UFCR_RXTL_SHIFT); 2205 /* XXX: keep DCE/DTE bit */ 2206 ufcr |= bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR) & 2207 IMX_UFCR_DCEDTE; 2208 2209 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2210 2211 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2212 imxuart_freq / imxuart_freqdiv / 1000); 2213 2214 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2215 IMX_UCR2_IRTS| 2216 IMX_UCR2_CTSC| 2217 IMX_UCR2_WS|IMX_UCR2_TXEN| 2218 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2219 /* clear status registers */ 2220 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2221 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2222 2223 2224 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2225 IMX_UCR1_UARTEN); 2226 2227 return (0); 2228 } 2229 2230 2231 #ifdef IMXUARTCONSOLE 2232 /* 2233 * Following are all routines needed for UART to act as console 2234 */ 2235 struct consdev imxucons = { 2236 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2237 NODEV, CN_NORMAL 2238 }; 2239 2240 2241 int 2242 imxuart_cnattach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2243 tcflag_t cflag) 2244 { 2245 struct imxuart_regs regs; 2246 int res; 2247 2248 regs.ur_iot = iot; 2249 regs.ur_iobase = iobase; 2250 2251 res = imxuart_init(®s, rate, cflag, true); 2252 if (res) 2253 return (res); 2254 2255 cn_tab = &imxucons; 2256 cn_init_magic(&imxuart_cnm_state); 2257 cn_set_magic("\047\001"); /* default magic is BREAK */ 2258 2259 imxuconsrate = rate; 2260 imxuconscflag = cflag; 2261 2262 imxuconsregs = regs; 2263 2264 return 0; 2265 } 2266 2267 int 2268 imxucngetc(dev_t dev) 2269 { 2270 return (imxuart_common_getc(dev, &imxuconsregs)); 2271 } 2272 2273 /* 2274 * Console kernel output character routine. 2275 */ 2276 void 2277 imxucnputc(dev_t dev, int c) 2278 { 2279 imxuart_common_putc(dev, &imxuconsregs, c); 2280 } 2281 2282 void 2283 imxucnpollc(dev_t dev, int on) 2284 { 2285 2286 imxuart_readahead_in = 0; 2287 imxuart_readahead_out = 0; 2288 } 2289 2290 #endif /* IMXUARTCONSOLE */ 2291 2292 #ifdef KGDB 2293 int 2294 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2295 tcflag_t cflag) 2296 { 2297 int res; 2298 2299 if (iot == imxuconsregs.ur_iot && 2300 iobase == imxuconsregs.ur_iobase) { 2301 #if !defined(DDB) 2302 return (EBUSY); /* cannot share with console */ 2303 #else 2304 imxu_kgdb_regs.ur_iot = iot; 2305 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2306 imxu_kgdb_regs.ur_iobase = iobase; 2307 #endif 2308 } else { 2309 imxu_kgdb_regs.ur_iot = iot; 2310 imxu_kgdb_regs.ur_iobase = iobase; 2311 2312 res = imxuart_init(&imxu_kgdb_regs, rate, cflag, true); 2313 if (res) 2314 return (res); 2315 2316 /* 2317 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2318 * expects this to be initialized 2319 */ 2320 cn_init_magic(&imxuart_cnm_state); 2321 cn_set_magic("\047\001"); 2322 } 2323 2324 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2325 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2326 2327 return (0); 2328 } 2329 2330 /* ARGSUSED */ 2331 int 2332 imxuart_kgdb_getc(void *arg) 2333 { 2334 struct imxuart_regs *regs = arg; 2335 2336 return (imxuart_common_getc(NODEV, regs)); 2337 } 2338 2339 /* ARGSUSED */ 2340 void 2341 imxuart_kgdb_putc(void *arg, int c) 2342 { 2343 struct imxuart_regs *regs = arg; 2344 2345 imxuart_common_putc(NODEV, regs, c); 2346 } 2347 #endif /* KGDB */ 2348 2349 /* helper function to identify the imxu ports used by 2350 console or KGDB (and not yet autoconf attached) */ 2351 int 2352 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2353 { 2354 bus_space_handle_t help; 2355 2356 if (!imxuconsattached && 2357 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2358 help = imxuconsregs.ur_ioh; 2359 #ifdef KGDB 2360 else if (!imxu_kgdb_attached && 2361 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2362 help = imxu_kgdb_regs.ur_ioh; 2363 #endif 2364 else 2365 return (0); 2366 2367 if (ioh) 2368 *ioh = help; 2369 return (1); 2370 } 2371 2372 #ifdef notyet 2373 2374 bool 2375 imxuart_cleanup(device_t self, int how) 2376 { 2377 /* 2378 * this routine exists to serve as a shutdown hook for systems that 2379 * have firmware which doesn't interact properly with a imxuart device in 2380 * FIFO mode. 2381 */ 2382 struct imxuart_softc *sc = device_private(self); 2383 2384 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2385 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2386 2387 return true; 2388 } 2389 #endif 2390 2391 #ifdef notyet 2392 bool 2393 imxuart_suspend(device_t self PMF_FN_ARGS) 2394 { 2395 struct imxuart_softc *sc = device_private(self); 2396 2397 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2398 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2399 2400 return true; 2401 } 2402 #endif 2403 2404 #ifdef notyet 2405 bool 2406 imxuart_resume(device_t self PMF_FN_ARGS) 2407 { 2408 struct imxuart_softc *sc = device_private(self); 2409 2410 mutex_spin_enter(&sc->sc_lock); 2411 imxuart_loadchannelregs(sc); 2412 mutex_spin_exit(&sc->sc_lock); 2413 2414 return true; 2415 } 2416 #endif 2417 2418 static void 2419 imxuart_enable_debugport(struct imxuart_softc *sc) 2420 { 2421 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2422 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2423 2424 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2425 2426 /* Turn on line break interrupt, set carrier. */ 2427 2428 sc->sc_ucr3 |= IMX_UCR3_DSR; 2429 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2430 2431 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2432 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2433 2434 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2435 IMX_UCR2_CTS; 2436 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2437 2438 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2439 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2440 } 2441 } 2442 2443 2444 void 2445 imxuart_set_frequency(u_int freq, u_int div) 2446 { 2447 imxuart_freq = freq; 2448 imxuart_freqdiv = div; 2449 } 2450