xref: /netbsd-src/sys/arch/arm/imx/imxcspireg.h (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55)
1 /*	$NetBSD: imxcspireg.h,v 1.1 2014/03/22 09:28:08 hkenken Exp $	*/
2 
3 /*
4  * Copyright (c) 2014  Genetec Corporation.  All rights reserved.
5  * Written by Hashimoto Kenichi for Genetec Corporation.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #ifndef	_ARM_IMX_IMXCSPIREG_H_
30 #define	_ARM_IMX_IMXCSPIREG_H_
31 
32 #define	CSPI_RXDATA		0x00
33 #define	CSPI_TXDATA		0x04
34 #define	CSPI_CONREG		0x08
35 #ifdef IMX51
36 #define	 CSPI_CON_CS		__BITS(13, 12)
37 #define	 CSPI_CON_DRCTL		__BITS( 9,  8)
38 #define	 CSPI_CON_BITCOUNT	__BITS(31, 20)
39 #else
40 #define	 CSPI_CON_CS		__BITS(25, 24)
41 #define	 CSPI_CON_DRCTL		__BITS(21, 20)
42 #define	 CSPI_CON_BITCOUNT	__BITS(12,  8)
43 #endif
44 #define	 CSPI_CON_DIV		__BITS(18, 16)
45 #define	 CSPI_CON_SSPOL		__BIT(7)	/* SPI SS Polarity Select */
46 #define	 CSPI_CON_SSCTL		__BIT(6)	/* In master mode, this bit
47 						 * selects the output wave form
48 						 * for the SS signal.
49 						 */
50 #define	 CSPI_CON_PHA		__BIT(5)	/* PHA */
51 #define	 CSPI_CON_POL		__BIT(4)	/* POL */
52 #define	 CSPI_CON_SMC		__BIT(3)	/* SMC */
53 #define	 CSPI_CON_XCH		__BIT(2)	/* XCH */
54 #define	 CSPI_CON_MODE		__BIT(1)	/* MODE */
55 #define	 CSPI_CON_ENABLE	__BIT(0)	/* EN */
56 #define	CSPI_INTREG		0x0c
57 #define	 CSPI_INTR_ALL_EN	0x000001ff	/* All Intarruption Enabled */
58 #ifdef IMX51
59 #define	 CSPI_INTR_TC_EN	__BIT(7)	/* TX Complete */
60 #else
61 #define	 CSPI_INTR_TC_EN	__BIT(8)	/* TX Complete */
62 #define	 CSPI_INTR_BO_EN	__BIT(7)	/* Bit Counter Overflow */
63 #endif
64 #define	 CSPI_INTR_RO_EN	__BIT(6)	/* RXFIFO Overflow */
65 #define	 CSPI_INTR_RF_EN	__BIT(5)	/* RXFIFO Full */
66 #define	 CSPI_INTR_RH_EN	__BIT(4)	/* RXFIFO Half Full */
67 #define	 CSPI_INTR_RR_EN	__BIT(3)	/* RXFIFO Ready */
68 #define	 CSPI_INTR_TF_EN	__BIT(2)	/* TXFIFO Full */
69 #define	 CSPI_INTR_TH_EN	__BIT(1)	/* TXFIFO Half Empty */
70 #define	 CSPI_INTR_TE_EN	__BIT(0)	/* TXFIFO Empty */
71 #define	CSPI_DMAREG		0x10
72 #define	CSPI_STATREG		0x14
73 #ifdef IMX51
74 #define	 CSPI_STAT_CLR_TC	__BIT(7)	/* Clear TC of status register */
75 #define  CSPI_STAT_CLR		CSPI_STAT_CLR_TC
76 #else
77 #define	 CSPI_STAT_CLR_TC	__BIT(8)	/* Clear TC of status register */
78 #define	 CSPI_STAT_CLR_BO	__BIT(7)	/* Clear BO of status register */
79 #define  CSPI_STAT_CLR		(CSPI_STAT_CLR_TC | CSPI_STAT_CLR_BO)
80 #endif
81 #define	 CSPI_STAT_RO		__BIT(6)	/* RXFIFO Overflow */
82 #define	 CSPI_STAT_RF		__BIT(5)	/* RXFIFO Full */
83 #define	 CSPI_STAT_RH		__BIT(4)	/* RXFIFO Half Full */
84 #define	 CSPI_STAT_RR		__BIT(3)	/* RXFIFO Ready */
85 #define	 CSPI_STAT_TF		__BIT(2)	/* TXFIFO Full */
86 #define	 CSPI_STAT_TH		__BIT(1)	/* TXFIFO Half Empty */
87 #define	 CSPI_STAT_TE		__BIT(0)	/* TXFIFO Empty */
88 #define	CSPI_PERIODREG		0x18
89 #define	CSPI_TESTREG		0x1c
90 
91 #define SPI_SIZE		0x100
92 
93 #endif	/* _ARM_IMX_IMXCSPIREG_H_ */
94