1 /* $NetBSD: imxclock.c,v 1.9 2020/05/29 12:30:38 rin Exp $ */ 2 /* 3 * Copyright (c) 2009, 2010 Genetec corp. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec corp. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * common part for i.MX31 and i.MX51 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: imxclock.c,v 1.9 2020/05/29 12:30:38 rin Exp $"); 34 35 #include "opt_imx.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/evcnt.h> 41 #include <sys/atomic.h> 42 #include <sys/time.h> 43 #include <sys/timetc.h> 44 45 #include <sys/types.h> 46 #include <sys/device.h> 47 48 #include <machine/intr.h> 49 #include <sys/bus.h> 50 51 #include <arm/cpu.h> 52 #include <arm/armreg.h> 53 #include <arm/cpufunc.h> 54 55 #include <arm/imx/imxclockvar.h> 56 #include <arm/imx/imxepitreg.h> 57 58 static u_int imx_epit_get_timecount(struct timecounter *); 59 static int imxclock_intr(void *); 60 61 static struct timecounter imx_epit_timecounter = { 62 .tc_get_timecount = imx_epit_get_timecount, 63 .tc_counter_mask = 0xffffffff, 64 .tc_name = "epit", 65 .tc_quality = 100, 66 }; 67 68 static volatile uint32_t imxclock_base; 69 struct imxclock_softc *imxclock = NULL; 70 71 void 72 cpu_initclocks(void) 73 { 74 uint32_t reg; 75 u_int freq; 76 77 if (epit1_sc != NULL) 78 imxclock = epit1_sc; 79 else if (epit2_sc != NULL) 80 imxclock = epit2_sc; 81 else 82 panic("%s: driver has not been initialized!", __FUNCTION__); 83 84 freq = imxclock_get_timerfreq(imxclock); 85 imx_epit_timecounter.tc_frequency = freq; 86 tc_init(&imx_epit_timecounter); 87 88 aprint_verbose_dev(imxclock->sc_dev, 89 "timer clock frequency %d\n", freq); 90 91 imxclock->sc_reload_value = freq / hz - 1; 92 93 /* stop timers */ 94 bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITCR, 0); 95 96 aprint_normal("clock: hz=%d stathz = %d\n", hz, stathz); 97 98 bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITLR, 99 imxclock->sc_reload_value); 100 bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITCMPR, 0); 101 102 reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | imxclock->sc_clksrc; 103 bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, 104 EPIT_EPITCR, reg); 105 reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN | 106 EPITCR_STOPEN; 107 bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, 108 EPIT_EPITCR, reg); 109 110 imxclock->sc_ih = intr_establish(imxclock->sc_intr, IPL_CLOCK, 111 IST_LEVEL, imxclock_intr, NULL); 112 } 113 114 void 115 setstatclockrate(int schz) 116 { 117 } 118 119 static int 120 imxclock_intr(void *arg) 121 { 122 struct imxclock_softc *sc = imxclock; 123 124 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPIT_EPITSR, 1); 125 atomic_add_32(&imxclock_base, sc->sc_reload_value); 126 127 hardclock((struct clockframe *)arg); 128 129 return 1; 130 } 131 132 u_int 133 imx_epit_get_timecount(struct timecounter *tc) 134 { 135 uint32_t counter; 136 uint32_t base; 137 u_int oldirqstate; 138 139 oldirqstate = disable_interrupts(I32_bit); 140 counter = bus_space_read_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITCNT); 141 base = imxclock_base; 142 restore_interrupts(oldirqstate); 143 144 return base - counter; 145 } 146