1 /* $NetBSD: imx51reg.h,v 1.2 2010/11/30 13:05:27 bsh Exp $ */ 2 /*- 3 * Copyright (c) 2007 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_IMX_IMX51REG_H_ 32 #define _ARM_IMX_IMX51REG_H_ 33 34 #define BOOTROM_BASE 0x00000000 35 #define BOOTROM_SIZE 0x9000 36 37 #define SCCRAM_BASE 0x1ffe0000 38 #define SCCRAM_SIZE 0x20000 39 40 #define GPUMEM_BASE 0x20000000 41 #define GPUMEM_SIZE 0x20000 42 43 #define GPU_BASE 0x30000000 44 #define GPU_SIZE 0x10000000 45 46 /* LCD controller */ 47 #define IPUEX_BASE 0x40000000 48 #define IPUEX_SIZE 0x20000000 49 50 #define DEBUGROM_BASE 0x60000000 51 #define DEBUGROM_SIZE 0x1000 52 53 #define ESDHC1_BASE 0x70004000 54 #define ESDHC2_BASE 0x70008000 55 #define ESDHC3_BASE 0x70020000 56 #define ESDHC4_BASE 0x70024000 57 #define ESDHC_SIZE 0x4000 58 59 #define UART1_BASE 0x73fbc000 60 #define UART2_BASE 0x73fc0000 61 #define UART3_BASE 0x7000c000 62 /* register definitions in imxuartreg.h */ 63 64 #define ECSPI1_BASE 0x70010000 65 #define ECSPI2_BASE 0x83fac000 66 #define ECSPI_SIZE 0x4000 67 68 #define SSI1_BASE 0x83fcc000 69 #define SSI2_BASE 0x70014000 70 #define SSI3_BASE 0x83fe8000 71 /* register definitions in imxssireg.h */ 72 73 #define SPDIF_BASE 0x70028000 74 #define SPDIF_SIZE 0x4000 75 76 #define PATA_UDMA_BASE 0x70030000 77 #define PATA_UDMA_SIZE 0x4000 78 #define PATA_PIO_BASE 0x83fe0000 79 #define PATA_PIO_SIZE 0x4000 80 81 #define SLM_BASE 0x70034000 82 #define SLM_SIZE 0x4000 83 84 #define HSI2C_BASE 0x70038000 85 #define HSI2C_SIZE 0x4000 86 87 #define SPBA_BASE 0x7003c000 88 #define SPBA_SIZE 0x4000 89 90 #define USBOH3_BASE 0x73f80000 91 #define USBOH3_PL301_BASE 0x73fc4000 92 #define USBOH3_EHCI_SIZE 0x200 93 #define USBOH3_OTG 0x000 94 #define USBOH3_EHCI(n) (USBOH3_EHCI_SIZE*(n)) /* n=1,2,3 */ 95 96 /* USB_CTRL register */ 97 #define USBOH3_USBCTRL 0x800 98 #define USBCTRL_OWIR __BIT(31) /* OTG Wakeup interrupt request */ 99 #define USBCTRL_OSIC_SHIFT 29 100 #define USBCTRL_OSIC __BITS(29,30) /* OTG Serial interface configuration */ 101 #define USBCTRL_OUIE __BIT(28) /* OTG Wake-up interrupt enable */ 102 #define USBCTRL_OBPAL __BITS(25,26) /* OTG Bypass value */ 103 #define USBCTRL_OPM __BIT(24) /* OTG Power Mask */ 104 #define USBCTRL_ICVOL __BIT(23) /* Host1 IC_USB voltage status */ 105 #define USBCTRL_ICTPIE __BIT(19) /* IC USB TP interrupt enable */ 106 #define USBCTRL_UBPCKE __BIT(18) /* Bypass clock enable */ 107 #define USBCTRL_H1TCKOEN __BIT(17) /* Host1 ULPO PHY clock enable */ 108 #define USBCTRL_ICTPC __BIT(16) /* Clear IC TP interrupt flag */ 109 #define USBCTRL_H1WIR __BIT(15) /* Host1 wakeup interrupt request */ 110 #define USBCTRL_H1STC_SHIFT 13 111 #define USBCTRL_H1SIC __BITS(13,14) /* Host1 serial interface config */ 112 #define USBCTRL_H1UIE __BIT(12) /* Host1 ILPI interrupt enable */ 113 #define USBCTRL_H1WIE __BIT(11) /* Host1 wakeup interrupt enable */ 114 #define USBCTRL_H1BPVAL __BITS(9,10) /* Host1 bypass value */ 115 #define USBCTRL_H1PM __BIT(8) /* Host1 power mask */ 116 #define USBCTRL_OHSTLL __BIT(7) /* OTG ULPI TLL enable */ 117 #define USBCTRL_H1HSTLL __BIT(6) /* Host1 ULPI TLL enable */ 118 #define USBCTRL_H1DISFSTTL __BIT(4) /* Host1 serial TLL disable */ 119 #define USBCTRL_OTCKOEN __BIT(1) /* OTG ULPI PHY clock enable */ 120 #define USBCTRL_BPE __BIT(0) /* Bypass enable */ 121 122 #define USBOH3_OTGMIRROR 0x804 123 #define USBOH3_PHYCTRL0 0x808 124 #define PHYCTRL0_VLOAD __BIT(31) 125 #define PHYCTRL0_VCONTROL __BITS(27,30) 126 #define PHYCTRL0_CONF2 __BIT(26) 127 #define PHYCTRL0_CONF3 __BIT(25) 128 #define PHYCTRL0_CHGRDETEN __BIT(24) 129 #define PHYCTRL0_CHGRDETON __BIT(23) 130 #define PHYCTRL0_VSTATUS __BITS(15,22) 131 #define PHYCTRL0_SUSPENDM __BIT(12) 132 #define PHYCTRL0_RESET __BIT(11) 133 #define PHYCTRL0_UTMI_ON_CLOCK __BIT(10) 134 #define PHYCTRL0_OTG_OVER_CUR_POL __BIT(9) 135 #define PHYCTRL0_OTG_OVER_CUR_DIS __BIT(8) 136 #define PHYCTRL0_OTG_XCVR_CLK_SEL __BIT(7) 137 #define PHYCTRL0_H1_XCVR_CLK_SEL __BIT(4) 138 #define PHYCTRL0_PWR_POL __BIT(3) 139 #define PHYCTRL0_CHRGDET __BIT(2) 140 #define PHYCTRL0_CHRGDET_INT_EN __BIT(1) 141 #define PHYCTRL0_CHRGDET_INT_FLG __BIT(0) 142 143 #define USBOH3_PHYCTRL1 0x80c 144 #define PHYCTRL1_PLLDIVVALUE_MASK __BITS(0,1) 145 #define PHYCTRL1_PLLDIVVALUE_19MHZ 0 /* 19.2MHz */ 146 #define PHYCTRL1_PLLDIVVALUE_24MHZ 1 147 #define PHYCTRL1_PLLDIVVALUE_26MHZ 2 148 #define PHYCTRL1_PLLDIVVALUE_27MHZ 3 149 #define USBOH3_USBCTRL1 0x810 150 #define USBCTRL1_UH3_EXT_CLK_EN __BIT(27) 151 #define USBCTRL1_UH2_EXT_CLK_EN __BIT(26) 152 #define USBCTRL1_UH1_EXT_CLK_EN __BIT(25) 153 #define USBCTRL1_OTG_EXT_CLK_EN __BIT(24) 154 #define USBOH3_USBCTRL2 0x814 155 #define USBOH3_USBCTRL3 0x818 156 157 #define USBOH3_SIZE 0x820 158 159 /* GPIO module */ 160 161 #define GPIO_BASE(n) (0x73f84000 + 0x4000 * ((n)-1)) 162 163 #define GPIO1_BASE GPIO_BASE(1) 164 #define GPIO2_BASE GPIO_BASE(2) 165 #define GPIO3_BASE GPIO_BASE(3) 166 #define GPIO4_BASE GPIO_BASE(4) 167 168 #define GPIO_NGROUPS 4 169 170 #define KPP_BASE 0x73f94000 171 /* register definitions in imxkppreg.h */ 172 173 #define WDOG1_BASE 0x73f98000 174 #define WDOG2_BASE 0x73f9c000 175 #define WDOG_SIZE 0x000a 176 177 #define GPT_BASE 0x73fa0000 178 #define GPT_SIZE 0x4000 179 180 #define SRTC_BASE 0x73fa4000 181 #define SRTC_SIZE 0x4000 182 183 /* IO multiplexor */ 184 #define IOMUXC_BASE 0x73fa8000 185 #define IOMUXC_SIZE 0x4000 186 187 #define IOMUXC_MUX_CTL 0x001c /* multiprex control */ 188 #define IOMUX_CONFIG_ALT0 (0) 189 #define IOMUX_CONFIG_ALT1 (1) 190 #define IOMUX_CONFIG_ALT2 (2) 191 #define IOMUX_CONFIG_ALT3 (3) 192 #define IOMUX_CONFIG_ALT4 (4) 193 #define IOMUX_CONFIG_ALT5 (5) 194 #define IOMUX_CONFIG_ALT6 (6) 195 #define IOMUX_CONFIG_ALT7 (7) 196 #define IOMUX_CONFIG_SION __BIT(4) 197 #define IOMUXC_PAD_CTL 0x03f0 /* pad control */ 198 #define PAD_CTL_DDR_INPUT __BIT(9) 199 #define PAD_CTL_HYS __BIT(8) 200 #define PAD_CTL_PKE __BIT(7) 201 #define PAD_CTL_PUE __BIT(6) 202 #define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE) 203 #define PAD_CTL_KEEPER (PAD_CTL_PKE|0) 204 #define PAD_CTL_PUS_100K_PD (0x0 << 4) 205 #define PAD_CTL_PUS_47K_PU (0x1 << 4) 206 #define PAD_CTL_PUS_100K_PU (0x2 << 4) 207 #define PAD_CTL_PUS_22K_PU (0x3 << 4) 208 #define PAD_CTL_ODE __BIT(3) /* opendrain */ 209 #define PAD_CTL_DSE_LOW (0x0 << 1) 210 #define PAD_CTL_DSE_MID (0x1 << 1) 211 #define PAD_CTL_DSE_HIGH (0x2 << 1) 212 #define PAD_CTL_DSE_MAX (0x3 << 1) 213 #define PAD_CTL_SRE __BIT(0) 214 #define IOMUXC_INPUT_CTL 0x08c4 /* input control */ 215 #define INPUT_DAISY_0 0 216 #define INPUT_DAISY_1 1 217 #define INPUT_DAISY_2 2 218 #define INPUT_DAISY_3 3 219 #define INPUT_DAISY_4 4 220 #define INPUT_DAISY_5 5 221 #define INPUT_DAISY_6 6 222 #define INPUT_DAISY_7 7 223 224 /* 225 * IOMUX index 226 */ 227 #define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff) 228 #define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff) 229 230 #define IOMUX_PIN(mux_adr, pad_adr) \ 231 (((mux_adr) << 16) | (((pad_adr) << 0))) 232 #define IOMUX_MUX_NONE 0xffff 233 #define IOMUX_PAD_NONE 0xffff 234 235 /* EPIT */ 236 #define EPIT1_BASE 0x73FAC000 237 #define EPIT2_BASE 0x73FB0000 238 /* register definitions in imxepitreg.h */ 239 240 #define PWM1_BASE 0x73fb4000 241 #define PWM2_BASE 0x73fb8000 242 #define PWM_SIZE 0x4000 243 244 #define SRC_BASE 0x73fd0000 245 #define SRC_SIZE 0x4000 246 247 #define CCM_BASE 0x73fd4000 248 #define CCM_SIZE 0x0088 249 250 #define GPC_BASE 0x73fd8000 251 #define GPC_SIZE 0x4000 252 253 #define DPLLIP1_BASE 0x83f80000 254 #define DPLLIP2_BASE 0x83f84000 255 #define DPLLIP3_BASE 0x83f88000 256 #define DPLLIP_SIZE 0x4000 257 258 #define AHBMAX_BASE 0x83f94000 259 #define AHBMAX_SIZE 0x4000 260 261 #define IIM_BASE 0x83f98000 262 #define IIM_SIZE 0x4000 263 264 #define CSU_BASE 0x83f9c000 265 #define CSU_SIZE 0x4000 266 267 #define OWIRE_BASE 0x83fa4000 /* 1-wire */ 268 #define OWIRE_SIZE 0x4000 269 270 #define FIRI_BASE 0x83fa8000 271 #define FIRI_SIZE 0x4000 272 273 274 #define SDMA_BASE 0x83fb0000 275 #define SDMA_SIZE 0x4000 276 /* see imxsdmareg.h for register definitions */ 277 278 #define SCC_BASE 0x83fb4000 279 #define SCC_SIZE 0x4000 280 281 #define ROMCP_BASE 0x83fb8000 282 #define ROMCP_SIZE 0x4000 283 284 #define RTIC_BASE 0x83fbc000 285 #define RTIC_SIZE 0x4000 286 287 #define CSPI_BASE 0x83fc0000 288 #define CSPI_SIZE 0x4000 289 290 #define I2C1_BASE 0x83fc8000 291 #define I2C2_BASE 0x83fc4000 292 /* register definitions in imxi2creg.h */ 293 294 #define AUDMUX_BASE 0x83fd0000 295 #define AUDMUX_SIZE 0x4000 296 #define AUDMUX_PTCR(n) ((n - 1) * 0x8) 297 #define PTCR_TFSDIR (1 << 31) 298 #define PTCR_TFSEL(x) (((x) & 0x7) << 27) 299 #define PTCR_TCLKDIR (1 << 26) 300 #define PTCR_TCSEL(x) (((x) & 0x7) << 22) 301 #define PTCR_RFSDIR (1 << 21) 302 #define PTCR_RFSEL(x) (((x) & 0x7) << 17) 303 #define PTCR_RCLKDIR (1 << 16) 304 #define PTCR_RCSEL(x) (((x) & 0x7) << 12) 305 #define PTCR_SYN (1 << 11) 306 307 #define AUDMUX_PDCR(n) ((n - 1) * 0x8 + 0x4) 308 #define PDCR_RXDSEL(x) (((x) & 0x7) << 13) 309 #define PDCR_TXRXEN (1 << 12) 310 #define PDCR_MODE(x) (((x) & 0x3) << 8) 311 #define PDCR_INMMASK(x) (((x) & 0xff) << 0) 312 #define AUDMUX_CNMCR 0x38 313 314 #define EMI_BASE 0x83fd8000 315 #define EMI_SIZE 0x4000 316 317 #define SIM_BASE 0x83fe4000 318 #define SIM_SIZE 0x4000 319 320 #define FEC_BASE 0x83fec000 321 #define FEC_SIZE 0x4000 322 #define TVE_BASE 0x83ff0000 323 #define TVE_SIZE 0x4000 324 #define VPU_BASE 0x83ff4000 325 #define VPU_SIZE 0x4000 326 #define SAHARA_BASE 0x83ff8000 327 #define SAHARA_SIZE 0x4000 328 329 #define CSD0DDR_BASE 0x90000000 330 #define CSD1DDR_BASE 0xa0000000 331 #define CSDDDR_SIZE 0x10000000 /* 256MiB */ 332 #define CS0_BASE 0xb0000000 333 #define CS0_SIZE 0x08000000 /* 128MiB */ 334 #define CS1_BASE 0xb8000000 335 #define CS1_SIZE 0x08000000 /* 128MiB */ 336 #define CS2_BASE 0xc0000000 337 #define CS2_SIZE 0x08000000 /* 128MiB */ 338 #define CS3_BASE 0xc8000000 339 #define CS3_SIZE 0x04000000 /* 64MiB */ 340 #define CS4_BASE 0xcc000000 341 #define CS4_SIZE 0x02000000 /* 32MiB */ 342 #define CS5_BASE 0xcefe0000 343 #define CS5_SIZE 0x00010000 /* 32MiB */ 344 #define NAND_FLASH_BASE 0xcfff0000 /* internal buffer */ 345 #define NAND_FLASH_SIZE 0x00010000 346 347 #define GPU2D_BASE 0xd0000000 348 #define GPU2D_SIZE 0x10000000 349 350 #define TZIC_BASE 0xe0000000 351 /* register definitions in imx51_tzicreg.h */ 352 353 #endif /* _ARM_IMX_IMX51REG_H_ */ 354