1 /* $NetBSD: imx51reg.h,v 1.4 2012/04/15 16:34:11 bsh Exp $ */ 2 /*- 3 * Copyright (c) 2007 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_IMX_IMX51REG_H_ 32 #define _ARM_IMX_IMX51REG_H_ 33 34 #define BOOTROM_BASE 0x00000000 35 #define BOOTROM_SIZE 0x9000 36 37 #define SCCRAM_BASE 0x1ffe0000 38 #define SCCRAM_SIZE 0x20000 39 40 #define GPUMEM_BASE 0x20000000 41 #define GPUMEM_SIZE 0x20000 42 43 #define GPU_BASE 0x30000000 44 #define GPU_SIZE 0x10000000 45 46 /* Image Prossasing Unit */ 47 #define IPU_BASE 0x40000000 48 #define IPU_CM_BASE (IPU_BASE + 0x1e000000) 49 #define IPU_CM_SIZE 0x8000 50 #define IPU_IDMAC_BASE (IPU_BASE + 0x1e008000) 51 #define IPU_IDMAC_SIZE 0x8000 52 #define IPU_DP_BASE (IPU_BASE + 0x1e018000) 53 #define IPU_DP_SIZE 0x8000 54 #define IPU_IC_BASE (IPU_BASE + 0x1e020000) 55 #define IPU_IC_SIZE 0x8000 56 #define IPU_IRT_BASE (IPU_BASE + 0x1e028000) 57 #define IPU_IRT_SIZE 0x8000 58 #define IPU_CSI0_BASE (IPU_BASE + 0x1e030000) 59 #define IPU_CSI0_SIZE 0x8000 60 #define IPU_CSI1_BASE (IPU_BASE + 0x1e038000) 61 #define IPU_CSI1_SIZE 0x8000 62 #define IPU_DI0_BASE (IPU_BASE + 0x1e040000) 63 #define IPU_DI0_SIZE 0x8000 64 #define IPU_DI1_BASE (IPU_BASE + 0x1e048000) 65 #define IPU_DI1_SIZE 0x8000 66 #define IPU_SMFC_BASE (IPU_BASE + 0x1e050000) 67 #define IPU_SMFC_SIZE 0x8000 68 #define IPU_DC_BASE (IPU_BASE + 0x1e058000) 69 #define IPU_DC_SIZE 0x8000 70 #define IPU_DMFC_BASE (IPU_BASE + 0x1e060000) 71 #define IPU_DMFC_SIZE 0x8000 72 #define IPU_VDI_BASE (IPU_BASE + 0x1e068000) 73 #define IPU_VDI_SIZE 0x8000 74 #define IPU_CPMEM_BASE (IPU_BASE + 0x1f000000) 75 #define IPU_CPMEM_SIZE 0x20000 76 #define IPU_LUT_BASE (IPU_BASE + 0x1f020000) 77 #define IPU_LUT_SIZE 0x20000 78 #define IPU_SRM_BASE (IPU_BASE + 0x1f040000) 79 #define IPU_SRM_SIZE 0x20000 80 #define IPU_TPM_BASE (IPU_BASE + 0x1f060000) 81 #define IPU_TPM_SIZE 0x20000 82 #define IPU_DCTMPL_BASE (IPU_BASE + 0x1f080000) 83 #define IPU_DCTMPL_SIZE 0x20000 84 85 #define DEBUGROM_BASE 0x60000000 86 #define DEBUGROM_SIZE 0x1000 87 88 #define ESDHC1_BASE 0x70004000 89 #define ESDHC2_BASE 0x70008000 90 #define ESDHC3_BASE 0x70020000 91 #define ESDHC4_BASE 0x70024000 92 #define ESDHC_SIZE 0x4000 93 94 #define UART1_BASE 0x73fbc000 95 #define UART2_BASE 0x73fc0000 96 #define UART3_BASE 0x7000c000 97 /* register definitions in imxuartreg.h */ 98 99 #define ECSPI1_BASE 0x70010000 100 #define ECSPI2_BASE 0x83fac000 101 #define ECSPI_SIZE 0x4000 102 103 #define SSI1_BASE 0x83fcc000 104 #define SSI2_BASE 0x70014000 105 #define SSI3_BASE 0x83fe8000 106 /* register definitions in imxssireg.h */ 107 108 #define SPDIF_BASE 0x70028000 109 #define SPDIF_SIZE 0x4000 110 111 #define PATA_UDMA_BASE 0x70030000 112 #define PATA_UDMA_SIZE 0x4000 113 #define PATA_PIO_BASE 0x83fe0000 114 #define PATA_PIO_SIZE 0x4000 115 116 #define SLM_BASE 0x70034000 117 #define SLM_SIZE 0x4000 118 119 #define HSI2C_BASE 0x70038000 120 #define HSI2C_SIZE 0x4000 121 122 #define SPBA_BASE 0x7003c000 123 #define SPBA_SIZE 0x4000 124 125 #define USBOH3_BASE 0x73f80000 126 #define USBOH3_PL301_BASE 0x73fc4000 127 #define USBOH3_EHCI_SIZE 0x200 128 #define USBOH3_OTG 0x000 129 #define USBOH3_EHCI(n) (USBOH3_EHCI_SIZE*(n)) /* n=1,2,3 */ 130 131 /* USB_CTRL register */ 132 #define USBOH3_USBCTRL 0x800 133 #define USBCTRL_OWIR __BIT(31) /* OTG Wakeup interrupt request */ 134 #define USBCTRL_OSIC_SHIFT 29 135 #define USBCTRL_OSIC __BITS(29,30) /* OTG Serial interface configuration */ 136 #define USBCTRL_OUIE __BIT(28) /* OTG Wake-up interrupt enable */ 137 #define USBCTRL_OBPAL __BITS(25,26) /* OTG Bypass value */ 138 #define USBCTRL_OPM __BIT(24) /* OTG Power Mask */ 139 #define USBCTRL_ICVOL __BIT(23) /* Host1 IC_USB voltage status */ 140 #define USBCTRL_ICTPIE __BIT(19) /* IC USB TP interrupt enable */ 141 #define USBCTRL_UBPCKE __BIT(18) /* Bypass clock enable */ 142 #define USBCTRL_H1TCKOEN __BIT(17) /* Host1 ULPO PHY clock enable */ 143 #define USBCTRL_ICTPC __BIT(16) /* Clear IC TP interrupt flag */ 144 #define USBCTRL_H1WIR __BIT(15) /* Host1 wakeup interrupt request */ 145 #define USBCTRL_H1STC_SHIFT 13 146 #define USBCTRL_H1SIC __BITS(13,14) /* Host1 serial interface config */ 147 #define USBCTRL_H1UIE __BIT(12) /* Host1 ILPI interrupt enable */ 148 #define USBCTRL_H1WIE __BIT(11) /* Host1 wakeup interrupt enable */ 149 #define USBCTRL_H1BPVAL __BITS(9,10) /* Host1 bypass value */ 150 #define USBCTRL_H1PM __BIT(8) /* Host1 power mask */ 151 #define USBCTRL_OHSTLL __BIT(7) /* OTG ULPI TLL enable */ 152 #define USBCTRL_H1HSTLL __BIT(6) /* Host1 ULPI TLL enable */ 153 #define USBCTRL_H1DISFSTTL __BIT(4) /* Host1 serial TLL disable */ 154 #define USBCTRL_OTCKOEN __BIT(1) /* OTG ULPI PHY clock enable */ 155 #define USBCTRL_BPE __BIT(0) /* Bypass enable */ 156 157 #define USBOH3_OTGMIRROR 0x804 158 #define USBOH3_PHYCTRL0 0x808 159 #define PHYCTRL0_VLOAD __BIT(31) 160 #define PHYCTRL0_VCONTROL __BITS(27,30) 161 #define PHYCTRL0_CONF2 __BIT(26) 162 #define PHYCTRL0_CONF3 __BIT(25) 163 #define PHYCTRL0_CHGRDETEN __BIT(24) 164 #define PHYCTRL0_CHGRDETON __BIT(23) 165 #define PHYCTRL0_VSTATUS __BITS(15,22) 166 #define PHYCTRL0_SUSPENDM __BIT(12) 167 #define PHYCTRL0_RESET __BIT(11) 168 #define PHYCTRL0_UTMI_ON_CLOCK __BIT(10) 169 #define PHYCTRL0_OTG_OVER_CUR_POL __BIT(9) 170 #define PHYCTRL0_OTG_OVER_CUR_DIS __BIT(8) 171 #define PHYCTRL0_OTG_XCVR_CLK_SEL __BIT(7) 172 #define PHYCTRL0_H1_XCVR_CLK_SEL __BIT(4) 173 #define PHYCTRL0_PWR_POL __BIT(3) 174 #define PHYCTRL0_CHRGDET __BIT(2) 175 #define PHYCTRL0_CHRGDET_INT_EN __BIT(1) 176 #define PHYCTRL0_CHRGDET_INT_FLG __BIT(0) 177 178 #define USBOH3_PHYCTRL1 0x80c 179 #define PHYCTRL1_PLLDIVVALUE_MASK __BITS(0,1) 180 #define PHYCTRL1_PLLDIVVALUE_19MHZ 0 /* 19.2MHz */ 181 #define PHYCTRL1_PLLDIVVALUE_24MHZ 1 182 #define PHYCTRL1_PLLDIVVALUE_26MHZ 2 183 #define PHYCTRL1_PLLDIVVALUE_27MHZ 3 184 #define USBOH3_USBCTRL1 0x810 185 #define USBCTRL1_UH3_EXT_CLK_EN __BIT(27) 186 #define USBCTRL1_UH2_EXT_CLK_EN __BIT(26) 187 #define USBCTRL1_UH1_EXT_CLK_EN __BIT(25) 188 #define USBCTRL1_OTG_EXT_CLK_EN __BIT(24) 189 #define USBOH3_USBCTRL2 0x814 190 #define USBOH3_USBCTRL3 0x818 191 192 #define USBOH3_SIZE 0x820 193 194 /* GPIO module */ 195 196 #define GPIO_BASE(n) (0x73f84000 + 0x4000 * ((n)-1)) 197 198 #define GPIO1_BASE GPIO_BASE(1) 199 #define GPIO2_BASE GPIO_BASE(2) 200 #define GPIO3_BASE GPIO_BASE(3) 201 #define GPIO4_BASE GPIO_BASE(4) 202 203 #define GPIO_NGROUPS 4 204 205 #define KPP_BASE 0x73f94000 206 /* register definitions in imxkppreg.h */ 207 208 #define WDOG1_BASE 0x73f98000 209 #define WDOG2_BASE 0x73f9c000 210 #define WDOG_SIZE 0x000a 211 212 #define GPT_BASE 0x73fa0000 213 #define GPT_SIZE 0x4000 214 215 #define SRTC_BASE 0x73fa4000 216 #define SRTC_SIZE 0x4000 217 218 /* IO multiplexor */ 219 #define IOMUXC_BASE 0x73fa8000 220 #define IOMUXC_SIZE 0x4000 221 222 #define IOMUXC_MUX_CTL 0x001c /* multiprex control */ 223 #define IOMUX_CONFIG_SION __BIT(4) 224 #define IOMUX_CONFIG_ALT0 (0) 225 #define IOMUX_CONFIG_ALT1 (1) 226 #define IOMUX_CONFIG_ALT2 (2) 227 #define IOMUX_CONFIG_ALT3 (3) 228 #define IOMUX_CONFIG_ALT4 (4) 229 #define IOMUX_CONFIG_ALT5 (5) 230 #define IOMUX_CONFIG_ALT6 (6) 231 #define IOMUX_CONFIG_ALT7 (7) 232 #define IOMUXC_PAD_CTL 0x03f0 /* pad control */ 233 #define PAD_CTL_HVE __BIT(13) 234 #define PAD_CTL_DDR_INPUT __BIT(9) 235 #define PAD_CTL_HYS __BIT(8) 236 #define PAD_CTL_PKE __BIT(7) 237 #define PAD_CTL_PUE __BIT(6) 238 #define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE) 239 #define PAD_CTL_KEEPER (PAD_CTL_PKE|0) 240 #define PAD_CTL_PUS_100K_PD (0x0 << 4) 241 #define PAD_CTL_PUS_47K_PU (0x1 << 4) 242 #define PAD_CTL_PUS_100K_PU (0x2 << 4) 243 #define PAD_CTL_PUS_22K_PU (0x3 << 4) 244 #define PAD_CTL_ODE __BIT(3) /* opendrain */ 245 #define PAD_CTL_DSE_LOW (0x0 << 1) 246 #define PAD_CTL_DSE_MID (0x1 << 1) 247 #define PAD_CTL_DSE_HIGH (0x2 << 1) 248 #define PAD_CTL_DSE_MAX (0x3 << 1) 249 #define PAD_CTL_SRE __BIT(0) 250 #define IOMUXC_INPUT_CTL 0x08c4 /* input control */ 251 #define INPUT_DAISY_0 0 252 #define INPUT_DAISY_1 1 253 #define INPUT_DAISY_2 2 254 #define INPUT_DAISY_3 3 255 #define INPUT_DAISY_4 4 256 #define INPUT_DAISY_5 5 257 #define INPUT_DAISY_6 6 258 #define INPUT_DAISY_7 7 259 260 /* 261 * IOMUX index 262 */ 263 #define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff) 264 #define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff) 265 266 #define IOMUX_PIN(mux_adr, pad_adr) \ 267 (((mux_adr) << 16) | (((pad_adr) << 0))) 268 #define IOMUX_MUX_NONE 0xffff 269 #define IOMUX_PAD_NONE 0xffff 270 271 /* EPIT */ 272 #define EPIT1_BASE 0x73FAC000 273 #define EPIT2_BASE 0x73FB0000 274 /* register definitions in imxepitreg.h */ 275 276 #define PWM1_BASE 0x73fb4000 277 #define PWM2_BASE 0x73fb8000 278 #define PWM_SIZE 0x4000 279 280 #define SRC_BASE 0x73fd0000 281 #define SRC_SIZE 0x4000 282 283 #define CCM_BASE 0x73fd4000 284 #define CCM_SIZE 0x0088 285 286 #define GPC_BASE 0x73fd8000 287 #define GPC_SIZE 0x4000 288 289 #define DPLLIP1_BASE 0x83f80000 290 #define DPLLIP2_BASE 0x83f84000 291 #define DPLLIP3_BASE 0x83f88000 292 #define DPLLIP_SIZE 0x4000 293 294 #define AHBMAX_BASE 0x83f94000 295 #define AHBMAX_SIZE 0x4000 296 297 #define IIM_BASE 0x83f98000 298 #define IIM_SIZE 0x4000 299 300 #define CSU_BASE 0x83f9c000 301 #define CSU_SIZE 0x4000 302 303 #define OWIRE_BASE 0x83fa4000 /* 1-wire */ 304 #define OWIRE_SIZE 0x4000 305 306 #define FIRI_BASE 0x83fa8000 307 #define FIRI_SIZE 0x4000 308 309 310 #define SDMA_BASE 0x83fb0000 311 #define SDMA_SIZE 0x4000 312 /* see imxsdmareg.h for register definitions */ 313 314 #define SCC_BASE 0x83fb4000 315 #define SCC_SIZE 0x4000 316 317 #define ROMCP_BASE 0x83fb8000 318 #define ROMCP_SIZE 0x4000 319 320 #define RTIC_BASE 0x83fbc000 321 #define RTIC_SIZE 0x4000 322 323 #define CSPI_BASE 0x83fc0000 324 #define CSPI_SIZE 0x4000 325 326 #define I2C1_BASE 0x83fc8000 327 #define I2C2_BASE 0x83fc4000 328 /* register definitions in imxi2creg.h */ 329 330 #define AUDMUX_BASE 0x83fd0000 331 #define AUDMUX_SIZE 0x4000 332 #define AUDMUX_PTCR(n) ((n - 1) * 0x8) 333 #define PTCR_TFSDIR (1 << 31) 334 #define PTCR_TFSEL(x) (((x) & 0x7) << 27) 335 #define PTCR_TCLKDIR (1 << 26) 336 #define PTCR_TCSEL(x) (((x) & 0x7) << 22) 337 #define PTCR_RFSDIR (1 << 21) 338 #define PTCR_RFSEL(x) (((x) & 0x7) << 17) 339 #define PTCR_RCLKDIR (1 << 16) 340 #define PTCR_RCSEL(x) (((x) & 0x7) << 12) 341 #define PTCR_SYN (1 << 11) 342 343 #define AUDMUX_PDCR(n) ((n - 1) * 0x8 + 0x4) 344 #define PDCR_RXDSEL(x) (((x) & 0x7) << 13) 345 #define PDCR_TXRXEN (1 << 12) 346 #define PDCR_MODE(x) (((x) & 0x3) << 8) 347 #define PDCR_INMMASK(x) (((x) & 0xff) << 0) 348 #define AUDMUX_CNMCR 0x38 349 350 #define EMI_BASE 0x83fd8000 351 #define EMI_SIZE 0x4000 352 353 #define SIM_BASE 0x83fe4000 354 #define SIM_SIZE 0x4000 355 356 #define FEC_BASE 0x83fec000 357 #define FEC_SIZE 0x4000 358 #define TVE_BASE 0x83ff0000 359 #define TVE_SIZE 0x4000 360 #define VPU_BASE 0x83ff4000 361 #define VPU_SIZE 0x4000 362 #define SAHARA_BASE 0x83ff8000 363 #define SAHARA_SIZE 0x4000 364 365 #define CSD0DDR_BASE 0x90000000 366 #define CSD1DDR_BASE 0xa0000000 367 #define CSDDDR_SIZE 0x10000000 /* 256MiB */ 368 #define CS0_BASE 0xb0000000 369 #define CS0_SIZE 0x08000000 /* 128MiB */ 370 #define CS1_BASE 0xb8000000 371 #define CS1_SIZE 0x08000000 /* 128MiB */ 372 #define CS2_BASE 0xc0000000 373 #define CS2_SIZE 0x08000000 /* 128MiB */ 374 #define CS3_BASE 0xc8000000 375 #define CS3_SIZE 0x04000000 /* 64MiB */ 376 #define CS4_BASE 0xcc000000 377 #define CS4_SIZE 0x02000000 /* 32MiB */ 378 #define CS5_BASE 0xcefe0000 379 #define CS5_SIZE 0x00010000 /* 32MiB */ 380 #define NAND_FLASH_BASE 0xcfff0000 /* internal buffer */ 381 #define NAND_FLASH_SIZE 0x00010000 382 383 #define GPU2D_BASE 0xd0000000 384 #define GPU2D_SIZE 0x10000000 385 386 #define TZIC_BASE 0xe0000000 387 /* register definitions in imx51_tzicreg.h */ 388 389 #endif /* _ARM_IMX_IMX51REG_H_ */ 390