1 /* $NetBSD: imx51_tzic.c,v 1.6 2014/03/10 09:35:18 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 SHIMIZU Ryo <ryo@nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: imx51_tzic.c,v 1.6 2014/03/10 09:35:18 skrll Exp $"); 30 31 #define _INTR_PRIVATE /* for arm/pic/picvar.h */ 32 33 #include "locators.h" 34 35 #include <sys/param.h> 36 #include <sys/evcnt.h> 37 #include <sys/device.h> 38 #include <sys/atomic.h> 39 40 #include <machine/intr.h> 41 #include <sys/bus.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <arm/cpu.h> 46 #include <arm/armreg.h> 47 #include <arm/cpufunc.h> 48 49 #include <machine/autoconf.h> 50 51 #include <arm/imx/imx51reg.h> 52 #include <arm/imx/imx51var.h> 53 #include <arm/imx/imx51_tzicreg.h> 54 55 static int tzic_match(device_t, cfdata_t, void *); 56 static void tzic_attach(device_t, device_t, void *); 57 58 /* for arm/pic */ 59 static void tzic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 60 static void tzic_block_irqs(struct pic_softc *, size_t, uint32_t); 61 static void tzic_establish_irq(struct pic_softc *, struct intrsource *); 62 static void tzic_source_name(struct pic_softc *, int, char *, size_t); 63 64 struct tzic_softc { 65 device_t sc_dev; 66 struct pic_softc sc_pic; 67 bus_space_tag_t sc_iot; 68 bus_space_handle_t sc_ioh; 69 uint32_t sc_enabled_mask[4]; 70 }; 71 72 const struct pic_ops tzic_pic_ops = { 73 .pic_unblock_irqs = tzic_unblock_irqs, 74 .pic_block_irqs = tzic_block_irqs, 75 .pic_establish_irq = tzic_establish_irq, 76 .pic_source_name = tzic_source_name 77 }; 78 79 static void tzic_intr_init(struct tzic_softc * const); 80 81 static const char * const tzic_intr_source_names[] = TZIC_INTR_SOURCE_NAMES; 82 83 extern struct cfdriver tzic_cd; 84 85 #define PIC_TO_SOFTC(pic) \ 86 ((struct tzic_softc *)((char *)(pic) - \ 87 offsetof(struct tzic_softc, sc_pic))) 88 89 #define INTC_READ(tzic, reg) \ 90 bus_space_read_4((tzic)->sc_iot, (tzic)->sc_ioh, (reg)) 91 #define INTC_WRITE(tzic, reg, val) \ 92 bus_space_write_4((tzic)->sc_iot, (tzic)->sc_ioh, (reg), (val)) 93 94 /* use [7:4] of interrupt priority. 95 * 0 is the highest priority. 96 */ 97 #define HW_TO_SW_IPL(ipl) (IPL_HIGH - ((ipl) >> 3)) 98 #define SW_TO_HW_IPL(ipl) ((IPL_HIGH - (ipl)) << 3) 99 100 CFATTACH_DECL_NEW(tzic, sizeof(struct tzic_softc), 101 tzic_match, tzic_attach, NULL, NULL); 102 103 struct tzic_softc *tzic_softc; 104 105 int 106 tzic_match(device_t parent, cfdata_t self, void *aux) 107 { 108 struct axi_attach_args *aa; 109 110 aa = aux; 111 112 if (aa->aa_addr != TZIC_BASE) 113 return 0; 114 115 return 1; 116 } 117 118 void 119 tzic_attach(device_t parent, device_t self, void *aux) 120 { 121 struct tzic_softc *tzic = device_private(self); 122 struct axi_attach_args * const aa = aux; 123 int error; 124 125 KASSERT(aa->aa_irqbase != AXICF_IRQBASE_DEFAULT); 126 KASSERT(self->dv_unit == 0); 127 128 aprint_normal(": TrustZone Interrupt Controller\n"); 129 aprint_naive("\n"); 130 131 tzic->sc_dev = self; 132 tzic->sc_iot = aa->aa_iot; 133 134 tzic_softc = tzic; 135 136 if (aa->aa_size == AXICF_SIZE_DEFAULT) 137 aa->aa_size = TZIC_SIZE; 138 139 error = bus_space_map(tzic->sc_iot, aa->aa_addr, aa->aa_size, 0, &tzic->sc_ioh); 140 141 if (error) { 142 panic("tzic_attach: failed to map register %#x-%#x: %d", 143 (uint32_t)aa->aa_addr, 144 (uint32_t)(aa->aa_addr + aa->aa_size - 1), 145 error); 146 } 147 148 tzic_intr_init(tzic); 149 150 tzic->sc_pic.pic_ops = &tzic_pic_ops; 151 tzic->sc_pic.pic_maxsources = TZIC_INTNUM; 152 strlcpy(tzic->sc_pic.pic_name, device_xname(self), 153 sizeof(tzic->sc_pic.pic_name)); 154 155 pic_add(&tzic->sc_pic, aa->aa_irqbase); 156 157 aprint_normal_dev(tzic->sc_dev, "interrupts %d..%d register VA:%p\n", 158 aa->aa_irqbase, aa->aa_irqbase + TZIC_INTNUM, 159 (void *)tzic->sc_ioh); 160 161 /* Everything is all set. Enable the interrupts. */ 162 enable_interrupts(I32_bit|F32_bit); 163 } 164 165 166 void 167 tzic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 168 { 169 struct tzic_softc * const tzic = PIC_TO_SOFTC(pic); 170 const size_t group = irq_base / 32; 171 172 KASSERT((irq_mask & tzic->sc_enabled_mask[group]) == 0); 173 174 tzic->sc_enabled_mask[group] |= irq_mask; 175 INTC_WRITE(tzic, TZIC_ENSET(group), irq_mask); 176 } 177 178 void 179 tzic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 180 { 181 struct tzic_softc * const tzic = PIC_TO_SOFTC(pic); 182 const size_t group = irq_base / 32; 183 184 tzic->sc_enabled_mask[group] &= ~irq_mask; 185 186 INTC_WRITE(tzic, TZIC_ENCLEAR(group), irq_mask); 187 } 188 189 /* 190 * Called with interrupts disabled 191 */ 192 static int 193 find_pending_irqs(struct tzic_softc *tzic, size_t group) 194 { 195 uint32_t pending = 0; 196 197 KASSERT( group <= 3 ); 198 199 pending = INTC_READ(tzic, TZIC_PND(group)); 200 201 KASSERT((tzic->sc_enabled_mask[group] & pending) == pending); 202 203 if (pending == 0) 204 return 0; 205 206 return pic_mark_pending_sources(&tzic->sc_pic, group * 32, pending); 207 } 208 209 void 210 tzic_establish_irq(struct pic_softc *pic, struct intrsource *is) 211 { 212 struct tzic_softc * const tzic = PIC_TO_SOFTC(pic); 213 int priority_shift; 214 int priority_offset; 215 uint32_t reg; 216 217 KASSERT(is->is_irq < 128); 218 KASSERT(is->is_ipl < 16); 219 KASSERT(is->is_type == IST_LEVEL); 220 221 priority_shift = (is->is_irq % 4) * 8; 222 priority_offset = (is->is_irq / 4); 223 reg = INTC_READ(tzic, TZIC_PRIORITY(priority_offset)); 224 reg &= ~(0xff << priority_shift); 225 reg |= SW_TO_HW_IPL(is->is_ipl) << priority_shift; 226 INTC_WRITE(tzic, TZIC_PRIORITY(priority_offset), reg); 227 } 228 229 void 230 tzic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len) 231 { 232 strlcpy(buf, tzic_intr_source_names[irq], len); 233 } 234 235 void 236 imx51_irq_handler(void *frame) 237 { 238 struct cpu_info * const ci = curcpu(); 239 const int oldipl = ci->ci_cpl; 240 const uint32_t oldipl_mask = __BIT(oldipl); 241 int ipl_mask = 0; 242 243 ci->ci_data.cpu_nintr++; 244 245 if (tzic_softc->sc_enabled_mask[0]) 246 ipl_mask |= find_pending_irqs(tzic_softc, 0); 247 if (tzic_softc->sc_enabled_mask[1]) 248 ipl_mask |= find_pending_irqs(tzic_softc, 1); 249 if (tzic_softc->sc_enabled_mask[2]) 250 ipl_mask |= find_pending_irqs(tzic_softc, 2); 251 if (tzic_softc->sc_enabled_mask[3]) 252 ipl_mask |= find_pending_irqs(tzic_softc, 3); 253 254 if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 255 pic_do_pending_ints(I32_bit, oldipl, frame); 256 } 257 258 static void 259 tzic_intr_init(struct tzic_softc * const tzic) 260 { 261 int i; 262 263 disable_interrupts(I32_bit|F32_bit); 264 265 (void) INTC_READ(tzic, TZIC_INTCNTL); 266 INTC_WRITE(tzic, TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN); 267 (void) INTC_READ(tzic, TZIC_INTCNTL); 268 INTC_WRITE(tzic, TZIC_PRIOMASK, SW_TO_HW_IPL(IPL_NONE)); 269 (void) INTC_READ(tzic, TZIC_PRIOMASK); 270 271 INTC_WRITE(tzic, TZIC_SYNCCTRL, 0x00); 272 (void) INTC_READ(tzic, TZIC_SYNCCTRL); 273 274 /* route all interrupts to IRQ. secure interrupts are for FIQ */ 275 for (i = 0; i < 4; i++) 276 INTC_WRITE(tzic, TZIC_INTSEC(i), 0xffffffff); 277 278 /* disable all interrupts */ 279 for (i = 0; i < 4; i++) 280 INTC_WRITE(tzic, TZIC_ENCLEAR(i), 0xffffffff); 281 282 } 283