1 /* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */ 2 /* 3 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _ARM_IMX_IMX51_IPUV3REG_H 28 #define _ARM_IMX_IMX51_IPUV3REG_H 29 30 /* register offset address */ 31 32 /* 33 * CM 34 * Control Module 35 */ 36 #define IPU_CM_CONF 0x00000000 37 #define CM_CONF_CSI_SEL __BIT(31) 38 #define CM_CONF_IC_INPUT __BIT(30) 39 #define CM_CONF_CSI1_DATA_SOURCE __BIT(29) 40 #define CM_CONF_CSI0_DATA_SOURCE __BIT(28) 41 #define CM_CONF_VDI_DMFC_SYNC __BIT(27) 42 #define CM_CONF_IC_DMFC_SYNC __BIT(26) 43 #define CM_CONF_IC_DMFC_SEL __BIT(25) 44 #define CM_CONF_ISP_DOUBLE_FLOW __BIT(24) 45 #define CM_CONF_IDMAC_DISABLE __BIT(22) 46 #define CM_CONF_IPU_DIAGBUS_ON __BIT(21) 47 #define CM_CONF_IPU_DIAGBUS_MODE __BITS(20, 16) 48 #define CM_CONF_VDI_EN __BIT(12) 49 #define CM_CONF_SISG_EN __BIT(11) 50 #define CM_CONF_DMFC_EN __BIT(10) 51 #define CM_CONF_DC_EN __BIT(9) 52 #define CM_CONF_SMFC_EN __BIT(8) 53 #define CM_CONF_DI1_EN __BIT(7) 54 #define CM_CONF_DI0_EN __BIT(6) 55 #define CM_CONF_DP_EN __BIT(5) 56 #define CM_CONF_ISP_EN __BIT(4) 57 #define CM_CONF_IRT_EN __BIT(3) 58 #define CM_CONF_IC_EN __BIT(2) 59 #define CM_CONF_CSI1_EN __BIT(1) 60 #define CM_CONF_CSI0_EN __BIT(0) 61 #define IPU_SISG_CTRL0 0x00000004 62 #define IPU_SISG_CTRL1 0x00000008 63 #define IPU_CM_INT_CTRL_1 0x0000003c 64 #define IPU_CM_INT_CTRL_2 0x00000040 65 #define IPU_CM_INT_CTRL_3 0x00000044 66 #define IPU_CM_INT_CTRL_4 0x00000048 67 #define IPU_CM_INT_CTRL_5 0x0000004c 68 #define IPU_CM_INT_CTRL_6 0x00000050 69 #define IPU_CM_INT_CTRL_7 0x00000054 70 #define IPU_CM_INT_CTRL_8 0x00000058 71 #define IPU_CM_INT_CTRL_9 0x0000005c 72 #define IPU_CM_INT_CTRL_10 0x00000060 73 #define IPU_CM_INT_CTRL_11 0x00000064 74 #define IPU_CM_INT_CTRL_12 0x00000068 75 #define IPU_CM_INT_CTRL_13 0x0000006c 76 #define IPU_CM_INT_CTRL_14 0x00000070 77 #define IPU_CM_INT_CTRL_15 0x00000074 78 #define IPU_CM_SDMA_EVENT_1 0x00000078 79 #define IPU_CM_SDMA_EVENT_2 0x0000007c 80 #define IPU_CM_SDMA_EVENT_3 0x00000080 81 #define IPU_CM_SDMA_EVENT_4 0x00000084 82 #define IPU_CM_SDMA_EVENT_7 0x00000088 83 #define IPU_CM_SDMA_EVENT_8 0x0000008c 84 #define IPU_CM_SDMA_EVENT_11 0x00000090 85 #define IPU_CM_SDMA_EVENT_12 0x00000094 86 #define IPU_CM_SDMA_EVENT_13 0x00000098 87 #define IPU_CM_SDMA_EVENT_14 0x0000009c 88 #define IPU_CM_SRM_PRI1 0x000000a0 89 #define IPU_CM_SRM_PRI2 0x000000a4 90 #define IPU_CM_FS_PROC_FLOW1 0x000000a8 91 #define IPU_CM_FS_PROC_FLOW2 0x000000ac 92 #define IPU_CM_FS_PROC_FLOW3 0x000000b0 93 #define IPU_CM_FS_DISP_FLOW1 0x000000b4 94 #define IPU_CM_FS_DISP_FLOW2 0x000000b8 95 #define IPU_CM_SKIP 0x000000bc 96 #define IPU_CM_DISP_ALT_CONF 0x000000c0 97 #define IPU_CM_DISP_GEN 0x000000c4 98 #define CM_DISP_GEN_DI0_COUNTER_RELEASE __BIT(24) 99 #define CM_DISP_GEN_DI1_COUNTER_RELEASE __BIT(23) 100 #define CM_DISP_GEN_MCU_MAX_BURST_STOP __BIT(22) 101 #define CM_DISP_GEN_MCU_T_SHIFT 18 102 #define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) 103 #define IPU_CM_DISP_ALT1 0x000000c8 104 #define IPU_CM_DISP_ALT2 0x000000cc 105 #define IPU_CM_DISP_ALT3 0x000000d0 106 #define IPU_CM_DISP_ALT4 0x000000d4 107 #define IPU_CM_SNOOP 0x000000d8 108 #define IPU_CM_MEM_RST 0x000000dc 109 #define CM_MEM_START __BIT(31) 110 #define CM_MEM_EN __BITS(22, 0) 111 #define IPU_CM_PM 0x000000e0 112 #define IPU_CM_GPR 0x000000e4 113 #define CM_GPR_IPU_CH_BUF1_RDY1_CLR __BIT(31) 114 #define CM_GPR_IPU_CH_BUF1_RDY0_CLR __BIT(30) 115 #define CM_GPR_IPU_CH_BUF0_RDY1_CLR __BIT(29) 116 #define CM_GPR_IPU_CH_BUF0_RDY0_CLR __BIT(28) 117 #define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR __BIT(27) 118 #define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR __BIT(26) 119 #define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR __BIT(25) 120 #define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR __BIT(24) 121 #define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS __BIT(23) 122 #define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS __BIT(22) 123 #define CM_GPR_IPU_CH_BUF2_RDY1_CLR __BIT(21) 124 #define CM_GPR_IPU_CH_BUF2_RDY0_CLR __BIT(20) 125 #define CM_GPR_IPU_GP(n) __BIT((n)) 126 #define IPU_CM_CH_DB_MODE_SEL_0 0x00000150 127 #define IPU_CM_CH_DB_MODE_SEL_1 0x00000154 128 #define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168 129 #define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c 130 #define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178 131 #define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c 132 #define IPU_CM_INT_STAT_1 0x00000200 133 #define IPU_CM_INT_STAT_2 0x00000204 134 #define IPU_CM_INT_STAT_3 0x00000208 135 #define IPU_CM_INT_STAT_4 0x0000020c 136 #define IPU_CM_INT_STAT_5 0x00000210 137 #define IPU_CM_INT_STAT_6 0x00000214 138 #define IPU_CM_INT_STAT_7 0x00000218 139 #define IPU_CM_INT_STAT_8 0x0000021c 140 #define IPU_CM_INT_STAT_9 0x00000220 141 #define IPU_CM_INT_STAT_10 0x00000224 142 #define IPU_CM_INT_STAT_11 0x00000228 143 #define IPU_CM_INT_STAT_12 0x0000022c 144 #define IPU_CM_INT_STAT_13 0x00000230 145 #define IPU_CM_INT_STAT_14 0x00000234 146 #define IPU_CM_INT_STAT_15 0x00000238 147 #define IPU_CM_CUR_BUF_0 0x0000023c 148 #define IPU_CM_CUR_BUF_1 0x00000240 149 #define IPU_CM_ALT_CUR_BUF_0 0x00000244 150 #define IPU_CM_ALT_CUR_BUF_1 0x00000248 151 #define IPU_CM_SRM_STAT 0x0000024c 152 #define IPU_CM_PROC_TASKS_STAT 0x00000250 153 #define IPU_CM_DISP_TASKS_STAT 0x00000254 154 #define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258 155 #define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c 156 #define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260 157 #define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264 158 #define IPU_CM_CH_BUF0_RDY0 0x00000268 159 #define IPU_CM_CH_BUF0_RDY1 0x0000026c 160 #define IPU_CM_CH_BUF1_RDY0 0x00000270 161 #define IPU_CM_CH_BUF1_RDY1 0x00000274 162 #define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278 163 #define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c 164 #define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280 165 #define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284 166 #define IPU_CM_CH_BUF2_RDY0 0x00000288 167 #define IPU_CM_CH_BUF2_RDY1 0x0000028c 168 169 /* 170 * IDMAC 171 * Image DMA Controller 172 */ 173 #define IPU_IDMAC_CONF 0x00000000 174 #define IPU_IDMAC_CH_EN_1 0x00000004 175 #define IPU_IDMAC_CH_EN_2 0x00000008 176 #define IPU_IDMAC_SEP_ALPHA 0x0000000c 177 #define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010 178 #define IPU_IDMAC_CH_PRI_1 0x00000014 179 #define IPU_IDMAC_CH_PRI_2 0x00000018 180 #define IPU_IDMAC_WM_EN_1 0x0000001c 181 #define IPU_IDMAC_WM_EN_2 0x00000020 182 #define IPU_IDMAC_LOCK_EN_1 0x00000024 183 #define IPU_IDMAC_LOCK_EN_2 0x00000028 184 #define IPU_IDMAC_SUB_ADDR_0 0x0000002c 185 #define IPU_IDMAC_SUB_ADDR_1 0x00000030 186 #define IPU_IDMAC_SUB_ADDR_2 0x00000034 187 #define IPU_IDMAC_SUB_ADDR_3 0x00000038 188 #define IPU_IDMAC_SUB_ADDR_4 0x0000003c 189 #define IPU_IDMAC_BNDM_EN_1 0x00000040 190 #define IPU_IDMAC_BNDM_EN_2 0x00000044 191 #define IPU_IDMAC_SC_CORD 0x00000048 192 #define IPU_IDMAC_SC_CORD1 0x0000004c 193 #define IPU_IDMAC_CH_BUSY_1 0x00000100 194 #define IPU_IDMAC_CH_BUSY_2 0x00000104 195 196 #define CH_PANNEL_BG 23 197 #define CH_PANNEL_FG 27 198 199 /* 200 * DP 201 * Display Port 202 */ 203 #define IPU_DP_DEBUG_CNT 0x000000bc 204 #define IPU_DP_DEBUG_STAT 0x000000c0 205 206 /* 207 * IC 208 * Image Converter 209 */ 210 #define IPU_IC_CONF 0x00000000 211 #define IPU_IC_PRP_ENC_RSC 0x00000004 212 #define IPU_IC_PRP_VF_RSC 0x00000008 213 #define IPU_IC_PP_RSC 0x0000000c 214 #define IPU_IC_CMBP_1 0x00000010 215 #define IPU_IC_CMBP_2 0x00000014 216 #define IPU_IC_IDMAC_1 0x00000018 217 #define IPU_IC_IDMAC_2 0x0000001c 218 #define IPU_IC_IDMAC_3 0x00000020 219 #define IPU_IC_IDMAC_4 0x00000024 220 221 /* 222 * CSI 223 * Camera Sensor Interface 224 */ 225 #define IPU_CSI0_SENS_CONF 0x00000000 226 #define IPU_CSI0_SENS_FRM_SIZE 0x00000004 227 #define IPU_CSI0_ACT_FRM_SIZE 0x00000008 228 #define IPU_CSI0_OUT_FRM_CTRL 0x0000000c 229 #define IPU_CSI0_TST_CTRL 0x00000010 230 #define IPU_CSI0_CCIR_CODE_1 0x00000014 231 #define IPU_CSI0_CCIR_CODE_2 0x00000018 232 #define IPU_CSI0_CCIR_CODE_3 0x0000001c 233 #define IPU_CSI0_DI 0x00000020 234 #define IPU_CSI0_SKIP 0x00000024 235 #define IPU_CSI0_CPD_CTRL 0x00000028 236 #define IPU_CSI0_CPD_OFFSET1 0x000000ec 237 #define IPU_CSI0_CPD_OFFSET2 0x000000f0 238 239 #define IPU_CSI1_SENS_CONF 0x00000000 240 #define IPU_CSI1_SENS_FRM_SIZE 0x00000004 241 #define IPU_CSI1_ACT_FRM_SIZE 0x00000008 242 #define IPU_CSI1_OUT_FRM_CTRL 0x0000000c 243 #define IPU_CSI1_TST_CTRL 0x00000010 244 #define IPU_CSI1_CCIR_CODE_1 0x00000014 245 #define IPU_CSI1_CCIR_CODE_2 0x00000018 246 #define IPU_CSI1_CCIR_CODE_3 0x0000001c 247 #define IPU_CSI1_DI 0x00000020 248 #define IPU_CSI1_SKIP 0x00000024 249 #define IPU_CSI1_CPD_CTRL 0x00000028 250 #define IPU_CSI1_CPD_OFFSET1 0x000000ec 251 #define IPU_CSI1_CPD_OFFSET2 0x000000f0 252 253 /* 254 * DI 255 * Display Interface 256 */ 257 #define IPU_DI_GENERAL 0x00000000 258 #define DI_GENERAL_DISP_Y_SEL __BITS(30, 28) 259 #define DI_GENERAL_CLOCK_STOP_MODE __BITS(27, 24) 260 #define DI_GENERAL_DISP_CLOCK_INIT __BIT(23) 261 #define DI_GENERAL_MASK_SEL __BIT(22) 262 #define DI_GENERAL_VSYNC_EXT __BIT(21) 263 #define DI_GENERAL_CLK_EXT __BIT(20) 264 #define DI_GENERAL_WATCHDOG_MODE __BITS(19, 18) 265 #define DI_GENERAL_POLARITY_DISP_CLK __BIT(17) 266 #define DI_GENERAL_SYNC_COUNT_SEL __BITS(15, 12) 267 #define DI_GENERAL_ERR_TREATMENT __BIT(11) 268 #define DI_GENERAL_ERM_VSYNC_SEL __BIT(10) 269 #define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8)) 270 #define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) 271 272 #define IPU_DI_BS_CLKGEN0 0x00000004 273 #define DI_BS_CLKGEN0_OFFSET_SHIFT 16 274 #define IPU_DI_BS_CLKGEN1 0x00000008 275 #define DI_BS_CLKGEN1_DOWN_SHIFT 16 276 #define DI_BS_CLKGEN1_UP_SHIFT 0 277 #define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4) 278 #define DI_SW_GEN0_RUN_VAL __BITS(30, 19) 279 #define DI_SW_GEN0_RUN_RESOL __BITS(18, 16) 280 #define DI_SW_GEN0_OFFSET_VAL __BITS(14, 3) 281 #define DI_SW_GEN0_OFFSET_RESOL __BITS( 2, 0) 282 #define __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol) \ 283 (((run_val) << 19) | ((run_resol) << 16) | \ 284 ((offset_val) << 3) | (offset_resol)) 285 #define IPU_DI_SW_GEN1(n) (0x00000030 + ((n) - 1) * 4) 286 #define DI_SW_GEN1_CNT_POL_GEN_EN __BITS(30, 29) 287 #define DI_SW_GEN1_CNT_AUTO_RELOAD __BIT(28) 288 #define DI_SW_GEN1_CNT_CLR_SEL __BITS(27, 25) 289 #define DI_SW_GEN1_CNT_DOWN __BITS(24, 16) 290 #define DI_SW_GEN1_CNT_POL_TRIG_SEL __BITS(14, 12) 291 #define DI_SW_GEN1_CNT_POL_CLR_SEL __BITS(11, 9) 292 #define DI_SW_GEN1_CNT_UP __BITS( 8, 0) 293 #define __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \ 294 (((pol_gen_en) << 29) | ((auto_reload) << 28) | \ 295 ((clr_sel) << 25) | \ 296 ((down) << 16) | ((pol_trig_sel) << 12) | \ 297 ((pol_clr_sel) << 9) | (up)) 298 #define IPU_DI_SYNC_AS_GEN 0x00000054 299 #define DI_SYNC_AS_GEN_SYNC_START_EN __BIT(28) 300 #define DI_SYNC_AS_GEN_VSYNC_SEL __BITS(15, 13) 301 #define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13 302 #define DI_SYNC_AS_GEN_SYNC_STAR __BITS(11, 0) 303 #define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) 304 #define DI_DW_GEN_ACCESS_SIZE_SHIFT 24 305 #define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16 306 #define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2) 307 #define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ 308 DI_DW_GEN_PIN_SHIFT(n)) 309 #define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) 310 #define DI_DW_SET_DOWN_SHIFT 16 311 #define DI_DW_SET_UP_SHIFT 0 312 #define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) 313 #define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16) 314 #define DI_STP_REP_MASK(n) (__BITS(11, 0) << DI_STP_REP_SHIFT((n))) 315 #define IPU_DI_SER_CONF 0x0000015c 316 #define IPU_DI_SSC 0x00000160 317 #define IPU_DI_POL 0x00000164 318 #define DI_POL_DRDY_POLARITY_17 __BIT(6) 319 #define DI_POL_DRDY_POLARITY_16 __BIT(5) 320 #define DI_POL_DRDY_POLARITY_15 __BIT(4) 321 #define DI_POL_DRDY_POLARITY_14 __BIT(3) 322 #define DI_POL_DRDY_POLARITY_13 __BIT(2) 323 #define DI_POL_DRDY_POLARITY_12 __BIT(1) 324 #define DI_POL_DRDY_POLARITY_11 __BIT(0) 325 #define IPU_DI_AW0 0x00000168 326 #define IPU_DI_AW1 0x0000016c 327 #define IPU_DI_SCR_CONF 0x00000170 328 #define IPU_DI_STAT 0x00000174 329 330 /* 331 * SMFC 332 * Sensor Multi FIFO Controller 333 */ 334 #define IPU_SMFC_MAP 0x00000000 335 #define IPU_SMFC_WMC 0x00000004 336 #define IPU_SMFC_BS 0x00000008 337 338 /* 339 * DC 340 * Display Controller 341 */ 342 #define IPU_DC_READ_CH_CONF 0x00000000 343 #define IPU_DC_READ_CH_ADDR 0x00000004 344 345 #define IPU_DC_RL0_CH_0 0x00000008 346 #define IPU_DC_RL1_CH_0 0x0000000c 347 #define IPU_DC_RL2_CH_0 0x00000010 348 #define IPU_DC_RL3_CH_0 0x00000014 349 #define IPU_DC_RL4_CH_0 0x00000018 350 #define IPU_DC_WR_CH_CONF_1 0x0000001c 351 #define IPU_DC_WR_CH_ADDR_1 0x00000020 352 #define IPU_DC_RL0_CH_1 0x00000024 353 #define IPU_DC_RL1_CH_1 0x00000028 354 #define IPU_DC_RL2_CH_1 0x0000002c 355 #define IPU_DC_RL3_CH_1 0x00000030 356 #define IPU_DC_RL4_CH_1 0x00000034 357 #define IPU_DC_WR_CH_CONF_2 0x00000038 358 #define IPU_DC_WR_CH_ADDR_2 0x0000003c 359 #define IPU_DC_RL0_CH_2 0x00000040 360 #define IPU_DC_RL1_CH_2 0x00000044 361 #define IPU_DC_RL2_CH_2 0x00000048 362 #define IPU_DC_RL3_CH_2 0x0000004c 363 #define IPU_DC_RL4_CH_2 0x00000050 364 #define IPU_DC_CMD_CH_CONF_3 0x00000054 365 #define IPU_DC_CMD_CH_CONF_4 0x00000058 366 #define IPU_DC_WR_CH_CONF_5 0x0000005c 367 #define IPU_DC_WR_CH_ADDR_5 0x00000060 368 #define IPU_DC_RL0_CH_5 0x00000064 369 #define IPU_DC_RL1_CH_5 0x00000068 370 #define IPU_DC_RL2_CH_5 0x0000006c 371 #define IPU_DC_RL3_CH_5 0x00000070 372 #define IPU_DC_RL4_CH_5 0x00000074 373 #define IPU_DC_WR_CH_CONF_6 0x00000078 374 #define IPU_DC_WR_CH_ADDR_6 0x0000007c 375 #define IPU_DC_RL0_CH_6 0x00000080 376 #define IPU_DC_RL1_CH_6 0x00000084 377 #define IPU_DC_RL2_CH_6 0x00000088 378 #define IPU_DC_RL3_CH_6 0x0000008c 379 #define IPU_DC_RL4_CH_6 0x00000090 380 #define IPU_DC_WR_CH_CONF1_8 0x00000094 381 #define IPU_DC_WR_CH_CONF2_8 0x00000098 382 #define IPU_DC_RL1_CH_8 0x0000009c 383 #define IPU_DC_RL2_CH_8 0x000000a0 384 #define IPU_DC_RL3_CH_8 0x000000a4 385 #define IPU_DC_RL4_CH_8 0x000000a8 386 #define IPU_DC_RL5_CH_8 0x000000ac 387 #define IPU_DC_RL6_CH_8 0x000000b0 388 #define IPU_DC_WR_CH_CONF1_9 0x000000b4 389 #define IPU_DC_WR_CH_CONF2_9 0x000000b8 390 #define IPU_DC_RL1_CH_9 0x000000bc 391 #define IPU_DC_RL2_CH_9 0x000000c0 392 #define IPU_DC_RL3_CH_9 0x000000c4 393 #define IPU_DC_RL4_CH_9 0x000000c8 394 #define IPU_DC_RL5_CH_9 0x000000cc 395 #define IPU_DC_RL6_CH_9 0x000000d0 396 397 #define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4) 398 #define DC_RL_CH_0 IPU_DC_RL0_CH_0 399 #define DC_RL_CH_1 IPU_DC_RL0_CH_1 400 #define DC_RL_CH_2 IPU_DC_RL0_CH_2 401 #define DC_RL_CH_5 IPU_DC_RL0_CH_5 402 #define DC_RL_CH_6 IPU_DC_RL0_CH_6 403 #define DC_RL_CH_8 IPU_DC_RL0_CH_8 404 405 #define DC_RL_EVT_NF 0 406 #define DC_RL_EVT_NL 1 407 #define DC_RL_EVT_EOF 2 408 #define DC_RL_EVT_NFIELD 3 409 #define DC_RL_EVT_EOL 4 410 #define DC_RL_EVT_EOFIELD 5 411 #define DC_RL_EVT_NEW_ADDR 6 412 #define DC_RL_EVT_NEW_CHAN 7 413 #define DC_RL_EVT_NEW_DATA 8 414 415 #define IPU_DC_GEN 0x000000d4 416 #define IPU_DC_DISP_CONF1_0 0x000000d8 417 #define IPU_DC_DISP_CONF1_1 0x000000dc 418 #define IPU_DC_DISP_CONF1_2 0x000000e0 419 #define IPU_DC_DISP_CONF1_3 0x000000e4 420 #define IPU_DC_DISP_CONF2_0 0x000000e8 421 #define IPU_DC_DISP_CONF2_1 0x000000ec 422 #define IPU_DC_DISP_CONF2_2 0x000000f0 423 #define IPU_DC_DISP_CONF2_3 0x000000f4 424 #define IPU_DC_DI0_CONF_1 0x000000f8 425 #define IPU_DC_DI0_CONF_2 0x000000fc 426 #define IPU_DC_DI1_CONF_1 0x00000100 427 #define IPU_DC_DI1_CONF_2 0x00000104 428 429 #define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4) 430 #define IPU_DC_MAP_CONF_0 0x00000108 431 #define IPU_DC_MAP_CONF_1 0x0000010c 432 #define IPU_DC_MAP_CONF_2 0x00000110 433 #define IPU_DC_MAP_CONF_3 0x00000114 434 #define IPU_DC_MAP_CONF_4 0x00000118 435 #define IPU_DC_MAP_CONF_5 0x0000011c 436 #define IPU_DC_MAP_CONF_6 0x00000120 437 #define IPU_DC_MAP_CONF_7 0x00000124 438 #define IPU_DC_MAP_CONF_8 0x00000128 439 #define IPU_DC_MAP_CONF_9 0x0000012c 440 #define IPU_DC_MAP_CONF_10 0x00000130 441 #define IPU_DC_MAP_CONF_11 0x00000134 442 #define IPU_DC_MAP_CONF_12 0x00000138 443 #define IPU_DC_MAP_CONF_13 0x0000013c 444 #define IPU_DC_MAP_CONF_14 0x00000140 445 446 #define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4) 447 #define IPU_DC_MAP_CONF_15 0x00000144 448 #define IPU_DC_MAP_CONF_16 0x00000148 449 #define IPU_DC_MAP_CONF_17 0x0000014c 450 #define IPU_DC_MAP_CONF_18 0x00000150 451 #define IPU_DC_MAP_CONF_19 0x00000154 452 #define IPU_DC_MAP_CONF_20 0x00000158 453 #define IPU_DC_MAP_CONF_21 0x0000015c 454 #define IPU_DC_MAP_CONF_22 0x00000160 455 #define IPU_DC_MAP_CONF_23 0x00000164 456 #define IPU_DC_MAP_CONF_24 0x00000168 457 #define IPU_DC_MAP_CONF_25 0x0000016c 458 #define IPU_DC_MAP_CONF_26 0x00000170 459 460 #define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4) 461 #define IPU_DC_UGDE0_0 0x00000174 462 #define IPU_DC_UGDE0_1 0x00000178 463 #define IPU_DC_UGDE0_2 0x0000017c 464 #define IPU_DC_UGDE0_3 0x00000180 465 #define IPU_DC_UGDE1_0 0x00000184 466 #define IPU_DC_UGDE1_1 0x00000188 467 #define IPU_DC_UGDE1_2 0x0000018c 468 #define IPU_DC_UGDE1_3 0x00000190 469 #define IPU_DC_UGDE2_0 0x00000194 470 #define IPU_DC_UGDE2_1 0x00000198 471 #define IPU_DC_UGDE2_2 0x0000019c 472 #define IPU_DC_UGDE2_3 0x000001a0 473 #define IPU_DC_UGDE3_0 0x000001a4 474 #define IPU_DC_UGDE3_1 0x000001a8 475 #define IPU_DC_UGDE3_2 0x000001ac 476 #define IPU_DC_UGDE3_3 0x000001b0 477 #define IPU_DC_LLA0 0x000001b4 478 #define IPU_DC_LLA1 0x000001b8 479 #define IPU_DC_R_LLA0 0x000001bc 480 #define IPU_DC_R_LLA1 0x000001c0 481 #define IPU_DC_WR_CH_ADDR_5_ALT 0x000001c4 482 #define IPU_DC_STAT 0x000001c8 483 484 /* 485 * DMFC 486 * Display Multi FIFO Controller 487 */ 488 #define IPU_DMFC_RD_CHAN 0x00000000 489 #define DMFC_RD_CHAN_PPW_C __BITS(25,24) 490 #define DMFC_RD_CHAN_WM_DR_0 __BITS(23,21) 491 #define DMFC_RD_CHAN_WM_SET_0 __BITS(20,18) 492 #define DMFC_RD_CHAN_WM_EN_0 __BIT(17) 493 #define DMFC_RD_CHAN_BURST_SIZE_0 __BITS( 7, 6) 494 #define IPU_DMFC_WR_CHAN 0x00000004 495 #define DMFC_WR_CHAN_BUSRT_SIZE_2C __BITS(31,30) 496 #define DMFC_WR_CHAN_FIFO_SIZE_2C __BITS(29,27) 497 #define DMFC_WR_CHAN_ST_ADDR_2C __BITS(26,24) 498 #define DMFC_WR_CHAN_BURST_SIZE_1C __BITS(23,22) 499 #define DMFC_WR_CHAN_FIFO_SIZE_1C __BITS(21,19) 500 #define DMFC_WR_CHAN_ST_ADDR_1C __BITS(18,16) 501 #define DMFC_WR_CHAN_BURST_SIZE_2 __BITS(15,14) 502 #define DMFC_WR_CHAN_FIFO_SIZE_2 __BITS(13,11) 503 #define DMFC_WR_CHAN_ST_ADDR_2 __BITS(10, 8) 504 #define DMFC_WR_CHAN_BURST_SIZE_1 __BITS( 7, 6) 505 #define DMFC_WR_CHAN_FIFO_SIZE_1 __BITS( 5, 3) 506 #define DMFC_WR_CHAN_ST_ADDR_1 __BITS( 2, 0) 507 #define IPU_DMFC_WR_CHAN_DEF 0x00000008 508 #define DMFC_WR_CHAN_DEF_WM_CLR_2C __BITS(31,29) 509 #define DMFC_WR_CHAN_DEF_WM_SET_2C __BITS(28,26) 510 #define DMFC_WR_CHAN_DEF_WM_EN_2C __BIT(25) 511 #define DMFC_WR_CHAN_DEF_WM_CLR_1C __BITS(23,21) 512 #define DMFC_WR_CHAN_DEF_WM_SET_1C __BITS(20,18) 513 #define DMFC_WR_CHAN_DEF_WM_EN_1C __BIT(17) 514 #define DMFC_WR_CHAN_DEF_WM_CLR_2 __BITS(15,13) 515 #define DMFC_WR_CHAN_DEF_WM_SET_2 __BITS(12,10) 516 #define DMFC_WR_CHAN_DEF_WM_EN_2 __BIT(9) 517 #define DMFC_WR_CHAN_DEF_WM_CLR_1 __BITS( 7, 5) 518 #define DMFC_WR_CHAN_DEF_WM_SET_1 __BITS( 3, 2) 519 #define DMFC_WR_CHAN_DEF_WM_EN_1 __BIT(1) 520 #define IPU_DMFC_DP_CHAN 0x0000000c 521 #define DMFC_DP_CHAN_BUSRT_SIZE_6F __BITS(31,30) 522 #define DMFC_DP_CHAN_FIFO_SIZE_6F __BITS(29,27) 523 #define DMFC_DP_CHAN_ST_ADDR_6F __BITS(26,24) 524 #define DMFC_DP_CHAN_BURST_SIZE_6B __BITS(23,22) 525 #define DMFC_DP_CHAN_FIFO_SIZE_6B __BITS(21,19) 526 #define DMFC_DP_CHAN_ST_ADDR_6B __BITS(18,16) 527 #define DMFC_DP_CHAN_BURST_SIZE_5F __BITS(15,14) 528 #define DMFC_DP_CHAN_FIFO_SIZE_5F __BITS(13,11) 529 #define DMFC_DP_CHAN_ST_ADDR_5F __BITS(10, 8) 530 #define DMFC_DP_CHAN_BURST_SIZE_5B __BITS( 7, 6) 531 #define DMFC_DP_CHAN_FIFO_SIZE_5B __BITS( 5, 3) 532 #define DMFC_DP_CHAN_ST_ADDR_5B __BITS( 2, 0) 533 #define IPU_DMFC_DP_CHAN_DEF 0x00000010 534 #define DMFC_DP_CHAN_DEF_WM_CLR_6F __BITS(31,29) 535 #define DMFC_DP_CHAN_DEF_WM_SET_6F __BITS(28,26) 536 #define DMFC_DP_CHAN_DEF_WM_EN_6F __BIT(25) 537 #define DMFC_DP_CHAN_DEF_WM_CLR_6B __BITS(23,21) 538 #define DMFC_DP_CHAN_DEF_WM_SET_6B __BITS(20,18) 539 #define DMFC_DP_CHAN_DEF_WM_EN_6B __BIT(17) 540 #define DMFC_DP_CHAN_DEF_WM_CLR_5F __BITS(15,13) 541 #define DMFC_DP_CHAN_DEF_WM_SET_5F __BITS(12,10) 542 #define DMFC_DP_CHAN_DEF_WM_EN_5F __BIT(9) 543 #define DMFC_DP_CHAN_DEF_WM_CLR_5B __BITS( 7, 5) 544 #define DMFC_DP_CHAN_DEF_WM_SET_5B __BITS( 4, 2) 545 #define DMFC_DP_CHAN_DEF_WM_EN_5B __BIT(1) 546 #define IPU_DMFC_GENERAL1 0x00000014 547 #define DMFC_GENERAL1_WAIT4EOT_9 __BIT(24) 548 #define DMFC_GENERAL1_WAIT4EOT_6F __BIT(23) 549 #define DMFC_GENERAL1_WAIT4EOT_6B __BIT(22) 550 #define DMFC_GENERAL1_WAIT4EOT_5F __BIT(21) 551 #define DMFC_GENERAL1_WAIT4EOT_5B __BIT(20) 552 #define DMFC_GENERAL1_WAIT4EOT_4 __BIT(19) 553 #define DMFC_GENERAL1_WAIT4EOT_3 __BIT(18) 554 #define DMFC_GENERAL1_WAIT4EOT_2 __BIT(17) 555 #define DMFC_GENERAL1_WAIT4EOT_1 __BIT(16) 556 #define DMFC_GENERAL1_WM_CLR_9 __BITS(15,13) 557 #define DMFC_GENERAL1_WM_SET_9 __BITS(12,10) 558 #define DMFC_GENERAL1_BURST_SIZE_9 __BITS( 6, 5) 559 #define DMFC_GENERAL1_DCDP_SYNC_PR __BITS( 1, 0) 560 #define DCDP_SYNC_PR_FORBIDDEN 0 561 #define DCDP_SYNC_PR_DC_DP 1 562 #define DCDP_SYNC_PR_DP_DC 2 563 #define DCDP_SYNC_PR_ROUNDROBIN 3 564 #define IPU_DMFC_GENERAL2 0x00000018 565 #define DMFC_GENERAL2_FRAME_HEIGHT_RD __BITS(28,16) 566 #define DMFC_GENERAL2_FRAME_WIDTH_RD __BITS(12, 0) 567 #define IPU_DMFC_IC_CTRL 0x0000001c 568 #define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD __BITS(31,19) 569 #define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD __BITS(18, 6) 570 #define DMFC_IC_CTRL_IC_PPW_C __BITS( 5, 4) 571 #define DMFC_IC_CTRL_IC_IN_PORT __BITS( 2, 0) 572 #define IC_IN_PORT_CH28 0 573 #define IC_IN_PORT_CH41 1 574 #define IC_IN_PORT_DISABLE 2 575 #define IC_IN_PORT_CH23 4 576 #define IC_IN_PORT_CH27 5 577 #define IC_IN_PORT_CH24 6 578 #define IC_IN_PORT_CH29 7 579 #define IPU_DMFC_WR_CHAN_ALT 0x00000020 580 #define IPU_DMFC_WR_CHAN_DEF_ALT 0x00000024 581 #define IPU_DMFC_DP_CHAN_ALT 0x00000028 582 #define IPU_DMFC_DP_CHAN_DEF_ALT 0x0000002c 583 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT __BITS(31,29) 584 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT __BITS(28,26) 585 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT __BIT(25) 586 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT __BITS(23,21) 587 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT __BITS(20,18) 588 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT __BIT(17) 589 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT __BITS( 7, 5) 590 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT __BITS( 4, 2) 591 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT __BIT(1) 592 #define IPU_DMFC_GENERAL1_ALT 0x00000030 593 #define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT __BIT(23) 594 #define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT __BIT(22) 595 #define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT __BIT(20) 596 #define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT __BIT(17) 597 #define IPU_DMFC_STAT 0x00000034 598 #define DMFC_STAT_IC_BUFFER_EMPTY __BIT(25) 599 #define DMFC_STAT_IC_BUFFER_FULL __BIT(24) 600 #define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) 601 #define DMFC_STAT_FIFO_FULL(n) __BIT((n)) 602 603 /* 604 * VCI 605 * Video De Interkacing Module 606 */ 607 #define IPU_VDI_FSIZE 0x00000000 608 #define IPU_VDI_C 0x00000004 609 610 /* 611 * DP 612 * Display Processor 613 */ 614 #define IPU_DP_COM_CONF_SYNC 0x00000000 615 #define DP_FG_EN_SYNC __BIT(0) 616 #define DP_DP_GWAM_SYNC __BIT(2) 617 #define IPU_DP_GRAPH_WIND_CTRL_SYNC 0x00000004 618 #define IPU_DP_FG_POS_SYNC 0x00000008 619 #define IPU_DP_CUR_POS_SYNC 0x0000000c 620 #define IPU_DP_CUR_MAP_SYNC 0x00000010 621 #define IPU_DP_CSC_SYNC_0 0x00000054 622 #define IPU_DP_CSC_SYNC_1 0x00000058 623 #define IPU_DP_CUR_POS_ALT 0x0000005c 624 #define IPU_DP_COM_CONF_ASYNC0 0x00000060 625 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC0 0x00000064 626 #define IPU_DP_FG_POS_ASYNC0 0x00000068 627 #define IPU_DP_CUR_POS_ASYNC0 0x0000006c 628 #define IPU_DP_CUR_MAP_ASYNC0 0x00000070 629 #define IPU_DP_CSC_ASYNC0_0 0x000000b4 630 #define IPU_DP_CSC_ASYNC0_1 0x000000b8 631 #define IPU_DP_COM_CONF_ASYNC1 0x000000bc 632 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC1 0x000000c0 633 #define IPU_DP_FG_POS_ASYNC1 0x000000c4 634 #define IPU_DP_CUR_POS_ASYNC1 0x000000c8 635 #define IPU_DP_CUR_MAP_ASYNC1 0x000000cc 636 #define IPU_DP_CSC_ASYNC1_0 0x00000110 637 #define IPU_DP_CSC_ASYNC1_1 0x00000114 638 639 /* IDMA parameter */ 640 /* 641 * non-Interleaved parameter 642 * 643 * param 0: XV W0[ 9: 0] 644 * YV W0[18:10] 645 * XB W0[31:19] 646 * param 1: YB W0[43:32] 647 * NSB W0[44] 648 * CF W0[45] 649 * UBO W0[61:46] 650 * param 2: UBO W0[67:62] 651 * VBO W0[89:68] 652 * IOX W0[93:90] 653 * RDRW W0[94] 654 * Reserved W0[95] 655 * param 3: Reserved W0[112:96] 656 * S0 W0[113] 657 * BNDM W0[116:114] 658 * BM W0[118:117] 659 * ROT W0[119] 660 * HF W0[120] 661 * VF W0[121] 662 * THF W0[122] 663 * CAP W0[123] 664 * CAE W0[124] 665 * FW W0[127:125] 666 * param 4: FW W0[137:128] 667 * FH W0[149:138] 668 * param 5: EBA0 W1[28:0] 669 * EBA1 W1[31:29] 670 * param 6: EBA1 W1[57:32] 671 * ILO W1[63:58] 672 * param 7: ILO W1[77:64] 673 * NPB W1[84:78] 674 * PFS W1[88:85] 675 * ALU W1[89] 676 * ALBM W1[92:90] 677 * ID W1[94:93] 678 * TH W1[95] 679 * param 8: TH W1[101:96] 680 * SLY W1[115:102] 681 * WID3 W1[127:125] 682 * param 9: SLUV W1[141:128] 683 * CRE W1[149] 684 * 685 * Interleaved parameter 686 * 687 * param 0: XV W0[ 9: 0] 688 * YV W0[18:10] 689 * XB W0[31:19] 690 * param 1: YB W0[43:32] 691 * NSB W0[44] 692 * CF W0[45] 693 * SX W0[57:46] 694 * SY W0[61:58] 695 * param 2: SY W0[68:62] 696 * NS W0[78:69] 697 * SDX W0[85:79] 698 * SM W0[95:86] 699 * param 3: SCC W0[96] 700 * SCE W0[97] 701 * SDY W0[104:98] 702 * SDRX W0[105] 703 * SDRY W0[106] 704 * BPP W0[109:107] 705 * DEC_SEL W0[111:110] 706 * DIM W0[112] 707 * SO W0[113] 708 * BNDM W0[116:114] 709 * BM W0[118:117] 710 * ROT W0[119] 711 * HF W0[120] 712 * VF W0[121] 713 * THF W0[122] 714 * CAP W0[123] 715 * CAE W0[124] 716 * FW W0[127:125] 717 * param 4: FW W0[137:128] 718 * FH W0[149:138] 719 * param 5: EBA0 W1[28:0] 720 * EBA1 W1[31:29] 721 * param 6: EBA1 W1[57:32] 722 * ILO W1[63:58] 723 * param 7: ILO W1[77:64] 724 * NPB W1[84:78] 725 * PFS W1[88:85] 726 * ALU W1[89] 727 * ALBM W1[92:90] 728 * ID W1[94:93] 729 * TH W1[95] 730 * param 8: TH W1[101:96] 731 * SL W1[115:102] 732 * WID0 W1[118:116] 733 * WID1 W1[121:119] 734 * WID2 W1[124:122] 735 * WID3 W1[127:125] 736 * param 9: OFS0 W1[132:128] 737 * OFS1 W1[137:133] 738 * OFS2 W1[142:138] 739 * OFS3 W1[147:143] 740 * SXYS W1[148] 741 * CRE W1[149] 742 * DEC_SEL2 W1[150] 743 */ 744 745 #define __IDMA_PARAM(word, shift, size) \ 746 ((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff)) 747 748 /* non-Interleaved parameter */ 749 /* W0 */ 750 #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) 751 #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) 752 #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) 753 #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) 754 #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) 755 #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) 756 #define IDMAC_Ch_PARAM_UBO __IDMA_PARAM(0, 46, 22) 757 #define IDMAC_Ch_PARAM_VBO __IDMA_PARAM(0, 68, 22) 758 #define IDMAC_Ch_PARAM_IOX __IDMA_PARAM(0, 90, 4) 759 #define IDMAC_Ch_PARAM_RDRW __IDMA_PARAM(0, 94, 1) 760 #define IDMAC_Ch_PARAM_S0 __IDMA_PARAM(0,113, 1) 761 #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) 762 #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) 763 #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) 764 #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) 765 #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) 766 #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) 767 #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) 768 #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) 769 #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) 770 #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) 771 /* W1 */ 772 #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) 773 #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) 774 #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) 775 #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) 776 #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) 777 #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) 778 #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) 779 #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) 780 #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) 781 #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) 782 #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) 783 #define IDMAC_Ch_PARAM_SLUV __IDMA_PARAM(1,128, 14) 784 #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) 785 786 /* Interleaved parameter */ 787 /* W0 */ 788 #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) 789 #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) 790 #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) 791 #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) 792 #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) 793 #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) 794 #define IDMAC_Ch_PARAM_SX __IDMA_PARAM(0, 46, 12) 795 #define IDMAC_Ch_PARAM_SY __IDMA_PARAM(0, 58, 11) 796 #define IDMAC_Ch_PARAM_NS __IDMA_PARAM(0, 69, 10) 797 #define IDMAC_Ch_PARAM_SDX __IDMA_PARAM(0, 79, 7) 798 #define IDMAC_Ch_PARAM_SM __IDMA_PARAM(0, 86, 10) 799 #define IDMAC_Ch_PARAM_SCC __IDMA_PARAM(0, 96, 1) 800 #define IDMAC_Ch_PARAM_SCE __IDMA_PARAM(0, 97, 1) 801 #define IDMAC_Ch_PARAM_SDY __IDMA_PARAM(0, 98, 7) 802 #define IDMAC_Ch_PARAM_SDRX __IDMA_PARAM(0,105, 1) 803 #define IDMAC_Ch_PARAM_SDRY __IDMA_PARAM(0,106, 1) 804 #define IDMAC_Ch_PARAM_BPP __IDMA_PARAM(0,107, 3) 805 #define IDMAC_Ch_PARAM_DEC_SEL __IDMA_PARAM(0,110, 2) 806 #define IDMAC_Ch_PARAM_DIM __IDMA_PARAM(0,112, 1) 807 #define IDMAC_Ch_PARAM_SO __IDMA_PARAM(0,113, 1) 808 #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) 809 #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) 810 #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) 811 #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) 812 #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) 813 #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) 814 #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) 815 #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) 816 #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) 817 #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) 818 /* W1 */ 819 #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) 820 #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) 821 #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) 822 #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) 823 #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) 824 #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) 825 #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) 826 #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) 827 #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) 828 #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) 829 #define IDMAC_Ch_PARAM_WID0 __IDMA_PARAM(1,116, 3) 830 #define IDMAC_Ch_PARAM_WID1 __IDMA_PARAM(1,119, 3) 831 #define IDMAC_Ch_PARAM_WID2 __IDMA_PARAM(1,122, 3) 832 #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) 833 #define IDMAC_Ch_PARAM_OFS0 __IDMA_PARAM(1,128, 5) 834 #define IDMAC_Ch_PARAM_OFS1 __IDMA_PARAM(1,133, 5) 835 #define IDMAC_Ch_PARAM_OFS2 __IDMA_PARAM(1,138, 5) 836 #define IDMAC_Ch_PARAM_OFS3 __IDMA_PARAM(1,143, 5) 837 #define IDMAC_Ch_PARAM_SXYS __IDMA_PARAM(1,148, 1) 838 #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) 839 #define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150, 1) 840 841 #endif /* _ARM_IMX_IMX51_IPUV3REG_H */ 842