1 /* $NetBSD: imx51_dpllreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ 2 /* 3 * Copyright (c) 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _IMX51_DPLLREG_H 28 #define _IMX51_DPLLREG_H 29 30 #include <sys/cdefs.h> 31 32 /* register offset address */ 33 34 #define IMX51_N_DPLLS 3 /* 1..3 */ 35 36 #define DPLL_BASE(n) (0x83F80000 + (0x4000 * ((n)-1))) 37 #define DPLL_SIZE 0x100 38 39 #define DPLL_DP_CTL 0x0000 40 #define DP_CTL_HFSM __BIT(7) 41 #define DP_CTL_REF_CLK_SEL_MASK __BITS(8,9) 42 #define DP_CTL_REF_CLK_SEL_COSC (__BIT(9)|0) 43 #define DP_CTL_REF_CLK_SEL_FPM (__BIT(9)|__BIT(8)) 44 #define DP_CTL_REF_CLK_DIV __BIT(10) 45 #define DP_CTL_DPDCK0_2_EN __BIT(12) 46 #define DPLL_DP_CONFIG 0x0004 47 #define DPLL_DP_OP 0x0008 48 #define DP_OP_PDF_SHIFT 0 49 #define DP_OP_PDF_MASK (0xf << DP_OP_PDF_SHIFT) 50 #define DP_OP_MFI_SHIFT 4 51 #define DP_OP_MFI_MASK (0xf << DP_OP_MFI_SHIFT) 52 #define DPLL_DP_MFD 0x000C 53 #define DPLL_DP_MFN 0x0010 54 #define DPLL_DP_MFNMINUS 0x0014 55 #define DPLL_DP_MFNPLUS 0x0018 56 #define DPLL_DP_HFS_OP 0x001C 57 #define DPLL_DP_HFS_MFD 0x0020 58 #define DPLL_DP_HFS_MFN 0x0024 59 #define DPLL_DP_TOGC 0x0028 60 #define DPLL_DP_DESTAT 0x002C 61 62 #endif /* _IMX51_DPLLREG_H */ 63