xref: /netbsd-src/sys/arch/arm/imx/imx51_clock.c (revision c2f76ff004a2cb67efe5b12d97bd3ef7fe89e18d)
1 /*	$NetBSD: imx51_clock.c,v 1.1 2010/11/13 06:51:37 bsh Exp $ */
2 /*
3  * Copyright (c) 2009  Genetec corp.  All rights reserved.
4  * Written by Hashimoto Kenichi for Genetec corp.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.1 2010/11/13 06:51:37 bsh Exp $");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/evcnt.h>
34 #include <sys/atomic.h>
35 #include <sys/time.h>
36 #include <sys/timetc.h>
37 
38 #include <sys/types.h>
39 #include <sys/device.h>
40 
41 #include <dev/clock_subr.h>
42 
43 #include <machine/intr.h>
44 #include <machine/bus.h>
45 
46 #include <arm/cpufunc.h>
47 
48 #include <arm/imx/imx51reg.h>
49 #include <arm/imx/imx51var.h>
50 #include <arm/imx/imxepitreg.h>
51 //#include <arm/imx/imx51_ccmvar.h> notyet
52 #include <arm/imx/imxclockvar.h>
53 
54 #include "imxccm.h"	/* if CCM driver is configured into the kernel */
55 #include "opt_imx51clk.h"
56 
57 
58 
59 static int imxclock_match(device_t, struct cfdata *, void *);
60 static void imxclock_attach(device_t, device_t, void *);
61 
62 struct imxclock_softc *epit1_sc = NULL;
63 struct imxclock_softc *epit2_sc = NULL;
64 
65 CFATTACH_DECL_NEW(imxclock, sizeof(struct imxclock_softc),
66     imxclock_match, imxclock_attach, NULL, NULL);
67 
68 static int
69 imxclock_match(device_t parent, struct cfdata *match, void *aux)
70 {
71 	struct axi_attach_args *aa = aux;
72 
73 	if ( (aa->aa_addr != EPIT1_BASE) &&
74 	     (aa->aa_addr != EPIT2_BASE) ) {
75 		return 0;
76 	}
77 
78 	return 2;
79 }
80 
81 static void
82 imxclock_attach(device_t parent, device_t self, void *aux)
83 {
84 	struct imxclock_softc *sc = device_private(self);
85 	struct axi_attach_args *aa = aux;
86 
87 	aprint_normal("\n");
88 
89 	sc->sc_dev = self;
90 	sc->sc_iot = aa->aa_iot;
91 	sc->sc_intr = aa->aa_irq;
92 
93 	KASSERT((sc->sc_intr == IRQ_EPIT1) || (sc->sc_intr == IRQ_EPIT2));
94 
95 	switch ( aa->aa_addr ) {
96 	case EPIT1_BASE:
97 		epit1_sc = sc;
98 		break;
99 	case EPIT2_BASE:
100 		epit2_sc = sc;
101 		break;
102 	default:
103 		panic("%s: invalid address %p", self->dv_xname, (void *)aa->aa_addr);
104 		break;
105 	}
106 
107 	if (bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size, 0, &sc->sc_ioh))
108 		panic("%s: Cannot map registers", device_xname(self));
109 }
110 
111 int
112 imxclock_get_timerfreq(struct imxclock_softc *sc)
113 {
114 	unsigned int ipg_freq;
115 #if NIMXCCM > 0
116 	struct imx51_clocks clk;
117 
118 	imx51_get_clocks(&clk);
119 
120 	ipg_freq = clk.ipg_clk;
121 #else
122 #ifndef	IMX51_IPGCLK_FREQ
123 #error	IMX51_IPGCLK_FREQ need to be defined.
124 #endif
125 	ipg_freq = IMX51_IPGCLK_FREQ;
126 #endif
127 
128 	return ipg_freq;
129 }
130 
131