1 /* $NetBSD: imx51_ccmreg.h,v 1.2 2012/09/01 00:07:32 matt Exp $ */ 2 /* 3 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _IMX51_CCMREG_H 28 #define _IMX51_CCMREG_H 29 30 #include <sys/cdefs.h> 31 32 /* register offset address */ 33 34 #define CCMC_BASE 0x73fd4000 35 #define CCMC_IMX6_BASE 0x020c4040 36 #define CCMC_CCR 0x0000 37 #define CCR_FPM_MULT __BIT(12) 38 #define CCR_COSC_EN __BIT(12) 39 #define CCMC_CCDR 0x0004 40 #define CCMC_CSR 0x0008 41 #define CCMC_CCSR 0x000c 42 #define CCSR_LP_APM __BIT(9) 43 #define CCSR_STEP_SEL_SHIFT 7 44 #define CCSR_STEP_SEL_MASK __BITS(8,CCSR_STEP_SEL_SHIFT) 45 #define CCSR_PLL2_DIV_PODF_SHIFT 5 46 #define CCSR_PLL2_DIV_PODF_MASK __BITS(6, CCSR_PLL2_DIV_PODF_SHIFT) 47 #define CCSR_PLL3_DIV_PODF_SHIFT 3 48 #define CCSR_PLL3_DIV_PODF_MASK __BITS(4, CCSR_PLL2_DIV_PODF_SHIFT) 49 #define CCSR_PLL1_SW_CLK_SEL __BIT(2) 50 #define CCSR_PLL2_SW_CLK_SEL __BIT(1) 51 #define CCSR_PLL3_SW_CLK_SEL __BIT(0) 52 #define CCMC_CACRR 0x0010 53 #define CCMC_CBCDR 0x0014 54 #define CBCDR_DDR_HIGH_FREQ_CLK_SEL __BIT(30) 55 #define CBCDR_DDR_CLK_PODF_SHIFT 27 56 #define CBCDR_DDR_CLK_PODF_MASK __BITS(29, CBCDR_DDR_CLK_PODF_SHIFT) 57 #define CDCDR_PERIPH_CLK2 __BITS(29, 27) 58 #define CBCDR_EMI_CLK_SEL __BIT(26) 59 #define CBCDR_PERIPH_CLK_SEL __BIT(25) 60 #define CBCDR_EMI_SLOW_PODF_SHIFT 22 61 #define CBCDR_EMI_SLOW_PODF_MASK __BITS(24, CBCDR_EMI_SLOW_PODF_SHIFT) 62 #define CBCDR_AXI_B_PODF_SHIFT 19 63 #define CBCDR_AXI_B_PODF_MASK __BITS(21, CBCDR_AXI_B_PODF_SHIFT) 64 #define CBCDR_AXI_A_PODF_SHIFT 16 65 #define CBCDR_AXI_A_PODF_MASK __BITS(28, CBCDR_AXI_A_PODF_SHIFT) 66 #define CBCDR_NFC_PODF_SHIFT 13 67 #define CBCDR_NFC_PODF_MASK __BITS(15, CBCDR_AXI_A_PODF_SHIFT) 68 #define CBCDR_AHB_PODF_SHIFT 10 69 #define CBCDR_AHB_PODF_MASK __BITS(12, CBCDR_AHB_PODF_SHIFT) 70 #define CBCDR_IPG_PODF_SHIFT 8 71 #define CBCDR_IPG_PODF_MASK __BITS(9, CBCDR_IPG_PODF_SHIFT) 72 #define CBCDR_PERCLK_PRED1_SHIFT 6 73 #define CBCDR_PERCLK_PRED1_MASK __BITS(7, CBCDR_PERCLK_PRED1_SHIFT) 74 #define CBCDR_PERCLK_PRED2_SHIFT 3 75 #define CBCDR_PERCLK_PRED2_MASK __BITS(5, CBCDR_PERCLK_PRED2_SHIFT) 76 #define CBCDR_PERCLK_PODF_SHIFT 0 77 #define CBCDR_PERCLK_PODF_MASK __BITS(2, CBCDR_PERCLK_PODF_SHIFT) 78 #define CCMC_CBCMR 0x0018 79 #define CBCMR_PERIPH_APM_SEL_SHIFT 12 80 #define CBCMR_PERIPH_APM_SEL_MASK __BITS(13, CBCMR_PERIPH_APM_SEL_SHIFT) 81 #define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6 82 #define CBCMR_IPU_HSP_CLK_SEL_MASK __BITS(7, CBCMR_IPU_HSP_CLK_SEL_SHIFT) 83 #define CBCMR_PERCLK_LP_APM_SEL __BIT(1) 84 #define CBCMR_PERCLK_IPG_SEL __BIT(0) 85 #define CCMC_CSCMR1 0x001c 86 #define CSCMR1_UART_CLK_SEL_SHIFT 24 87 #define CSCMR1_UART_CLK_SEL_MASK __BITS(25, CSCMR1_UART_CLK_SEL_SHIFT) 88 #define CCMC_CSCMR2 0x0020 89 #define CCMC_CSCDR1 0x0024 90 #define CSCDR1_UART_CLK_PRED_SHIFT 3 91 #define CSCDR1_UART_CLK_PRED_MASK __BITS(5, CSCDR1_UART_CLK_PRED_SHIFT) 92 #define CSCDR1_UART_CLK_PODF_SHIFT 0 93 #define CSCDR1_UART_CLK_PODF_MASK __BITS(2, CSCDR1_UART_CLK_PODF_SHIFT) 94 #define CCMC_CS1CDR 0x0028 95 #define CCMC_CS2CDR 0x002c 96 #define CCMC_CDCDR 0x0030 97 #define CCMC_CHSCCDR 0x0034 // i.MX6 98 #define CCMC_CSCDR2 0x0038 99 #define CCMC_CSCDR3 0x003c 100 #define CCMC_CSCDR4 0x0040 101 #define CCMC_CWDR 0x0044 102 #define CCMC_CDHIPR 0x0048 103 #define CCMC_CDCR 0x004c 104 #define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0 105 #define CDCR_PERIPH_CLK_DVFS_PODF_MASK \ 106 __BITS(1,CDCR_PERIPH_CLK_DVFS_PODF_SHIFT) 107 #define CCMC_CTOR 0x0050 108 #define CCMC_CLPCR 0x0054 109 #define CCMC_CISR 0x0058 110 #define CCMC_CIMR 0x005c 111 #define CCMC_CCOSR 0x0060 112 #define CCMC_CGPR 0x0064 113 #define CCMC_CCGR(n) (0x0068 + (n) * 4) 114 #define CCMC_CMEOR 0x0084 115 116 #define CCMC_SIZE 0x88 117 118 /* CCGR Clock Gate Register */ 119 120 #define CCMR_CCGR_NSOURCE 16 121 #define CCMR_CCGR_NGROUPS 7 122 #define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) 123 #define __CCGR_NUM(a, b) ((a) * 16 + (b)) 124 125 #define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) 126 #define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) 127 #define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) 128 #define CCGR_TZIC_CLK __CCGR_NUM(0, 3) 129 #define CCGR_DAP_CLK __CCGR_NUM(0, 4) 130 #define CCGR_TPIU_CLK __CCGR_NUM(0, 5) 131 #define CCGR_CTI2_CLK __CCGR_NUM(0, 6) 132 #define CCGR_CTI3_CLK __CCGR_NUM(0, 7) 133 #define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) 134 #define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) 135 #define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) 136 #define CCGR_ROM_CLK __CCGR_NUM(0, 11) 137 #define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) 138 #define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) 139 #define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) 140 #define CCGR_IIM_CLK __CCGR_NUM(0, 15) 141 #define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) 142 #define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) 143 #define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) 144 #define CCGR_UART1_CLK __CCGR_NUM(1, 3) 145 #define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) 146 #define CCGR_UART2_CLK __CCGR_NUM(1, 5) 147 #define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) 148 #define CCGR_UART3_CLK __CCGR_NUM(1, 7) 149 #define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) 150 #define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) 151 #define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) 152 #define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) 153 #define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) 154 #define CCGR_FIRI_CLK __CCGR_NUM(1, 13) 155 #define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) 156 #define CCGR_SCC_CLK __CCGR_NUM(1, 15) 157 #define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) 158 #define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) 159 #define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) 160 #define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) 161 #define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) 162 #define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1) 163 #define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2) 164 #define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3) 165 #define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4) 166 #define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5) 167 #define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6) 168 #define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7) 169 #define CCGR_SSI1_CLK __CCGR_NUM(3, 8) 170 #define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9) 171 #define CCGR_SSI2_CLK __CCGR_NUM(3, 10) 172 #define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11) 173 #define CCGR_SSI3_CLK __CCGR_NUM(3, 12) 174 #define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13) 175 #define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14) 176 #define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15) 177 #define CCGR_PATA_CLK __CCGR_NUM(4, 0) 178 #define CCGR_SIM_CLK __CCGR_NUM(4, 1) 179 #define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2) 180 #define CCGR_SAHARA_CLK __CCGR_NUM(4, 3) 181 #define CCGR_RTIC_CLK __CCGR_NUM(4, 4) 182 #define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5) 183 #define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6) 184 #define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7) 185 #define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8) 186 #define CCGR_CSPI_CLK __CCGR_NUM(4, 9) 187 #define CCGR_SRTC_CLK __CCGR_NUM(4, 10) 188 #define CCGR_SDMA_CLK __CCGR_NUM(4, 11) 189 #define CCGR_SPBA_CLK __CCGR_NUM(5, 0) 190 #define CCGR_GPU_CLK __CCGR_NUM(5, 1) 191 #define CCGR_GARB_CLK __CCGR_NUM(5, 2) 192 #define CCGR_VPU_CLK __CCGR_NUM(5, 3) 193 #define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4) 194 #define CCGR_IPU_CLK __CCGR_NUM(5, 5) 195 #define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0) 196 #define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1) 197 #define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2) 198 #define CCGR_GPU2D_CLK __CCGR_NUM(6, 3) 199 #define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4) 200 #define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5) 201 202 #endif /* _IMX51_CCMREG_H */ 203 204