15a80dc5fSbsh /*
25a80dc5fSbsh * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
35a80dc5fSbsh * Written by Hiroyuki Bessho for Genetec Corporation.
45a80dc5fSbsh *
55a80dc5fSbsh * Redistribution and use in source and binary forms, with or without
65a80dc5fSbsh * modification, are permitted provided that the following conditions
75a80dc5fSbsh * are met:
85a80dc5fSbsh * 1. Redistributions of source code must retain the above copyright
95a80dc5fSbsh * notice, this list of conditions and the following disclaimer.
105a80dc5fSbsh * 2. Redistributions in binary form must reproduce the above copyright
115a80dc5fSbsh * notice, this list of conditions and the following disclaimer in the
125a80dc5fSbsh * documentation and/or other materials provided with the distribution.
135a80dc5fSbsh *
145a80dc5fSbsh * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
155a80dc5fSbsh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
165a80dc5fSbsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
175a80dc5fSbsh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
185a80dc5fSbsh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
195a80dc5fSbsh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
205a80dc5fSbsh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
215a80dc5fSbsh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
225a80dc5fSbsh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
235a80dc5fSbsh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
245a80dc5fSbsh * POSSIBILITY OF SUCH DAMAGE.
255a80dc5fSbsh *
265a80dc5fSbsh */
275a80dc5fSbsh
285a80dc5fSbsh #include "opt_imxuart.h"
295a80dc5fSbsh #include <sys/param.h>
305a80dc5fSbsh #include <sys/bus.h>
315a80dc5fSbsh #include <sys/device.h>
325a80dc5fSbsh #include <arm/imx/imx31reg.h>
335a80dc5fSbsh #include <arm/imx/imx31var.h>
345a80dc5fSbsh #include <arm/imx/imxuartreg.h>
355a80dc5fSbsh #include <arm/imx/imxuartvar.h>
365a80dc5fSbsh
37*4f4d98d9Shkenken static int imx31_uart_match(device_t, struct cfdata *, void *);
38*4f4d98d9Shkenken static void imx31_uart_attach(device_t, device_t, void *);
39*4f4d98d9Shkenken
40*4f4d98d9Shkenken CFATTACH_DECL_NEW(imx31_uart, sizeof(struct imxuart_softc),
41*4f4d98d9Shkenken imx31_uart_match, imx31_uart_attach, NULL, NULL);
425a80dc5fSbsh
435a80dc5fSbsh int
imx31_uart_match(device_t parent,struct cfdata * cf,void * aux)44*4f4d98d9Shkenken imx31_uart_match(device_t parent, struct cfdata *cf, void *aux)
455a80dc5fSbsh {
465a80dc5fSbsh struct aips_attach_args * const aipsa = aux;
475a80dc5fSbsh
485a80dc5fSbsh switch (aipsa->aipsa_addr) {
495a80dc5fSbsh case UART1_BASE:
505a80dc5fSbsh case UART2_BASE:
515a80dc5fSbsh case UART3_BASE:
525a80dc5fSbsh case UART4_BASE:
535a80dc5fSbsh case UART5_BASE:
545a80dc5fSbsh return 1;
555a80dc5fSbsh }
565a80dc5fSbsh
575a80dc5fSbsh return 0;
585a80dc5fSbsh }
595a80dc5fSbsh
605a80dc5fSbsh void
imx31_uart_attach(device_t parent,device_t self,void * aux)61*4f4d98d9Shkenken imx31_uart_attach(device_t parent, device_t self, void *aux)
625a80dc5fSbsh {
635a80dc5fSbsh struct aips_attach_args * aa = aux;
645a80dc5fSbsh
655a80dc5fSbsh imxuart_attach_common(parent, self,
665a80dc5fSbsh aa->aipsa_memt, aa->aipsa_addr, aa->aipsa_size, aa->aipsa_intr, 0);
675a80dc5fSbsh }
685a80dc5fSbsh
69