1 /* $Id: imx23_rtcreg.h,v 1.1 2012/11/20 19:06:13 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_RTCREG_H_ 33 #define _ARM_IMX_IMX23_RTCREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_RTC_BASE 0x8005C000 38 39 /* 40 * Real-Time Clock Control Register. 41 */ 42 #define HW_RTC_CTRL 0x000 43 #define HW_RTC_CTRL_SET 0x004 44 #define HW_RTC_CTRL_CLR 0x008 45 #define HW_RTC_CTRL_TOG 0x00C 46 47 #define HW_RTC_CTRL_SFTRST __BIT(31) 48 #define HW_RTC_CTRL_CLKGATE __BIT(30) 49 #define HW_RTC_CTRL_RSVD0 __BITS(29, 7) 50 #define HW_RTC_CTRL_SUPPRESS_COPY2ANALOG __BIT(6) 51 #define HW_RTC_CTRL_FORCE_UPDATE __BIT(5) 52 #define HW_RTC_CTRL_WATCHDOGEN __BIT(4) 53 #define HW_RTC_CTRL_ONEMSEC_IRQ __BIT(3) 54 #define HW_RTC_CTRL_ALARM_IRQ __BIT(2) 55 #define HW_RTC_CTRL_ONEMSEC_IRQ_EN __BIT(1) 56 #define HW_RTC_CTRL_ALARM_IRQ_EN __BIT(0) 57 58 /* 59 * Real-Time Clock Status Register. 60 */ 61 #define HW_RTC_STAT 0x010 62 #define HW_RTC_STAT_SET 0x014 63 #define HW_RTC_STAT_CLR 0x018 64 #define HW_RTC_STAT_TOG 0x01C 65 66 #define HW_RTC_STAT_RTC_PRESENT __BIT(31) 67 #define HW_RTC_STAT_ALARM_PRESENT __BIT(30) 68 #define HW_RTC_STAT_WATCHDOG_PRESENT __BIT(29) 69 #define HW_RTC_STAT_XTAL32000_PRESENT __BIT(28) 70 #define HW_RTC_STAT_XTAL32768_PRESENT __BIT(27) 71 #define HW_RTC_STAT_RSVD1 __BITS(26, 24) 72 #define HW_RTC_STAT_STALE_REGS __BIT(23, 16) 73 #define HW_RTC_STAT_NEW_REGS __BIT(15, 8) 74 #define HW_RTC_STAT_RSVD0 __BIT(7, 0) 75 76 /* 77 * Real-Time Clock Milliseconds Counter. 78 */ 79 #define HW_RTC_MILLISECONDS 0x020 80 #define HW_RTC_MILLISECONDS_SET 0x024 81 #define HW_RTC_MILLISECONDS_CLR 0x028 82 #define HW_RTC_MILLISECONDS_TOG 0x02C 83 84 #define HW_RTC_MILLISECONDS_COUNT __BITS(31, 0) 85 86 /* 87 * Real-Time Clock Seconds Counter. 88 */ 89 #define HW_RTC_SECONDS 0x030 90 #define HW_RTC_SECONDS_SET 0x034 91 #define HW_RTC_SECONDS_CLR 0x038 92 #define HW_RTC_SECONDS_TOG 0x03C 93 94 #define HW_RTC_SECONDS_COUNT __BITS(31, 0) 95 96 /* 97 * Real-Time Clock Alarm Register. 98 */ 99 #define HW_RTC_ALARM 0x040 100 #define HW_RTC_ALARM_SET 0x044 101 #define HW_RTC_ALARM_CLR 0x048 102 #define HW_RTC_ALARM_TOG 0x04C 103 104 #define HW_RTC_ALARM_VALUE __BITS(31, 0) 105 106 /* 107 * Watchdog Timer Register. 108 */ 109 #define HW_RTC_WATCHDOG 0x050 110 #define HW_RTC_WATCHDOG_SET 0x054 111 #define HW_RTC_WATCHDOG_CLR 0x058 112 #define HW_RTC_WATCHDOG_TOG 0x05C 113 114 #define HW_RTC_WATCHDOG_COUNT __BITS(31, 0) 115 116 /* 117 * Persistent State Register 0. 118 */ 119 #define HW_RTC_PERSISTENT0 0x060 120 #define HW_RTC_PERSISTENT0_SET 0x064 121 #define HW_RTC_PERSISTENT0_CLR 0x068 122 #define HW_RTC_PERSISTENT0_TOG 0x06C 123 124 #define HW_RTC_PERSISTENT0_SPARE_ANALOG __BITS(31, 18) 125 #define HW_RTC_PERSISTENT0_AUTO_RESTART __BIT(17) 126 #define HW_RTC_PERSISTENT0_DISABLE_PSWITCH __BIT(16) 127 #define HW_RTC_PERSISTENT0_LOWERBIAS __BITS(15, 14) 128 #define HW_RTC_PERSISTENT0_DISABLE_XTALOK __BIT(13) 129 #define HW_RTC_PERSISTENT0_MSEC_RES __BITS(12, 8) 130 #define HW_RTC_PERSISTENT0_ALARM_WAKE __BIT(7) 131 #define HW_RTC_PERSISTENT0_XTAL32_FREQ __BIT(6) 132 #define HW_RTC_PERSISTENT0_XTAL32KHZ_PWRUP __BIT(5) 133 #define HW_RTC_PERSISTENT0_XTAL24MHZ_PWRUP __BIT(4) 134 #define HW_RTC_PERSISTENT0_LCK_SECS __BIT(3) 135 #define HW_RTC_PERSISTENT0_ALARM_EN __BIT(2) 136 #define HW_RTC_PERSISTENT0_ALARM_WAKE_EN __BIT(1) 137 #define HW_RTC_PERSISTENT0_CLOCKSOURCE __BIT(0) 138 139 /* 140 * Persistent State Register 1. 141 */ 142 #define HW_RTC_PERSISTENT1 0x070 143 #define HW_RTC_PERSISTENT1_SET 0x074 144 #define HW_RTC_PERSISTENT1_CLR 0x078 145 #define HW_RTC_PERSISTENT1_TOG 0x07C 146 147 #define HW_RTC_PERSISTENT1_GENERAL __BITS(31, 0) 148 149 /* 150 * Persistent State Register 2. 151 */ 152 #define HW_RTC_PERSISTENT2 0x080 153 #define HW_RTC_PERSISTENT2_SET 0x084 154 #define HW_RTC_PERSISTENT2_CLR 0x088 155 #define HW_RTC_PERSISTENT2_TOG 0x08C 156 157 #define HW_RTC_PERSISTENT2_GENERAL __BITS(31, 0) 158 159 /* 160 * Persistent State Register 3. 161 */ 162 #define HW_RTC_PERSISTENT3 0x090 163 #define HW_RTC_PERSISTENT3_SET 0x094 164 #define HW_RTC_PERSISTENT3_CLR 0x098 165 #define HW_RTC_PERSISTENT3_TOG 0x09C 166 167 #define HW_RTC_PERSISTENT3_GENERAL __BITS(31, 0) 168 169 /* 170 * Persistent State Register 4. 171 */ 172 #define HW_RTC_PERSISTENT4 0x0A0 173 #define HW_RTC_PERSISTENT4_SET 0x0A4 174 #define HW_RTC_PERSISTENT4_CLR 0x0A8 175 #define HW_RTC_PERSISTENT4_TOG 0x0AC 176 177 #define HW_RTC_PERSISTENT4_GENERAL __BITS(31, 0) 178 179 /* 180 * Persistent State Register 5. 181 */ 182 #define HW_RTC_PERSISTENT5 0x0B0 183 #define HW_RTC_PERSISTENT5_SET 0x0B4 184 #define HW_RTC_PERSISTENT5_CLR 0x0B8 185 #define HW_RTC_PERSISTENT5_TOG 0x0BC 186 187 #define HW_RTC_PERSISTENT5_GENERAL __BITS(31, 0) 188 189 /* 190 * Real-Time Clock Debug Register. 191 */ 192 #define HW_RTC_DEBUG 0x0C0 193 #define HW_RTC_DEBUG_SET 0x0C4 194 #define HW_RTC_DEBUG_CLR 0x0C8 195 #define HW_RTC_DEBUG_TOG 0x0CC 196 197 #define HW_RTC_DEBUG_RSVD0 __BITS(31, 2) 198 #define HW_RTC_DEBUG_WATCHDOG_RESET_MASK __BIT(1) 199 #define HW_RTC_DEBUG_WATCHDOG_RESET __BIT(0) 200 201 /* 202 * Real-Time Clock Version Register. 203 */ 204 #define HW_RTC_VERSION 0x0D0 205 206 #define HW_RTC_VERSION_MAJOR __BITS(31, 24) 207 #define HW_RTC_VERSION_MINOR __BITS(23, 16) 208 #define HW_RTC_VERSION_STEP __BITS(15, 9) 209 210 #endif /* !_ARM_IMX_IMX23_RTCREG_H_ */ 211