1 /* $Id: imx23_icoll.c,v 1.2 2012/12/16 19:40:00 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/errno.h> 37 #include <sys/systm.h> 38 39 #define _INTR_PRIVATE 40 #include <arm/pic/picvar.h> 41 42 #include <arm/imx/imx23_icollreg.h> 43 #include <arm/imx/imx23var.h> 44 45 #define ICOLL_SOFT_RST_LOOP 455 /* At least 1 us ... */ 46 #define ICOLL_READ(sc, reg) \ 47 bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 48 #define ICOLL_WRITE(sc, reg, val) \ 49 bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 50 51 #define ICOLL_IRQ_REG_SIZE 0x10 52 #define ICOLL_CLR_IRQ(sc, irq) \ 53 ICOLL_WRITE(sc, HW_ICOLL_INTERRUPT0_CLR + \ 54 (irq) * ICOLL_IRQ_REG_SIZE, \ 55 HW_ICOLL_INTERRUPT_ENABLE) 56 #define ICOLL_SET_IRQ(sc, irq) \ 57 ICOLL_WRITE(sc, HW_ICOLL_INTERRUPT0_SET + \ 58 (irq) * ICOLL_IRQ_REG_SIZE, \ 59 HW_ICOLL_INTERRUPT_ENABLE) 60 #define ICOLL_GET_PRIO(sc, irq) \ 61 __SHIFTOUT(ICOLL_READ(sc, HW_ICOLL_INTERRUPT0 + \ 62 (irq) * ICOLL_IRQ_REG_SIZE), \ 63 HW_ICOLL_INTERRUPT_PRIORITY) 64 65 #define PICTOSOFTC(pic) \ 66 ((struct icoll_softc *)((char *)(pic) - \ 67 offsetof(struct icoll_softc, sc_pic))) 68 69 /* 70 * pic callbacks. 71 */ 72 static void icoll_unblock_irqs(struct pic_softc *, size_t, uint32_t); 73 static void icoll_block_irqs(struct pic_softc *, size_t, uint32_t); 74 static int icoll_find_pending_irqs(struct pic_softc *); 75 static void icoll_establish_irq(struct pic_softc *, struct intrsource *); 76 static void icoll_source_name(struct pic_softc *, int, char *, size_t); 77 static void icoll_set_priority(struct pic_softc *, int); 78 79 /* 80 * autoconf(9) callbacks. 81 */ 82 static int icoll_match(device_t, cfdata_t, void *); 83 static void icoll_attach(device_t, device_t, void *); 84 static int icoll_activate(device_t, enum devact); 85 86 /* 87 * ARM interrupt handler. 88 */ 89 void imx23_intr_dispatch(struct clockframe *); 90 91 const static struct pic_ops icoll_pic_ops = { 92 .pic_unblock_irqs = icoll_unblock_irqs, 93 .pic_block_irqs = icoll_block_irqs, 94 .pic_find_pending_irqs = icoll_find_pending_irqs, 95 .pic_establish_irq = icoll_establish_irq, 96 .pic_source_name = icoll_source_name, 97 .pic_set_priority = icoll_set_priority 98 }; 99 100 struct icoll_softc { 101 device_t sc_dev; 102 struct pic_softc sc_pic; 103 bus_space_tag_t sc_iot; 104 bus_space_handle_t sc_hdl; 105 }; 106 107 /* For IRQ handler. */ 108 static struct icoll_softc *icoll_sc; 109 110 /* 111 * Private to driver. 112 */ 113 static void icoll_reset(struct icoll_softc *); 114 115 CFATTACH_DECL3_NEW(icoll, 116 sizeof(struct icoll_softc), 117 icoll_match, 118 icoll_attach, 119 NULL, 120 icoll_activate, 121 NULL, 122 NULL, 123 0); 124 125 /* 126 * ARM interrupt handler. 127 */ 128 void 129 imx23_intr_dispatch(struct clockframe *frame) 130 { 131 struct cpu_info * const ci = curcpu(); 132 struct pic_softc *pic_sc; 133 int saved_spl; 134 uint8_t irq; 135 uint8_t prio; 136 137 pic_sc = &icoll_sc->sc_pic; 138 139 ci->ci_data.cpu_nintr++; 140 141 /* Save current spl. */ 142 saved_spl = curcpl(); 143 144 /* IRQ to be handled. */ 145 irq = __SHIFTOUT(ICOLL_READ(icoll_sc, HW_ICOLL_STAT), 146 HW_ICOLL_STAT_VECTOR_NUMBER); 147 148 /* Save IRQ's priority. Acknowledge it later. */ 149 prio = ICOLL_GET_PRIO(icoll_sc, irq); 150 151 /* 152 * Notify ICOLL to deassert IRQ before re-enabling the IRQ's. 153 * This is done by writing anything to HW_ICOLL_VECTOR. 154 */ 155 ICOLL_WRITE(icoll_sc, HW_ICOLL_VECTOR, 156 __SHIFTIN(0x3fffffff, HW_ICOLL_VECTOR_IRQVECTOR)); 157 158 /* Bogus IRQ. */ 159 if (irq == 0x7f) { 160 cpsie(I32_bit); 161 ICOLL_WRITE(icoll_sc, HW_ICOLL_LEVELACK, (1<<prio)); 162 cpsid(I32_bit); 163 return; 164 } 165 166 /* Raise the spl to the level of the IRQ. */ 167 if (pic_sc->pic_sources[irq]->is_ipl > ci->ci_cpl) 168 saved_spl = _splraise(pic_sc->pic_sources[irq]->is_ipl); 169 170 /* Call the handler registered for the IRQ. */ 171 cpsie(I32_bit); 172 pic_dispatch(pic_sc->pic_sources[irq], frame); 173 174 /* 175 * Acknowledge the IRQ by writing its priority to HW_ICOLL_LEVELACK. 176 * Interrupts should be enabled. 177 */ 178 ICOLL_WRITE(icoll_sc, HW_ICOLL_LEVELACK, (1<<prio)); 179 cpsid(I32_bit); 180 181 /* Restore the saved spl. */ 182 splx(saved_spl); 183 184 return; 185 } 186 187 /* 188 * pic callbacks. 189 */ 190 static void 191 icoll_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 192 { 193 struct icoll_softc *sc = PICTOSOFTC(pic); 194 uint8_t b; 195 196 for (;;) { 197 b = ffs(irq_mask); 198 if (b == 0) break; 199 b--; /* Zero based index. */ 200 ICOLL_SET_IRQ(sc, irq_base + b); 201 irq_mask &= ~(1<<b); 202 } 203 204 return; 205 } 206 207 static void 208 icoll_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 209 { 210 struct icoll_softc *sc = PICTOSOFTC(pic); 211 uint8_t b; 212 213 for (;;) { 214 b = ffs(irq_mask); 215 if (b == 0) break; 216 b--; /* Zero based index. */ 217 ICOLL_CLR_IRQ(sc, irq_base + b); 218 irq_mask &= ~(1<<b); 219 } 220 221 return; 222 } 223 224 static int 225 icoll_find_pending_irqs(struct pic_softc *pic) 226 { 227 return 0; /* ICOLL HW doesn't provide list of pending interrupts. */ 228 } 229 230 static void 231 icoll_establish_irq(struct pic_softc *pic, struct intrsource *is) 232 { 233 return; /* Nothing to establish. */ 234 } 235 236 static void 237 icoll_source_name(struct pic_softc *pic, int irq, char *is_source, size_t size) 238 { 239 snprintf(is_source, size, "irq %d", irq); 240 } 241 242 /* 243 * Set new interrupt priority level by enabling or disabling IRQ's. 244 */ 245 static void 246 icoll_set_priority(struct pic_softc *pic, int newipl) 247 { 248 struct icoll_softc *sc = PICTOSOFTC(pic); 249 struct intrsource *is; 250 int i; 251 252 for (i = 0; i < pic->pic_maxsources; i++) { 253 is = pic->pic_sources[i]; 254 if (is == NULL) 255 continue; 256 if (is->is_ipl > newipl) 257 ICOLL_SET_IRQ(sc, pic->pic_irqbase + is->is_irq); 258 else 259 ICOLL_CLR_IRQ(sc, pic->pic_irqbase + is->is_irq); 260 } 261 } 262 263 /* 264 * autoconf(9) callbacks. 265 */ 266 static int 267 icoll_match(device_t parent, cfdata_t match, void *aux) 268 { 269 struct apb_attach_args *aa = aux; 270 271 if ((aa->aa_addr == HW_ICOLL_BASE) && (aa->aa_size == HW_ICOLL_SIZE)) 272 return 1; 273 274 return 0; 275 } 276 277 static void 278 icoll_attach(device_t parent, device_t self, void *aux) 279 { 280 static int icoll_attached = 0; 281 struct icoll_softc *sc = device_private(self); 282 struct apb_attach_args *aa = aux; 283 284 if (icoll_attached) 285 return; 286 287 icoll_sc = sc; 288 289 sc->sc_dev = self; 290 sc->sc_iot = aa->aa_iot; 291 292 sc->sc_pic.pic_maxsources = IRQ_LAST + 1; 293 sc->sc_pic.pic_ops = &icoll_pic_ops; 294 strlcpy(sc->sc_pic.pic_name, device_xname(self), 295 sizeof(sc->sc_pic.pic_name)); 296 297 if (bus_space_map(sc->sc_iot, 298 aa->aa_addr, aa->aa_size, 0, &(sc->sc_hdl))) { 299 aprint_error_dev(sc->sc_dev, "unable to map bus space\n"); 300 return; 301 } 302 303 icoll_reset(sc); 304 pic_add(&sc->sc_pic, 0); 305 aprint_normal("\n"); 306 icoll_attached = 1; 307 308 return; 309 } 310 311 static int 312 icoll_activate(device_t self, enum devact act) 313 { 314 return EOPNOTSUPP; 315 } 316 317 /* 318 * Reset the ICOLL block. 319 * 320 * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 321 */ 322 static void 323 icoll_reset(struct icoll_softc *sc) 324 { 325 unsigned int loop; 326 327 /* 328 * Prepare for soft-reset by making sure that SFTRST is not currently 329 * asserted. Also clear CLKGATE so we can wait for its assertion below. 330 */ 331 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_SFTRST); 332 333 /* Wait at least a microsecond for SFTRST to deassert. */ 334 loop = 0; 335 while ((ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_SFTRST) || 336 (loop < ICOLL_SOFT_RST_LOOP)) { 337 loop++; 338 } 339 340 /* Clear CLKGATE so we can wait for its assertion below. */ 341 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_CLKGATE); 342 343 /* Soft-reset the block. */ 344 ICOLL_WRITE(sc, HW_ICOLL_CTRL_SET, HW_ICOLL_CTRL_SFTRST); 345 346 /* Wait until clock is in the gated state. */ 347 while (!(ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_CLKGATE)); 348 349 /* Bring block out of reset. */ 350 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_SFTRST); 351 352 loop = 0; 353 while ((ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_SFTRST) || 354 (loop < ICOLL_SOFT_RST_LOOP)) { 355 loop++; 356 } 357 358 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_CLKGATE); 359 360 /* Wait until clock is in the NON-gated state. */ 361 while (ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_CLKGATE); 362 363 return; 364 } 365