1 /* $Id: imx23_clkctrlreg.h,v 1.1 2012/11/20 19:06:13 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_CLKCTRLREG_H_ 33 #define _ARM_IMX_IMX23_CLKCTRLREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_CLKCTRL_BASE 0x80040000 38 39 /* 40 * PLL Control Register 0. 41 */ 42 #define HW_CLKCTRL_PLLCTRL0 0x000 43 #define HW_CLKCTRL_PLLCTRL0_SET 0x004 44 #define HW_CLKCTRL_PLLCTRL0_CLR 0x008 45 #define HW_CLKCTRL_PLLCTRL0_TOG 0x00C 46 47 #define HW_CLKCTRL_PLLCTRL0_RSRVD6 __BITS(31, 30) 48 #define HW_CLKCTRL_PLLCTRL0_LFR_SEL __BITS(29, 28) 49 #define HW_CLKCTRL_PLLCTRL0_RSRVD5 __BITS(27, 26) 50 #define HW_CLKCTRL_PLLCTRL0_CP_SEL __BITS(25, 24) 51 #define HW_CLKCTRL_PLLCTRL0_RSRVD4 __BITS(23, 22) 52 #define HW_CLKCTRL_PLLCTRL0_DIV_SEL __BITS(21, 20) 53 #define HW_CLKCTRL_PLLCTRL0_RSRVD3 __BIT(19) 54 #define HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS __BIT(18) 55 #define HW_CLKCTRL_PLLCTRL0_RSRVD2 __BIT(17) 56 #define HW_CLKCTRL_PLLCTRL0_POWER __BIT(16) 57 #define HW_CLKCTRL_PLLCTRL0_RSRVD1 __BITS(15, 0) 58 59 /* 60 * PLL Control Register 1. 61 */ 62 #define HW_CLKCTRL_PLLCTRL1 0x010 63 64 #define HW_CLKCTRL_PLLCTRL1_LOCK __BIT(31) 65 #define HW_CLKCTRL_PLLCTRL1_FORCE_LOCK __BIT(30) 66 #define HW_CLKCTRL_PLLCTRL1_RSRVD1 __BITS(29, 16) 67 #define HW_CLKCTRL_PLLCTRL1_LOCK_COUNT __BITS(15, 0) 68 69 /* 70 * CPU Clock Control Register. 71 */ 72 #define HW_CLKCTRL_CPU 0x020 73 #define HW_CLKCTRL_CPU_SET 0x024 74 #define HW_CLKCTRL_CPU_CLR 0x028 75 #define HW_CLKCTRL_CPU_TOG 0x02c 76 77 #define HW_CLKCTRL_CPU_RSVD6 __BITS(31, 30) 78 #define HW_CLKCTRL_CPU_BUSY_REF_XTAL __BIT(29) 79 #define HW_CLKCTRL_CPU_BUSY_REF_CPU __BIT(28) 80 #define HW_CLKCTRL_CPU_RSVD5 __BIT(27) 81 #define HW_CLKCTRL_CPU_DIV_XTAL_FRAC_EN __BIT(26) 82 #define HW_CLKCTRL_CPU_DIV_XTAL __BITS(25, 16) 83 #define HW_CLKCTRL_CPU_RSVD4 __BITS(15, 13) 84 #define HW_CLKCTRL_CPU_INTERRUPT_WAIT __BIT(12) 85 #define HW_CLKCTRL_CPU_RSVD3 __BIT(11) 86 #define HW_CLKCTRL_CPU_RSVD2 __BIT(10) 87 #define HW_CLKCTRL_CPU_RSVD1 __BITS(9, 6) 88 #define HW_CLKCTRL_CPU_DIV_CPU __BITS(5, 0) 89 90 /* 91 * AHB, APBH Bus Clock Control Register. 92 */ 93 #define HW_CLKCTRL_HBUS 0x030 94 #define HW_CLKCTRL_HBUS_SET 0x034 95 #define HW_CLKCTRL_HBUS_CLR 0x038 96 #define HW_CLKCTRL_HBUS_TOG 0x03c 97 98 #define HW_CLKCTRL_HBUS_RSRVD4 __BITS(31, 30) 99 #define HW_CLKCTRL_HBUS_BUSY __BIT(29) 100 #define HW_CLKCTRL_HBUS_DCP_AS_ENABLE __BIT(28) 101 #define HW_CLKCTRL_HBUS_PXP_AS_ENABLE __BIT(27) 102 #define HW_CLKCTRL_HBUS_APBHDMA_AS_ENABLE __BIT(26) 103 #define HW_CLKCTRL_HBUS_APBXDMA_AS_ENABLE __BIT(25) 104 #define HW_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE __BIT(24) 105 #define HW_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE __BIT(23) 106 #define HW_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE __BIT(22) 107 #define HW_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE __BIT(21) 108 #define HW_CLKCTRL_HBUS_AUTO_SLOW_MODE __BIT(20) 109 #define HW_CLKCTRL_HBUS_RSRVD2 __BIT(19) 110 #define HW_CLKCTRL_HBUS_SLOW_DIV __BITS(18, 16) 111 #define HW_CLKCTRL_HBUS_RSRVD1 __BITS(15, 6) 112 #define HW_CLKCTRL_HBUS_DIV_FRAC_EN __BIT(5) 113 #define HW_CLKCTRL_HBUS_DIV __BITS(4, 0) 114 115 /* 116 * APBX Clock Control Register. 117 */ 118 #define HW_CLKCTRL_XBUS 0x040 119 120 #define HW_CLKCTRL_XBUS_BUSY __BIT(31) 121 #define HW_CLKCTRL_XBUS_RSVD2 __BITS(30, 11) 122 #define HW_CLKCTRL_XBUS_RSVD1 __BIT(10) 123 #define HW_CLKCTRL_XBUS_DIV __BITS(9, 0) 124 125 /* 126 * XTAL Clock Control Register. 127 */ 128 #define HW_CLKCTRL_XTAL 0x050 129 #define HW_CLKCTRL_XTAL_SET 0x054 130 #define HW_CLKCTRL_XTAL_CLR 0x058 131 #define HW_CLKCTRL_XTAL_TOG 0x05C 132 133 #define HW_CLKCTRL_XTAL_UART_CLK_GATE __BIT(31) 134 #define HW_CLKCTRL_XTAL_FILT_CLK24M_GATE __BIT(30) 135 #define HW_CLKCTRL_XTAL_PWM_CLK24M_GATE __BIT(29) 136 #define HW_CLKCTRL_XTAL_DRI_CLK24M_GATE __BIT(28) 137 #define HW_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE __BIT(27) 138 #define HW_CLKCTRL_XTAL_TIMROT_CLK32K_GATE __BIT(26) 139 #define HW_CLKCTRL_XTAL_RSRVD1 __BITS(25, 2) 140 #define HW_CLKCTRL_XTAL_DIV_UART __BITS(1, 0) 141 142 /* 143 * PIX (LCDIF) Clock Control Register. 144 */ 145 #define HW_CLKCTRL_PIX 0x060 146 147 #define HW_CLKCTRL_PIX_CLKGATE __BIT(31) 148 #define HW_CLKCTRL_PIX_RSRVD2 __BIT(30) 149 #define HW_CLKCTRL_PIX_BUSY __BIT(29) 150 #define HW_CLKCTRL_PIX_RSRVD1 __BITS(28, 13) 151 #define HW_CLKCTRL_PIX_DIV_FRAC_EN __BIT(12) 152 #define HW_CLKCTRL_PIX_DIV __BITS(11, 0) 153 154 /* 155 * Synchronous Serial Port Clock Control Register. 156 */ 157 #define HW_CLKCTRL_SSP 0x070 158 159 #define HW_CLKCTRL_SSP_CLKGATE __BIT(31) 160 #define HW_CLKCTRL_SSP_RSVD3 __BIT(30) 161 #define HW_CLKCTRL_SSP_BUSY __BIT(29) 162 #define HW_CLKCTRL_SSP_RSVD2 __BITS(28, 10) 163 #define HW_CLKCTRL_SSP_RSVD1 __BIT(9) 164 #define HW_CLKCTRL_SSP_DIV __BITS(8, 0) 165 166 /* 167 * General-Purpose Media Interface Clock Control Register. 168 */ 169 #define HW_CLKCTRL_GPMI 0x080 170 171 #define HW_CLKCTRL_GPMI_CLKGATE __BIT(31) 172 #define HW_CLKCTRL_GPMI_RSVD3 __BIT(30) 173 #define HW_CLKCTRL_GPMI_BUSY __BIT(29) 174 #define HW_CLKCTRL_GPMI_RSVD2 __BITS(28, 11) 175 #define HW_CLKCTRL_GPMI_RSVD1 __BIT(10) 176 #define HW_CLKCTRL_GPMI_DIV __BIT(9, 0) 177 178 /* 179 * SPDIF Clock Control Register. 180 */ 181 #define HW_CLKCTRL_SPDIF 0x090 182 183 #define HW_CLKCTRL_SPDIF_CLKGATE __BIT(31) 184 #define HW_CLKCTRL_SPDIF_RSRVD __BITS(30, 0) 185 186 /* 187 * EMI Clock Control Register. 188 */ 189 #define HW_CLKCTRL_EMI 0x0a0 190 191 #define HW_CLKCTRL_EMI_CLKGATE __BIT(31) 192 #define HW_CLKCTRL_EMI_SYNC_MODE_EN __BIT(30) 193 #define HW_CLKCTRL_EMI_BUSY_REF_XTAL __BIT(29) 194 #define HW_CLKCTRL_EMI_BUSY_REF_EMI __BIT(28) 195 #define HW_CLKCTRL_EMI_BUSY_REF_CPU __BIT(27) 196 #define HW_CLKCTRL_EMI_BUSY_SYNC_MODE __BIT(26) 197 #define HW_CLKCTRL_EMI_RSVD5 __BITS(25, 18) 198 #define HW_CLKCTRL_EMI_RSVD4 __BIT(17) 199 #define HW_CLKCTRL_EMI_RSVD3 __BIT(16) 200 #define HW_CLKCTRL_EMI_RSVD2 __BITS(15, 12) 201 #define HW_CLKCTRL_EMI_DIV_XTAL __BITS(11, 8) 202 #define HW_CLKCTRL_EMI_RSVD1 __BITS(7, 6) 203 #define HW_CLKCTRL_EMI_DIV_EMI __BITS(5, 0) 204 205 /* 206 * SAIF Clock Control Register. 207 */ 208 #define HW_CLKCTRL_SAIF 0x0c0 209 210 #define HW_CLKCTRL_SAIF_CLKGATE __BIT(31) 211 #define HW_CLKCTRL_SAIF_RSRVD2 __BIT(30) 212 #define HW_CLKCTRL_SAIF_BUSY __BIT(29) 213 #define HW_CLKCTRL_SAIF_RSRVD1 __BITS(28, 17) 214 #define HW_CLKCTRL_SAIF_DIV_FRAC_EN __BIT(16) 215 #define HW_CLKCTRL_SAIF_DIV __BITS(15, 0) 216 217 /* 218 * TV Encoder Clock Control Register. 219 */ 220 #define HW_CLKCTRL_TV 0x0d0 221 222 #define HW_CLKCTRL_TV_CLK_TV108M_GATE __BIT(31) 223 #define HW_CLKCTRL_TV_CLK_TV_GATE __BIT(30) 224 #define HW_CLKCTRL_TV_RSRVD __BITS(29, 0) 225 226 /* 227 * ETM Clock Control Register. 228 */ 229 #define HW_CLKCTRL_ETM 0x0e0 230 231 #define HW_CLKCTRL_ETM_CLKGATE __BIT(31) 232 #define HW_CLKCTRL_ETM_RSRVD2 __BIT(30) 233 #define HW_CLKCTRL_ETM_BUSY __BIT(29) 234 #define HW_CLKCTRL_ETM_RSRVD1 __BITS(28, 7) 235 #define HW_CLKCTRL_ETM_DIV_FRAC_EN __BIT(6) 236 #define HW_CLKCTRL_ETM_DIV __BITs(5, 0) 237 238 /* 239 * Fractional Clock Control Register. 240 */ 241 #define HW_CLKCTRL_FRAC 0x0f0 242 #define HW_CLKCTRL_FRAC_SET 0x0f4 243 #define HW_CLKCTRL_FRAC_CLR 0x0f8 244 #define HW_CLKCTRL_FRAC_TOG 0x0fC 245 246 #define HW_CLKCTRL_FRAC_CLKGATEIO __BIT(31) 247 #define HW_CLKCTRL_FRAC_IO_STABLE __BIT(30) 248 #define HW_CLKCTRL_FRAC_IOFRAC __BITS(29, 24) 249 #define HW_CLKCTRL_FRAC_CLKGATEPIX __BIT(23) 250 #define HW_CLKCTRL_FRAC_PIX_STABLE __BIT(22) 251 #define HW_CLKCTRL_FRAC_PIXFRAC __BITS(21, 16) 252 #define HW_CLKCTRL_FRAC_CLKGATEEMI __BIT(15) 253 #define HW_CLKCTRL_FRAC_EMI_STABLE __BIT(14) 254 #define HW_CLKCTRL_FRAC_EMIFRAC __BITS(13, 8) 255 #define HW_CLKCTRL_FRAC_CLKGATECPU __BIT(7) 256 #define HW_CLKCTRL_FRAC_CPU_STABLE __BIT(6) 257 #define HW_CLKCTRL_FRAC_CPUFRAC __BITS(5, 0) 258 259 /* 260 * Fractional Clock Control Register 1. 261 */ 262 #define HW_CLKCTRL_FRAC1 0x100 263 #define HW_CLKCTRL_FRAC1_SET 0x104 264 #define HW_CLKCTRL_FRAC1_CLR 0x108 265 #define HW_CLKCTRL_FRAC1_TOG 0x10C 266 267 #define HW_CLKCTRL_FRAC1_CLKGATEVID __BIT(31) 268 #define HW_CLKCTRL_FRAC1_VID_STABLE __BIT(30) 269 #define HW_CLKCTRL_FRAC1_RSRVD1 __BITS(29, 0) 270 271 /* 272 * Clock Frequency Sequence Control Register. 273 */ 274 #define HW_CLKCTRL_CLKSEQ 0x110 275 #define HW_CLKCTRL_CLKSEQ_SET 0x114 276 #define HW_CLKCTRL_CLKSEQ_CLR 0x118 277 #define HW_CLKCTRL_CLKSEQ_TOG 0x11c 278 279 #define HW_CLKCTRL_CLKSEQ_RSRVD1 __BITS(31, 9) 280 #define HW_CLKCTRL_CLKSEQ_BYPASS_ETM __BIT(8) 281 #define HW_CLKCTRL_CLKSEQ_BYPASS_CPU __BIT(7) 282 #define HW_CLKCTRL_CLKSEQ_BYPASS_EMI __BIT(6) 283 #define HW_CLKCTRL_CLKSEQ_BYPASS_SSP __BIT(5) 284 #define HW_CLKCTRL_CLKSEQ_BYPASS_GPMI __BIT(4) 285 #define HW_CLKCTRL_CLKSEQ_BYPASS_IR __BIT(3) 286 #define HW_CLKCTRL_CLKSEQ_RSRVD0 __BIT(2) 287 #define HW_CLKCTRL_CLKSEQ_BYPASS_PIX __BIT(1) 288 #define HW_CLKCTRL_CLKSEQ_BYPASS_SAIF __BIT(0) 289 290 /* 291 * System Software Reset Register. 292 */ 293 #define HW_CLKCTRL_RESET 0x120 294 295 #define HW_CLKCTRL_RESET_RSRVD __BITS(31, 2) 296 #define HW_CLKCTRL_RESET_CHIP __BIT(1) 297 #define HW_CLKCTRL_RESET_DIG __BIT(0) 298 299 /* 300 * CLKCTRL Status. 301 */ 302 #define HW_CLKCTRL_STATUS 0x130 303 304 #define HW_CLKCTRL_STATUS_CPU_LIMIT __BITS(31, 30) 305 #define HW_CLKCTRL_STATUS_RSRVD __BITS(29, 0) 306 307 /* 308 * CLKCTRL Version Register. 309 */ 310 #define HW_CLKCTRL_VERSION 0x140 311 312 #define HW_CLKCTRL_VERSION_MAJOR __BITS(31, 24) 313 #define HW_CLKCTRL_VERSION_MINOR __BITS(23, 16) 314 #define HW_CLKCTRL_VERSION_STEP __BITS(15, 0) 315 316 #endif /* !_ARM_IMX_IMX23_CLKCTRLREG_H_ */ 317