1 /* $NetBSD: if_enet.c,v 1.10 2016/12/15 09:28:02 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * i.MX6,7 10/100/1000-Mbps ethernet MAC (ENET) 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.10 2016/12/15 09:28:02 ozaki-r Exp $"); 35 36 #include "vlan.h" 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/mbuf.h> 41 #include <sys/device.h> 42 #include <sys/sockio.h> 43 #include <sys/kernel.h> 44 #include <sys/rndsource.h> 45 46 #include <lib/libkern/libkern.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_ether.h> 52 #include <net/bpf.h> 53 #include <net/if_vlanvar.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/ip.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <arm/imx/if_enetreg.h> 63 #include <arm/imx/if_enetvar.h> 64 65 #undef DEBUG_ENET 66 #undef ENET_EVENT_COUNTER 67 68 #define ENET_TICK hz 69 70 #ifdef DEBUG_ENET 71 int enet_debug = 0; 72 # define DEVICE_DPRINTF(args...) \ 73 do { if (enet_debug) device_printf(sc->sc_dev, args); } while (0) 74 #else 75 # define DEVICE_DPRINTF(args...) 76 #endif 77 78 79 #define RXDESC_MAXBUFSIZE 0x07f0 80 /* ENET does not work greather than 0x0800... */ 81 82 #undef ENET_SUPPORT_JUMBO /* JUMBO FRAME SUPPORT is unstable */ 83 #ifdef ENET_SUPPORT_JUMBO 84 # define ENET_MAX_PKT_LEN 4034 /* MAX FIFO LEN */ 85 #else 86 # define ENET_MAX_PKT_LEN 1522 87 #endif 88 #define ENET_DEFAULT_PKT_LEN 1522 /* including VLAN tag */ 89 #define MTU2FRAMESIZE(n) \ 90 ((n) + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN) 91 92 93 #define ENET_MAX_PKT_NSEGS 64 94 95 #define ENET_TX_NEXTIDX(idx) (((idx) >= (ENET_TX_RING_CNT - 1)) ? 0 : ((idx) + 1)) 96 #define ENET_RX_NEXTIDX(idx) (((idx) >= (ENET_RX_RING_CNT - 1)) ? 0 : ((idx) + 1)) 97 98 #define TXDESC_WRITEOUT(idx) \ 99 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \ 100 sizeof(struct enet_txdesc) * (idx), \ 101 sizeof(struct enet_txdesc), \ 102 BUS_DMASYNC_PREWRITE) 103 104 #define TXDESC_READIN(idx) \ 105 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \ 106 sizeof(struct enet_txdesc) * (idx), \ 107 sizeof(struct enet_txdesc), \ 108 BUS_DMASYNC_PREREAD) 109 110 #define RXDESC_WRITEOUT(idx) \ 111 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, \ 112 sizeof(struct enet_rxdesc) * (idx), \ 113 sizeof(struct enet_rxdesc), \ 114 BUS_DMASYNC_PREWRITE) 115 116 #define RXDESC_READIN(idx) \ 117 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, \ 118 sizeof(struct enet_rxdesc) * (idx), \ 119 sizeof(struct enet_rxdesc), \ 120 BUS_DMASYNC_PREREAD) 121 122 #define ENET_REG_READ(sc, reg) \ 123 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg) 124 125 #define ENET_REG_WRITE(sc, reg, value) \ 126 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, value) 127 128 #ifdef ENET_EVENT_COUNTER 129 static void enet_attach_evcnt(struct enet_softc *); 130 static void enet_update_evcnt(struct enet_softc *); 131 #endif 132 133 static int enet_intr(void *); 134 static void enet_tick(void *); 135 static int enet_tx_intr(void *); 136 static int enet_rx_intr(void *); 137 static void enet_rx_csum(struct enet_softc *, struct ifnet *, struct mbuf *, 138 int); 139 140 static void enet_start(struct ifnet *); 141 static int enet_ifflags_cb(struct ethercom *); 142 static int enet_ioctl(struct ifnet *, u_long, void *); 143 static int enet_init(struct ifnet *); 144 static void enet_stop(struct ifnet *, int); 145 static void enet_watchdog(struct ifnet *); 146 static void enet_mediastatus(struct ifnet *, struct ifmediareq *); 147 148 static int enet_miibus_readreg(device_t, int, int); 149 static void enet_miibus_writereg(device_t, int, int, int); 150 static void enet_miibus_statchg(struct ifnet *); 151 152 static void enet_gethwaddr(struct enet_softc *, uint8_t *); 153 static void enet_sethwaddr(struct enet_softc *, uint8_t *); 154 static void enet_setmulti(struct enet_softc *); 155 static int enet_encap_mbufalign(struct mbuf **); 156 static int enet_encap_txring(struct enet_softc *, struct mbuf **); 157 static int enet_init_regs(struct enet_softc *, int); 158 static int enet_alloc_ring(struct enet_softc *); 159 static void enet_init_txring(struct enet_softc *); 160 static int enet_init_rxring(struct enet_softc *); 161 static void enet_reset_rxdesc(struct enet_softc *, int); 162 static int enet_alloc_rxbuf(struct enet_softc *, int); 163 static void enet_drain_txbuf(struct enet_softc *); 164 static void enet_drain_rxbuf(struct enet_softc *); 165 static int enet_alloc_dma(struct enet_softc *, size_t, void **, 166 bus_dmamap_t *); 167 168 CFATTACH_DECL_NEW(enet, sizeof(struct enet_softc), 169 enet_match, enet_attach, NULL, NULL); 170 171 void 172 enet_attach_common(device_t self, bus_space_tag_t iot, 173 bus_dma_tag_t dmat, bus_addr_t addr, bus_size_t size, int irq) 174 { 175 struct enet_softc *sc; 176 struct ifnet *ifp; 177 178 sc = device_private(self); 179 sc->sc_dev = self; 180 sc->sc_iot = iot; 181 sc->sc_addr = addr; 182 sc->sc_dmat = dmat; 183 184 aprint_naive("\n"); 185 aprint_normal(": Gigabit Ethernet Controller\n"); 186 if (bus_space_map(sc->sc_iot, sc->sc_addr, size, 0, 187 &sc->sc_ioh)) { 188 aprint_error_dev(self, "cannot map registers\n"); 189 return; 190 } 191 192 /* allocate dma buffer */ 193 if (enet_alloc_ring(sc)) 194 return; 195 196 #define IS_ENADDR_ZERO(enaddr) \ 197 ((enaddr[0] | enaddr[1] | enaddr[2] | \ 198 enaddr[3] | enaddr[4] | enaddr[5]) == 0) 199 200 if (IS_ENADDR_ZERO(sc->sc_enaddr)) { 201 /* by any chance, mac-address is already set by bootloader? */ 202 enet_gethwaddr(sc, sc->sc_enaddr); 203 if (IS_ENADDR_ZERO(sc->sc_enaddr)) { 204 /* give up. set randomly */ 205 uint32_t eaddr = random(); 206 /* not multicast */ 207 sc->sc_enaddr[0] = (eaddr >> 24) & 0xfc; 208 sc->sc_enaddr[1] = eaddr >> 16; 209 sc->sc_enaddr[2] = eaddr >> 8; 210 sc->sc_enaddr[3] = eaddr; 211 eaddr = random(); 212 sc->sc_enaddr[4] = eaddr >> 8; 213 sc->sc_enaddr[5] = eaddr; 214 215 aprint_error_dev(self, 216 "cannot get mac address. set randomly\n"); 217 } 218 } 219 enet_sethwaddr(sc, sc->sc_enaddr); 220 221 aprint_normal_dev(self, "Ethernet address %s\n", 222 ether_sprintf(sc->sc_enaddr)); 223 224 enet_init_regs(sc, 1); 225 226 /* setup interrupt handlers */ 227 if ((sc->sc_ih = intr_establish(irq, IPL_NET, 228 IST_LEVEL, enet_intr, sc)) == NULL) { 229 aprint_error_dev(self, "unable to establish interrupt\n"); 230 goto failure; 231 } 232 233 if (sc->sc_imxtype == 7) { 234 /* i.MX7 use 3 interrupts */ 235 if ((sc->sc_ih2 = intr_establish(irq + 1, IPL_NET, 236 IST_LEVEL, enet_intr, sc)) == NULL) { 237 aprint_error_dev(self, "unable to establish 2nd interrupt\n"); 238 intr_disestablish(sc->sc_ih); 239 goto failure; 240 } 241 if ((sc->sc_ih3 = intr_establish(irq + 2, IPL_NET, 242 IST_LEVEL, enet_intr, sc)) == NULL) { 243 aprint_error_dev(self, "unable to establish 3rd interrupt\n"); 244 intr_disestablish(sc->sc_ih2); 245 intr_disestablish(sc->sc_ih); 246 goto failure; 247 } 248 } 249 250 /* callout will be scheduled from enet_init() */ 251 callout_init(&sc->sc_tick_ch, 0); 252 callout_setfunc(&sc->sc_tick_ch, enet_tick, sc); 253 254 /* setup ifp */ 255 ifp = &sc->sc_ethercom.ec_if; 256 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 257 ifp->if_softc = sc; 258 ifp->if_mtu = ETHERMTU; 259 ifp->if_baudrate = IF_Gbps(1); 260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 261 ifp->if_ioctl = enet_ioctl; 262 ifp->if_start = enet_start; 263 ifp->if_init = enet_init; 264 ifp->if_stop = enet_stop; 265 ifp->if_watchdog = enet_watchdog; 266 267 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 268 #ifdef ENET_SUPPORT_JUMBO 269 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 270 #endif 271 272 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 273 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 274 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 275 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx | 276 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 277 278 IFQ_SET_MAXLEN(&ifp->if_snd, max(ENET_TX_RING_CNT, IFQ_MAXLEN)); 279 IFQ_SET_READY(&ifp->if_snd); 280 281 /* setup MII */ 282 sc->sc_ethercom.ec_mii = &sc->sc_mii; 283 sc->sc_mii.mii_ifp = ifp; 284 sc->sc_mii.mii_readreg = enet_miibus_readreg; 285 sc->sc_mii.mii_writereg = enet_miibus_writereg; 286 sc->sc_mii.mii_statchg = enet_miibus_statchg; 287 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 288 enet_mediastatus); 289 290 /* try to attach PHY */ 291 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 292 MII_OFFSET_ANY, 0); 293 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 294 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 295 0, NULL); 296 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 297 } else { 298 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 299 } 300 301 if_attach(ifp); 302 ether_ifattach(ifp, sc->sc_enaddr); 303 ether_set_ifflags_cb(&sc->sc_ethercom, enet_ifflags_cb); 304 305 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 306 RND_TYPE_NET, RND_FLAG_DEFAULT); 307 308 #ifdef ENET_EVENT_COUNTER 309 enet_attach_evcnt(sc); 310 #endif 311 312 sc->sc_stopping = false; 313 314 return; 315 316 failure: 317 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 318 return; 319 } 320 321 #ifdef ENET_EVENT_COUNTER 322 static void 323 enet_attach_evcnt(struct enet_softc *sc) 324 { 325 const char *xname; 326 327 xname = device_xname(sc->sc_dev); 328 329 #define ENET_EVCNT_ATTACH(name) \ 330 evcnt_attach_dynamic(&sc->sc_ev_ ## name, EVCNT_TYPE_MISC, \ 331 NULL, xname, #name); 332 333 ENET_EVCNT_ATTACH(t_drop); 334 ENET_EVCNT_ATTACH(t_packets); 335 ENET_EVCNT_ATTACH(t_bc_pkt); 336 ENET_EVCNT_ATTACH(t_mc_pkt); 337 ENET_EVCNT_ATTACH(t_crc_align); 338 ENET_EVCNT_ATTACH(t_undersize); 339 ENET_EVCNT_ATTACH(t_oversize); 340 ENET_EVCNT_ATTACH(t_frag); 341 ENET_EVCNT_ATTACH(t_jab); 342 ENET_EVCNT_ATTACH(t_col); 343 ENET_EVCNT_ATTACH(t_p64); 344 ENET_EVCNT_ATTACH(t_p65to127n); 345 ENET_EVCNT_ATTACH(t_p128to255n); 346 ENET_EVCNT_ATTACH(t_p256to511); 347 ENET_EVCNT_ATTACH(t_p512to1023); 348 ENET_EVCNT_ATTACH(t_p1024to2047); 349 ENET_EVCNT_ATTACH(t_p_gte2048); 350 ENET_EVCNT_ATTACH(t_octets); 351 ENET_EVCNT_ATTACH(r_packets); 352 ENET_EVCNT_ATTACH(r_bc_pkt); 353 ENET_EVCNT_ATTACH(r_mc_pkt); 354 ENET_EVCNT_ATTACH(r_crc_align); 355 ENET_EVCNT_ATTACH(r_undersize); 356 ENET_EVCNT_ATTACH(r_oversize); 357 ENET_EVCNT_ATTACH(r_frag); 358 ENET_EVCNT_ATTACH(r_jab); 359 ENET_EVCNT_ATTACH(r_p64); 360 ENET_EVCNT_ATTACH(r_p65to127); 361 ENET_EVCNT_ATTACH(r_p128to255); 362 ENET_EVCNT_ATTACH(r_p256to511); 363 ENET_EVCNT_ATTACH(r_p512to1023); 364 ENET_EVCNT_ATTACH(r_p1024to2047); 365 ENET_EVCNT_ATTACH(r_p_gte2048); 366 ENET_EVCNT_ATTACH(r_octets); 367 } 368 369 static void 370 enet_update_evcnt(struct enet_softc *sc) 371 { 372 sc->sc_ev_t_drop.ev_count += ENET_REG_READ(sc, ENET_RMON_T_DROP); 373 sc->sc_ev_t_packets.ev_count += ENET_REG_READ(sc, ENET_RMON_T_PACKETS); 374 sc->sc_ev_t_bc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_T_BC_PKT); 375 sc->sc_ev_t_mc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_T_MC_PKT); 376 sc->sc_ev_t_crc_align.ev_count += ENET_REG_READ(sc, ENET_RMON_T_CRC_ALIGN); 377 sc->sc_ev_t_undersize.ev_count += ENET_REG_READ(sc, ENET_RMON_T_UNDERSIZE); 378 sc->sc_ev_t_oversize.ev_count += ENET_REG_READ(sc, ENET_RMON_T_OVERSIZE); 379 sc->sc_ev_t_frag.ev_count += ENET_REG_READ(sc, ENET_RMON_T_FRAG); 380 sc->sc_ev_t_jab.ev_count += ENET_REG_READ(sc, ENET_RMON_T_JAB); 381 sc->sc_ev_t_col.ev_count += ENET_REG_READ(sc, ENET_RMON_T_COL); 382 sc->sc_ev_t_p64.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P64); 383 sc->sc_ev_t_p65to127n.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P65TO127N); 384 sc->sc_ev_t_p128to255n.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P128TO255N); 385 sc->sc_ev_t_p256to511.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P256TO511); 386 sc->sc_ev_t_p512to1023.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P512TO1023); 387 sc->sc_ev_t_p1024to2047.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P1024TO2047); 388 sc->sc_ev_t_p_gte2048.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P_GTE2048); 389 sc->sc_ev_t_octets.ev_count += ENET_REG_READ(sc, ENET_RMON_T_OCTETS); 390 sc->sc_ev_r_packets.ev_count += ENET_REG_READ(sc, ENET_RMON_R_PACKETS); 391 sc->sc_ev_r_bc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_R_BC_PKT); 392 sc->sc_ev_r_mc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_R_MC_PKT); 393 sc->sc_ev_r_crc_align.ev_count += ENET_REG_READ(sc, ENET_RMON_R_CRC_ALIGN); 394 sc->sc_ev_r_undersize.ev_count += ENET_REG_READ(sc, ENET_RMON_R_UNDERSIZE); 395 sc->sc_ev_r_oversize.ev_count += ENET_REG_READ(sc, ENET_RMON_R_OVERSIZE); 396 sc->sc_ev_r_frag.ev_count += ENET_REG_READ(sc, ENET_RMON_R_FRAG); 397 sc->sc_ev_r_jab.ev_count += ENET_REG_READ(sc, ENET_RMON_R_JAB); 398 sc->sc_ev_r_p64.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P64); 399 sc->sc_ev_r_p65to127.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P65TO127); 400 sc->sc_ev_r_p128to255.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P128TO255); 401 sc->sc_ev_r_p256to511.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P256TO511); 402 sc->sc_ev_r_p512to1023.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P512TO1023); 403 sc->sc_ev_r_p1024to2047.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P1024TO2047); 404 sc->sc_ev_r_p_gte2048.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P_GTE2048); 405 sc->sc_ev_r_octets.ev_count += ENET_REG_READ(sc, ENET_RMON_R_OCTETS); 406 } 407 #endif /* ENET_EVENT_COUNTER */ 408 409 static void 410 enet_tick(void *arg) 411 { 412 struct enet_softc *sc; 413 struct mii_data *mii; 414 struct ifnet *ifp; 415 int s; 416 417 sc = arg; 418 mii = &sc->sc_mii; 419 ifp = &sc->sc_ethercom.ec_if; 420 421 s = splnet(); 422 423 if (sc->sc_stopping) 424 goto out; 425 426 #ifdef ENET_EVENT_COUNTER 427 enet_update_evcnt(sc); 428 #endif 429 430 /* update counters */ 431 ifp->if_ierrors += ENET_REG_READ(sc, ENET_RMON_R_UNDERSIZE); 432 ifp->if_ierrors += ENET_REG_READ(sc, ENET_RMON_R_FRAG); 433 ifp->if_ierrors += ENET_REG_READ(sc, ENET_RMON_R_JAB); 434 435 /* clear counters */ 436 ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR); 437 ENET_REG_WRITE(sc, ENET_MIBC, 0); 438 439 mii_tick(mii); 440 out: 441 442 if (!sc->sc_stopping) 443 callout_schedule(&sc->sc_tick_ch, ENET_TICK); 444 445 splx(s); 446 } 447 448 static int 449 enet_intr(void *arg) 450 { 451 struct enet_softc *sc; 452 struct ifnet *ifp; 453 uint32_t status; 454 455 sc = arg; 456 status = ENET_REG_READ(sc, ENET_EIR); 457 458 if (sc->sc_imxtype == 7) { 459 if (status & (ENET_EIR_TXF|ENET_EIR_TXF1|ENET_EIR_TXF2)) 460 enet_tx_intr(arg); 461 if (status & (ENET_EIR_RXF|ENET_EIR_RXF1|ENET_EIR_RXF2)) 462 enet_rx_intr(arg); 463 } else { 464 if (status & ENET_EIR_TXF) 465 enet_tx_intr(arg); 466 if (status & ENET_EIR_RXF) 467 enet_rx_intr(arg); 468 } 469 470 if (status & ENET_EIR_EBERR) { 471 device_printf(sc->sc_dev, "Ethernet Bus Error\n"); 472 ifp = &sc->sc_ethercom.ec_if; 473 enet_stop(ifp, 1); 474 enet_init(ifp); 475 } else { 476 ENET_REG_WRITE(sc, ENET_EIR, status); 477 } 478 479 rnd_add_uint32(&sc->sc_rnd_source, status); 480 481 return 1; 482 } 483 484 static int 485 enet_tx_intr(void *arg) 486 { 487 struct enet_softc *sc; 488 struct ifnet *ifp; 489 struct enet_txsoft *txs; 490 int idx; 491 492 sc = (struct enet_softc *)arg; 493 ifp = &sc->sc_ethercom.ec_if; 494 495 for (idx = sc->sc_tx_considx; idx != sc->sc_tx_prodidx; 496 idx = ENET_TX_NEXTIDX(idx)) { 497 498 txs = &sc->sc_txsoft[idx]; 499 500 TXDESC_READIN(idx); 501 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_R) { 502 /* This TX Descriptor has not been transmitted yet */ 503 break; 504 } 505 506 /* txsoft is available on first segment (TXFLAGS1_T1) */ 507 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_T1) { 508 bus_dmamap_unload(sc->sc_dmat, 509 txs->txs_dmamap); 510 m_freem(txs->txs_mbuf); 511 ifp->if_opackets++; 512 } 513 514 /* checking error */ 515 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_L) { 516 uint32_t flags2; 517 518 flags2 = sc->sc_txdesc_ring[idx].tx_flags2; 519 520 if (flags2 & (TXFLAGS2_TXE | 521 TXFLAGS2_UE | TXFLAGS2_EE | TXFLAGS2_FE | 522 TXFLAGS2_LCE | TXFLAGS2_OE | TXFLAGS2_TSE)) { 523 #ifdef DEBUG_ENET 524 if (enet_debug) { 525 char flagsbuf[128]; 526 527 snprintb(flagsbuf, sizeof(flagsbuf), 528 "\20" "\20TRANSMIT" "\16UNDERFLOW" 529 "\15COLLISION" "\14FRAME" 530 "\13LATECOLLISION" "\12OVERFLOW", 531 flags2); 532 533 device_printf(sc->sc_dev, 534 "txdesc[%d]: transmit error: " 535 "flags2=%s\n", idx, flagsbuf); 536 } 537 #endif /* DEBUG_ENET */ 538 ifp->if_oerrors++; 539 } 540 } 541 542 sc->sc_tx_free++; 543 } 544 sc->sc_tx_considx = idx; 545 546 if (sc->sc_tx_free > 0) 547 ifp->if_flags &= ~IFF_OACTIVE; 548 549 /* 550 * No more pending TX descriptor, 551 * cancel the watchdog timer. 552 */ 553 if (sc->sc_tx_free == ENET_TX_RING_CNT) 554 ifp->if_timer = 0; 555 556 return 1; 557 } 558 559 static int 560 enet_rx_intr(void *arg) 561 { 562 struct enet_softc *sc; 563 struct ifnet *ifp; 564 struct enet_rxsoft *rxs; 565 int idx, len, amount; 566 uint32_t flags1, flags2; 567 struct mbuf *m, *m0, *mprev; 568 569 sc = arg; 570 ifp = &sc->sc_ethercom.ec_if; 571 572 m0 = mprev = NULL; 573 amount = 0; 574 for (idx = sc->sc_rx_readidx; ; idx = ENET_RX_NEXTIDX(idx)) { 575 576 rxs = &sc->sc_rxsoft[idx]; 577 578 RXDESC_READIN(idx); 579 if (sc->sc_rxdesc_ring[idx].rx_flags1_len & RXFLAGS1_E) { 580 /* This RX Descriptor has not been received yet */ 581 break; 582 } 583 584 /* 585 * build mbuf from RX Descriptor if needed 586 */ 587 m = rxs->rxs_mbuf; 588 rxs->rxs_mbuf = NULL; 589 590 flags1 = sc->sc_rxdesc_ring[idx].rx_flags1_len; 591 len = RXFLAGS1_LEN(flags1); 592 593 #define RACC_SHIFT16 2 594 if (m0 == NULL) { 595 m0 = m; 596 m_adj(m0, RACC_SHIFT16); 597 len -= RACC_SHIFT16; 598 m->m_len = len; 599 amount = len; 600 } else { 601 if (flags1 & RXFLAGS1_L) 602 len = len - amount - RACC_SHIFT16; 603 604 m->m_len = len; 605 amount += len; 606 m->m_flags &= ~M_PKTHDR; 607 mprev->m_next = m; 608 } 609 mprev = m; 610 611 flags2 = sc->sc_rxdesc_ring[idx].rx_flags2; 612 613 if (flags1 & RXFLAGS1_L) { 614 /* last buffer */ 615 if ((amount < ETHER_HDR_LEN) || 616 ((flags1 & (RXFLAGS1_LG | RXFLAGS1_NO | 617 RXFLAGS1_CR | RXFLAGS1_OV | RXFLAGS1_TR)) || 618 (flags2 & (RXFLAGS2_ME | RXFLAGS2_PE | 619 RXFLAGS2_CE)))) { 620 621 #ifdef DEBUG_ENET 622 if (enet_debug) { 623 char flags1buf[128], flags2buf[128]; 624 snprintb(flags1buf, sizeof(flags1buf), 625 "\20" "\31MISS" "\26LENGTHVIOLATION" 626 "\25NONOCTET" "\23CRC" "\22OVERRUN" 627 "\21TRUNCATED", flags1); 628 snprintb(flags2buf, sizeof(flags2buf), 629 "\20" "\40MAC" "\33PHY" 630 "\32COLLISION", flags2); 631 632 DEVICE_DPRINTF( 633 "rxdesc[%d]: receive error: " 634 "flags1=%s,flags2=%s,len=%d\n", 635 idx, flags1buf, flags2buf, amount); 636 } 637 #endif /* DEBUG_ENET */ 638 ifp->if_ierrors++; 639 m_freem(m0); 640 641 } else { 642 /* packet receive ok */ 643 m_set_rcvif(m0, ifp); 644 m0->m_pkthdr.len = amount; 645 646 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 647 rxs->rxs_dmamap->dm_mapsize, 648 BUS_DMASYNC_PREREAD); 649 650 if (ifp->if_csum_flags_rx & (M_CSUM_IPv4 | 651 M_CSUM_TCPv4 | M_CSUM_UDPv4 | 652 M_CSUM_TCPv6 | M_CSUM_UDPv6)) 653 enet_rx_csum(sc, ifp, m0, idx); 654 655 if_percpuq_enqueue(ifp->if_percpuq, m0); 656 } 657 658 m0 = NULL; 659 mprev = NULL; 660 amount = 0; 661 662 } else { 663 /* continued from previous buffer */ 664 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 665 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 666 } 667 668 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 669 if (enet_alloc_rxbuf(sc, idx) != 0) { 670 panic("enet_alloc_rxbuf NULL\n"); 671 } 672 } 673 sc->sc_rx_readidx = idx; 674 675 /* re-enable RX DMA to make sure */ 676 ENET_REG_WRITE(sc, ENET_RDAR, ENET_RDAR_ACTIVE); 677 678 return 1; 679 } 680 681 static void 682 enet_rx_csum(struct enet_softc *sc, struct ifnet *ifp, struct mbuf *m, int idx) 683 { 684 uint32_t flags2; 685 uint8_t proto; 686 687 flags2 = sc->sc_rxdesc_ring[idx].rx_flags2; 688 689 if (flags2 & RXFLAGS2_IPV6) { 690 proto = sc->sc_rxdesc_ring[idx].rx_proto; 691 692 /* RXFLAGS2_PCR is valid when IPv6 and TCP/UDP */ 693 if ((proto == IPPROTO_TCP) && 694 (ifp->if_csum_flags_rx & M_CSUM_TCPv6)) 695 m->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 696 else if ((proto == IPPROTO_UDP) && 697 (ifp->if_csum_flags_rx & M_CSUM_UDPv6)) 698 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 699 else 700 return; 701 702 /* IPv6 protocol checksum error */ 703 if (flags2 & RXFLAGS2_PCR) 704 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 705 706 } else { 707 struct ether_header *eh; 708 uint8_t *ip; 709 710 eh = mtod(m, struct ether_header *); 711 712 /* XXX: is an IPv4? */ 713 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 714 return; 715 ip = (uint8_t *)(eh + 1); 716 if ((ip[0] & 0xf0) == 0x40) 717 return; 718 719 proto = sc->sc_rxdesc_ring[idx].rx_proto; 720 if (flags2 & RXFLAGS2_ICE) { 721 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 722 m->m_pkthdr.csum_flags |= 723 M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 724 } 725 } else { 726 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 727 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 728 } 729 730 /* 731 * PCR is valid when 732 * ICE == 0 and FRAG == 0 733 */ 734 if (flags2 & RXFLAGS2_FRAG) 735 return; 736 737 /* 738 * PCR is valid when proto is TCP or UDP 739 */ 740 if ((proto == IPPROTO_TCP) && 741 (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 742 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 743 else if ((proto == IPPROTO_UDP) && 744 (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 745 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 746 else 747 return; 748 749 /* IPv4 protocol cksum error */ 750 if (flags2 & RXFLAGS2_PCR) 751 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 752 } 753 } 754 } 755 756 static void 757 enet_setmulti(struct enet_softc *sc) 758 { 759 struct ifnet *ifp; 760 struct ether_multi *enm; 761 struct ether_multistep step; 762 int promisc; 763 uint32_t crc; 764 uint32_t gaddr[2]; 765 766 ifp = &sc->sc_ethercom.ec_if; 767 768 promisc = 0; 769 if ((ifp->if_flags & IFF_PROMISC) || sc->sc_ethercom.ec_multicnt > 0) { 770 ifp->if_flags |= IFF_ALLMULTI; 771 if (ifp->if_flags & IFF_PROMISC) 772 promisc = 1; 773 gaddr[0] = gaddr[1] = 0xffffffff; 774 } else { 775 gaddr[0] = gaddr[1] = 0; 776 777 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 778 while (enm != NULL) { 779 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 780 gaddr[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 781 ETHER_NEXT_MULTI(step, enm); 782 } 783 } 784 785 ENET_REG_WRITE(sc, ENET_GAUR, gaddr[0]); 786 ENET_REG_WRITE(sc, ENET_GALR, gaddr[1]); 787 788 if (promisc) { 789 /* match all packet */ 790 ENET_REG_WRITE(sc, ENET_IAUR, 0xffffffff); 791 ENET_REG_WRITE(sc, ENET_IALR, 0xffffffff); 792 } else { 793 /* don't match any packet */ 794 ENET_REG_WRITE(sc, ENET_IAUR, 0); 795 ENET_REG_WRITE(sc, ENET_IALR, 0); 796 } 797 } 798 799 static void 800 enet_gethwaddr(struct enet_softc *sc, uint8_t *hwaddr) 801 { 802 uint32_t paddr; 803 804 paddr = ENET_REG_READ(sc, ENET_PALR); 805 hwaddr[0] = paddr >> 24; 806 hwaddr[1] = paddr >> 16; 807 hwaddr[2] = paddr >> 8; 808 hwaddr[3] = paddr; 809 810 paddr = ENET_REG_READ(sc, ENET_PAUR); 811 hwaddr[4] = paddr >> 24; 812 hwaddr[5] = paddr >> 16; 813 } 814 815 static void 816 enet_sethwaddr(struct enet_softc *sc, uint8_t *hwaddr) 817 { 818 uint32_t paddr; 819 820 paddr = (hwaddr[0] << 24) | (hwaddr[1] << 16) | (hwaddr[2] << 8) | 821 hwaddr[3]; 822 ENET_REG_WRITE(sc, ENET_PALR, paddr); 823 paddr = (hwaddr[4] << 24) | (hwaddr[5] << 16); 824 ENET_REG_WRITE(sc, ENET_PAUR, paddr); 825 } 826 827 /* 828 * ifnet interfaces 829 */ 830 static int 831 enet_init(struct ifnet *ifp) 832 { 833 struct enet_softc *sc; 834 int s, error; 835 836 sc = ifp->if_softc; 837 838 s = splnet(); 839 840 enet_init_regs(sc, 0); 841 enet_init_txring(sc); 842 error = enet_init_rxring(sc); 843 if (error != 0) { 844 enet_drain_rxbuf(sc); 845 device_printf(sc->sc_dev, "Cannot allocate mbuf cluster\n"); 846 goto init_failure; 847 } 848 849 /* reload mac address */ 850 memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 851 enet_sethwaddr(sc, sc->sc_enaddr); 852 853 /* program multicast address */ 854 enet_setmulti(sc); 855 856 /* update if_flags */ 857 ifp->if_flags |= IFF_RUNNING; 858 ifp->if_flags &= ~IFF_OACTIVE; 859 860 /* update local copy of if_flags */ 861 sc->sc_if_flags = ifp->if_flags; 862 863 /* mii */ 864 mii_mediachg(&sc->sc_mii); 865 866 /* enable RX DMA */ 867 ENET_REG_WRITE(sc, ENET_RDAR, ENET_RDAR_ACTIVE); 868 869 sc->sc_stopping = false; 870 callout_schedule(&sc->sc_tick_ch, ENET_TICK); 871 872 init_failure: 873 splx(s); 874 875 return error; 876 } 877 878 static void 879 enet_start(struct ifnet *ifp) 880 { 881 struct enet_softc *sc; 882 struct mbuf *m; 883 int npkt; 884 885 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 886 return; 887 888 sc = ifp->if_softc; 889 for (npkt = 0; ; npkt++) { 890 IFQ_POLL(&ifp->if_snd, m); 891 if (m == NULL) 892 break; 893 894 if (sc->sc_tx_free <= 0) { 895 /* no tx descriptor now... */ 896 ifp->if_flags |= IFF_OACTIVE; 897 DEVICE_DPRINTF("TX descriptor is full\n"); 898 break; 899 } 900 901 IFQ_DEQUEUE(&ifp->if_snd, m); 902 903 if (enet_encap_txring(sc, &m) != 0) { 904 /* too many mbuf chains? */ 905 ifp->if_flags |= IFF_OACTIVE; 906 DEVICE_DPRINTF( 907 "TX descriptor is full. dropping packet\n"); 908 m_freem(m); 909 ifp->if_oerrors++; 910 break; 911 } 912 913 /* Pass the packet to any BPF listeners */ 914 bpf_mtap(ifp, m); 915 } 916 917 if (npkt) { 918 /* enable TX DMA */ 919 ENET_REG_WRITE(sc, ENET_TDAR, ENET_TDAR_ACTIVE); 920 921 ifp->if_timer = 5; 922 } 923 } 924 925 static void 926 enet_stop(struct ifnet *ifp, int disable) 927 { 928 struct enet_softc *sc; 929 int s; 930 uint32_t v; 931 932 sc = ifp->if_softc; 933 934 s = splnet(); 935 936 sc->sc_stopping = true; 937 callout_stop(&sc->sc_tick_ch); 938 939 /* clear ENET_ECR[ETHEREN] to abort receive and transmit */ 940 v = ENET_REG_READ(sc, ENET_ECR); 941 ENET_REG_WRITE(sc, ENET_ECR, v & ~ENET_ECR_ETHEREN); 942 943 /* Mark the interface as down and cancel the watchdog timer. */ 944 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 945 ifp->if_timer = 0; 946 947 if (disable) { 948 enet_drain_txbuf(sc); 949 enet_drain_rxbuf(sc); 950 } 951 952 splx(s); 953 } 954 955 static void 956 enet_watchdog(struct ifnet *ifp) 957 { 958 struct enet_softc *sc; 959 int s; 960 961 sc = ifp->if_softc; 962 s = splnet(); 963 964 device_printf(sc->sc_dev, "watchdog timeout\n"); 965 ifp->if_oerrors++; 966 967 /* salvage packets left in descriptors */ 968 enet_tx_intr(sc); 969 enet_rx_intr(sc); 970 971 /* reset */ 972 enet_stop(ifp, 1); 973 enet_init(ifp); 974 975 splx(s); 976 } 977 978 static void 979 enet_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 980 { 981 struct enet_softc *sc = ifp->if_softc; 982 983 ether_mediastatus(ifp, ifmr); 984 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 985 | sc->sc_flowflags; 986 } 987 988 static int 989 enet_ifflags_cb(struct ethercom *ec) 990 { 991 struct ifnet *ifp = &ec->ec_if; 992 struct enet_softc *sc = ifp->if_softc; 993 int change = ifp->if_flags ^ sc->sc_if_flags; 994 995 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 996 return ENETRESET; 997 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 998 return 0; 999 1000 enet_setmulti(sc); 1001 1002 sc->sc_if_flags = ifp->if_flags; 1003 return 0; 1004 } 1005 1006 static int 1007 enet_ioctl(struct ifnet *ifp, u_long command, void *data) 1008 { 1009 struct enet_softc *sc; 1010 struct ifreq *ifr; 1011 int s, error; 1012 uint32_t v; 1013 1014 sc = ifp->if_softc; 1015 ifr = data; 1016 1017 error = 0; 1018 1019 s = splnet(); 1020 1021 switch (command) { 1022 case SIOCSIFMTU: 1023 if (MTU2FRAMESIZE(ifr->ifr_mtu) > ENET_MAX_PKT_LEN) { 1024 error = EINVAL; 1025 } else { 1026 ifp->if_mtu = ifr->ifr_mtu; 1027 1028 /* set maximum frame length */ 1029 v = MTU2FRAMESIZE(ifr->ifr_mtu); 1030 ENET_REG_WRITE(sc, ENET_FTRL, v); 1031 v = ENET_REG_READ(sc, ENET_RCR); 1032 v &= ~ENET_RCR_MAX_FL(0x3fff); 1033 v |= ENET_RCR_MAX_FL(ifp->if_mtu + 1034 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 1035 ENET_REG_WRITE(sc, ENET_RCR, v); 1036 } 1037 break; 1038 case SIOCSIFMEDIA: 1039 case SIOCGIFMEDIA: 1040 /* Flow control requires full-duplex mode. */ 1041 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1042 (ifr->ifr_media & IFM_FDX) == 0) 1043 ifr->ifr_media &= ~IFM_ETH_FMASK; 1044 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1045 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1046 /* We can do both TXPAUSE and RXPAUSE. */ 1047 ifr->ifr_media |= 1048 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1049 } 1050 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1051 } 1052 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1053 break; 1054 default: 1055 error = ether_ioctl(ifp, command, data); 1056 if (error != ENETRESET) 1057 break; 1058 1059 /* post-process */ 1060 error = 0; 1061 switch (command) { 1062 case SIOCSIFCAP: 1063 error = (*ifp->if_init)(ifp); 1064 break; 1065 case SIOCADDMULTI: 1066 case SIOCDELMULTI: 1067 if (ifp->if_flags & IFF_RUNNING) 1068 enet_setmulti(sc); 1069 break; 1070 } 1071 break; 1072 } 1073 1074 splx(s); 1075 1076 return error; 1077 } 1078 1079 /* 1080 * for MII 1081 */ 1082 static int 1083 enet_miibus_readreg(device_t dev, int phy, int reg) 1084 { 1085 struct enet_softc *sc; 1086 int timeout; 1087 uint32_t val, status; 1088 1089 sc = device_private(dev); 1090 1091 /* clear MII update */ 1092 ENET_REG_WRITE(sc, ENET_EIR, ENET_EIR_MII); 1093 1094 /* read command */ 1095 ENET_REG_WRITE(sc, ENET_MMFR, 1096 ENET_MMFR_ST | ENET_MMFR_OP_READ | ENET_MMFR_TA | 1097 ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy)); 1098 1099 /* check MII update */ 1100 for (timeout = 5000; timeout > 0; --timeout) { 1101 status = ENET_REG_READ(sc, ENET_EIR); 1102 if (status & ENET_EIR_MII) 1103 break; 1104 } 1105 if (timeout <= 0) { 1106 DEVICE_DPRINTF("MII read timeout: reg=0x%02x\n", 1107 reg); 1108 val = -1; 1109 } else { 1110 val = ENET_REG_READ(sc, ENET_MMFR) & ENET_MMFR_DATAMASK; 1111 } 1112 1113 return val; 1114 } 1115 1116 static void 1117 enet_miibus_writereg(device_t dev, int phy, int reg, int val) 1118 { 1119 struct enet_softc *sc; 1120 int timeout; 1121 1122 sc = device_private(dev); 1123 1124 /* clear MII update */ 1125 ENET_REG_WRITE(sc, ENET_EIR, ENET_EIR_MII); 1126 1127 /* write command */ 1128 ENET_REG_WRITE(sc, ENET_MMFR, 1129 ENET_MMFR_ST | ENET_MMFR_OP_WRITE | ENET_MMFR_TA | 1130 ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy) | 1131 (ENET_MMFR_DATAMASK & val)); 1132 1133 /* check MII update */ 1134 for (timeout = 5000; timeout > 0; --timeout) { 1135 if (ENET_REG_READ(sc, ENET_EIR) & ENET_EIR_MII) 1136 break; 1137 } 1138 if (timeout <= 0) { 1139 DEVICE_DPRINTF("MII write timeout: reg=0x%02x\n", 1140 reg); 1141 } 1142 } 1143 1144 static void 1145 enet_miibus_statchg(struct ifnet *ifp) 1146 { 1147 struct enet_softc *sc; 1148 struct mii_data *mii; 1149 struct ifmedia_entry *ife; 1150 uint32_t ecr, ecr0; 1151 uint32_t rcr, rcr0; 1152 uint32_t tcr, tcr0; 1153 1154 sc = ifp->if_softc; 1155 mii = &sc->sc_mii; 1156 ife = mii->mii_media.ifm_cur; 1157 1158 /* get current status */ 1159 ecr0 = ecr = ENET_REG_READ(sc, ENET_ECR) & ~ENET_ECR_RESET; 1160 rcr0 = rcr = ENET_REG_READ(sc, ENET_RCR); 1161 tcr0 = tcr = ENET_REG_READ(sc, ENET_TCR); 1162 1163 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1164 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 1165 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1166 mii->mii_media_active &= ~IFM_ETH_FMASK; 1167 } 1168 1169 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1170 tcr |= ENET_TCR_FDEN; /* full duplex */ 1171 rcr &= ~ENET_RCR_DRT;; /* enable receive on transmit */ 1172 } else { 1173 tcr &= ~ENET_TCR_FDEN; /* half duplex */ 1174 rcr |= ENET_RCR_DRT; /* disable receive on transmit */ 1175 } 1176 1177 if ((tcr ^ tcr0) & ENET_TCR_FDEN) { 1178 /* 1179 * need to reset because 1180 * FDEN can change when ECR[ETHEREN] is 0 1181 */ 1182 enet_init_regs(sc, 0); 1183 return; 1184 } 1185 1186 switch (IFM_SUBTYPE(ife->ifm_media)) { 1187 case IFM_AUTO: 1188 case IFM_1000_T: 1189 ecr |= ENET_ECR_SPEED; /* 1000Mbps mode */ 1190 break; 1191 case IFM_100_TX: 1192 ecr &= ~ENET_ECR_SPEED; /* 100Mbps mode */ 1193 rcr &= ~ENET_RCR_RMII_10T; /* 100Mbps mode */ 1194 break; 1195 case IFM_10_T: 1196 ecr &= ~ENET_ECR_SPEED; /* 10Mbps mode */ 1197 rcr |= ENET_RCR_RMII_10T; /* 10Mbps mode */ 1198 break; 1199 default: 1200 ecr = ecr0; 1201 rcr = rcr0; 1202 tcr = tcr0; 1203 break; 1204 } 1205 1206 if (sc->sc_flowflags & IFM_FLOW) 1207 rcr |= ENET_RCR_FCE; 1208 else 1209 rcr &= ~ENET_RCR_FCE; 1210 1211 /* update registers if need change */ 1212 if (ecr != ecr0) 1213 ENET_REG_WRITE(sc, ENET_ECR, ecr); 1214 if (rcr != rcr0) 1215 ENET_REG_WRITE(sc, ENET_RCR, rcr); 1216 if (tcr != tcr0) 1217 ENET_REG_WRITE(sc, ENET_TCR, tcr); 1218 } 1219 1220 /* 1221 * handling descriptors 1222 */ 1223 static void 1224 enet_init_txring(struct enet_softc *sc) 1225 { 1226 int i; 1227 1228 /* build TX ring */ 1229 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1230 sc->sc_txdesc_ring[i].tx_flags1_len = 1231 ((i == (ENET_TX_RING_CNT - 1)) ? TXFLAGS1_W : 0); 1232 sc->sc_txdesc_ring[i].tx_databuf = 0; 1233 sc->sc_txdesc_ring[i].tx_flags2 = TXFLAGS2_INT; 1234 sc->sc_txdesc_ring[i].tx__reserved1 = 0; 1235 sc->sc_txdesc_ring[i].tx_flags3 = 0; 1236 sc->sc_txdesc_ring[i].tx_1588timestamp = 0; 1237 sc->sc_txdesc_ring[i].tx__reserved2 = 0; 1238 sc->sc_txdesc_ring[i].tx__reserved3 = 0; 1239 1240 TXDESC_WRITEOUT(i); 1241 } 1242 1243 sc->sc_tx_free = ENET_TX_RING_CNT; 1244 sc->sc_tx_considx = 0; 1245 sc->sc_tx_prodidx = 0; 1246 } 1247 1248 static int 1249 enet_init_rxring(struct enet_softc *sc) 1250 { 1251 int i, error; 1252 1253 /* build RX ring */ 1254 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1255 error = enet_alloc_rxbuf(sc, i); 1256 if (error != 0) 1257 return error; 1258 } 1259 1260 sc->sc_rx_readidx = 0; 1261 1262 return 0; 1263 } 1264 1265 static int 1266 enet_alloc_rxbuf(struct enet_softc *sc, int idx) 1267 { 1268 struct mbuf *m; 1269 int error; 1270 1271 KASSERT((idx >= 0) && (idx < ENET_RX_RING_CNT)); 1272 1273 /* free mbuf if already allocated */ 1274 if (sc->sc_rxsoft[idx].rxs_mbuf != NULL) { 1275 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap); 1276 m_freem(sc->sc_rxsoft[idx].rxs_mbuf); 1277 sc->sc_rxsoft[idx].rxs_mbuf = NULL; 1278 } 1279 1280 /* allocate new mbuf cluster */ 1281 MGETHDR(m, M_DONTWAIT, MT_DATA); 1282 if (m == NULL) 1283 return ENOBUFS; 1284 MCLGET(m, M_DONTWAIT); 1285 if (!(m->m_flags & M_EXT)) { 1286 m_freem(m); 1287 return ENOBUFS; 1288 } 1289 m->m_len = MCLBYTES; 1290 m->m_next = NULL; 1291 1292 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 1293 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1294 BUS_DMA_READ | BUS_DMA_NOWAIT); 1295 if (error) { 1296 m_freem(m); 1297 return error; 1298 } 1299 1300 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 0, 1301 sc->sc_rxsoft[idx].rxs_dmamap->dm_mapsize, 1302 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1303 1304 sc->sc_rxsoft[idx].rxs_mbuf = m; 1305 enet_reset_rxdesc(sc, idx); 1306 return 0; 1307 } 1308 1309 static void 1310 enet_reset_rxdesc(struct enet_softc *sc, int idx) 1311 { 1312 uint32_t paddr; 1313 1314 paddr = sc->sc_rxsoft[idx].rxs_dmamap->dm_segs[0].ds_addr; 1315 1316 sc->sc_rxdesc_ring[idx].rx_flags1_len = 1317 RXFLAGS1_E | 1318 ((idx == (ENET_RX_RING_CNT - 1)) ? RXFLAGS1_W : 0); 1319 sc->sc_rxdesc_ring[idx].rx_databuf = paddr; 1320 sc->sc_rxdesc_ring[idx].rx_flags2 = 1321 RXFLAGS2_INT; 1322 sc->sc_rxdesc_ring[idx].rx_hl = 0; 1323 sc->sc_rxdesc_ring[idx].rx_proto = 0; 1324 sc->sc_rxdesc_ring[idx].rx_cksum = 0; 1325 sc->sc_rxdesc_ring[idx].rx_flags3 = 0; 1326 sc->sc_rxdesc_ring[idx].rx_1588timestamp = 0; 1327 sc->sc_rxdesc_ring[idx].rx__reserved2 = 0; 1328 sc->sc_rxdesc_ring[idx].rx__reserved3 = 0; 1329 1330 RXDESC_WRITEOUT(idx); 1331 } 1332 1333 static void 1334 enet_drain_txbuf(struct enet_softc *sc) 1335 { 1336 int idx; 1337 struct enet_txsoft *txs; 1338 struct ifnet *ifp; 1339 1340 ifp = &sc->sc_ethercom.ec_if; 1341 1342 for (idx = sc->sc_tx_considx; idx != sc->sc_tx_prodidx; 1343 idx = ENET_TX_NEXTIDX(idx)) { 1344 1345 /* txsoft[] is used only first segment */ 1346 txs = &sc->sc_txsoft[idx]; 1347 TXDESC_READIN(idx); 1348 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_T1) { 1349 sc->sc_txdesc_ring[idx].tx_flags1_len = 0; 1350 bus_dmamap_unload(sc->sc_dmat, 1351 txs->txs_dmamap); 1352 m_freem(txs->txs_mbuf); 1353 1354 ifp->if_oerrors++; 1355 } 1356 sc->sc_tx_free++; 1357 } 1358 } 1359 1360 static void 1361 enet_drain_rxbuf(struct enet_softc *sc) 1362 { 1363 int i; 1364 1365 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1366 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) { 1367 sc->sc_rxdesc_ring[i].rx_flags1_len = 0; 1368 bus_dmamap_unload(sc->sc_dmat, 1369 sc->sc_rxsoft[i].rxs_dmamap); 1370 m_freem(sc->sc_rxsoft[i].rxs_mbuf); 1371 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1372 } 1373 } 1374 } 1375 1376 static int 1377 enet_alloc_ring(struct enet_softc *sc) 1378 { 1379 int i, error; 1380 1381 /* 1382 * build DMA maps for TX. 1383 * TX descriptor must be able to contain mbuf chains, 1384 * so, make up ENET_MAX_PKT_NSEGS dmamap. 1385 */ 1386 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1387 error = bus_dmamap_create(sc->sc_dmat, ENET_MAX_PKT_LEN, 1388 ENET_MAX_PKT_NSEGS, ENET_MAX_PKT_LEN, 0, BUS_DMA_NOWAIT, 1389 &sc->sc_txsoft[i].txs_dmamap); 1390 1391 if (error) { 1392 aprint_error_dev(sc->sc_dev, 1393 "can't create DMA map for TX descs\n"); 1394 goto fail_1; 1395 } 1396 } 1397 1398 /* 1399 * build DMA maps for RX. 1400 * RX descripter contains An mbuf cluster, 1401 * and make up a dmamap. 1402 */ 1403 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1404 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1405 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1406 &sc->sc_rxsoft[i].rxs_dmamap); 1407 if (error) { 1408 aprint_error_dev(sc->sc_dev, 1409 "can't create DMA map for RX descs\n"); 1410 goto fail_2; 1411 } 1412 } 1413 1414 if (enet_alloc_dma(sc, sizeof(struct enet_txdesc) * ENET_TX_RING_CNT, 1415 (void **)&(sc->sc_txdesc_ring), &(sc->sc_txdesc_dmamap)) != 0) 1416 return -1; 1417 memset(sc->sc_txdesc_ring, 0, 1418 sizeof(struct enet_txdesc) * ENET_TX_RING_CNT); 1419 1420 if (enet_alloc_dma(sc, sizeof(struct enet_rxdesc) * ENET_RX_RING_CNT, 1421 (void **)&(sc->sc_rxdesc_ring), &(sc->sc_rxdesc_dmamap)) != 0) 1422 return -1; 1423 memset(sc->sc_rxdesc_ring, 0, 1424 sizeof(struct enet_rxdesc) * ENET_RX_RING_CNT); 1425 1426 return 0; 1427 1428 fail_2: 1429 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1430 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1431 bus_dmamap_destroy(sc->sc_dmat, 1432 sc->sc_rxsoft[i].rxs_dmamap); 1433 } 1434 fail_1: 1435 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1436 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1437 bus_dmamap_destroy(sc->sc_dmat, 1438 sc->sc_txsoft[i].txs_dmamap); 1439 } 1440 return error; 1441 } 1442 1443 static int 1444 enet_encap_mbufalign(struct mbuf **mp) 1445 { 1446 struct mbuf *m, *m0, *mt, *p, *x; 1447 void *ap; 1448 uint32_t alignoff, chiplen; 1449 1450 /* 1451 * iMX6 SoC ethernet controller requires 1452 * address of buffer must aligned 8, and 1453 * length of buffer must be greater than 10 (first fragment only?) 1454 */ 1455 #define ALIGNBYTE 8 1456 #define MINBUFSIZE 10 1457 #define ALIGN_PTR(p, align) \ 1458 (void *)(((uintptr_t)(p) + ((align) - 1)) & -(align)) 1459 1460 m0 = *mp; 1461 mt = p = NULL; 1462 for (m = m0; m != NULL; m = m->m_next) { 1463 alignoff = (uintptr_t)m->m_data & (ALIGNBYTE - 1); 1464 if (m->m_len < (ALIGNBYTE * 2)) { 1465 /* 1466 * rearrange mbuf data aligned 1467 * 1468 * align 8 * * * * * 1469 * +0123456789abcdef0123456789abcdef0 1470 * FROM m->m_data[___________abcdefghijklmn_______] 1471 * 1472 * +0123456789abcdef0123456789abcdef0 1473 * TO m->m_data[________abcdefghijklm___________] or 1474 * m->m_data[________________abcdefghijklmn__] 1475 */ 1476 if ((alignoff != 0) && (m->m_len != 0)) { 1477 chiplen = ALIGNBYTE - alignoff; 1478 if (M_LEADINGSPACE(m) >= alignoff) { 1479 ap = m->m_data - alignoff; 1480 memmove(ap, m->m_data, m->m_len); 1481 m->m_data = ap; 1482 } else if (M_TRAILINGSPACE(m) >= chiplen) { 1483 ap = m->m_data + chiplen; 1484 memmove(ap, m->m_data, m->m_len); 1485 m->m_data = ap; 1486 } else { 1487 /* 1488 * no space to align data. (M_READONLY?) 1489 * allocate new mbuf aligned, 1490 * and copy to it. 1491 */ 1492 MGET(x, M_DONTWAIT, m->m_type); 1493 if (x == NULL) { 1494 m_freem(m); 1495 return ENOBUFS; 1496 } 1497 MCLAIM(x, m->m_owner); 1498 if (m->m_flags & M_PKTHDR) 1499 M_MOVE_PKTHDR(x, m); 1500 x->m_len = m->m_len; 1501 x->m_data = ALIGN_PTR(x->m_data, 1502 ALIGNBYTE); 1503 memcpy(mtod(x, void *), mtod(m, void *), 1504 m->m_len); 1505 p->m_next = x; 1506 x->m_next = m_free(m); 1507 m = x; 1508 } 1509 } 1510 1511 /* 1512 * fill 1st mbuf at least 10byte 1513 * 1514 * align 8 * * * * * 1515 * +0123456789abcdef0123456789abcdef0 1516 * FROM m->m_data[________abcde___________________] 1517 * m->m_data[__fg____________________________] 1518 * m->m_data[_________________hi_____________] 1519 * m->m_data[__________jk____________________] 1520 * m->m_data[____l___________________________] 1521 * 1522 * +0123456789abcdef0123456789abcdef0 1523 * TO m->m_data[________abcdefghij______________] 1524 * m->m_data[________________________________] 1525 * m->m_data[________________________________] 1526 * m->m_data[___________k____________________] 1527 * m->m_data[____l___________________________] 1528 */ 1529 if (mt == NULL) { 1530 mt = m; 1531 while (mt->m_len == 0) { 1532 mt = mt->m_next; 1533 if (mt == NULL) { 1534 m_freem(m); 1535 return ENOBUFS; 1536 } 1537 } 1538 1539 /* mt = 1st mbuf, x = 2nd mbuf */ 1540 x = mt->m_next; 1541 while (mt->m_len < MINBUFSIZE) { 1542 if (x == NULL) { 1543 m_freem(m); 1544 return ENOBUFS; 1545 } 1546 1547 alignoff = (uintptr_t)x->m_data & 1548 (ALIGNBYTE - 1); 1549 chiplen = ALIGNBYTE - alignoff; 1550 if (chiplen > x->m_len) { 1551 chiplen = x->m_len; 1552 } else if ((mt->m_len + chiplen) < 1553 MINBUFSIZE) { 1554 /* 1555 * next mbuf should be greater 1556 * than ALIGNBYTE? 1557 */ 1558 if (x->m_len >= (chiplen + 1559 ALIGNBYTE * 2)) 1560 chiplen += ALIGNBYTE; 1561 else 1562 chiplen = x->m_len; 1563 } 1564 1565 if (chiplen && 1566 (M_TRAILINGSPACE(mt) < chiplen)) { 1567 /* 1568 * move data to the begining of 1569 * m_dat[] (aligned) to en- 1570 * large trailingspace 1571 */ 1572 if (mt->m_flags & M_EXT) { 1573 ap = mt->m_ext.ext_buf; 1574 } else if (mt->m_flags & 1575 M_PKTHDR) { 1576 ap = mt->m_pktdat; 1577 } else { 1578 ap = mt->m_dat; 1579 } 1580 ap = ALIGN_PTR(ap, ALIGNBYTE); 1581 memcpy(ap, mt->m_data, mt->m_len); 1582 mt->m_data = ap; 1583 } 1584 1585 if (chiplen && 1586 (M_TRAILINGSPACE(mt) >= chiplen)) { 1587 memcpy(mt->m_data + mt->m_len, 1588 x->m_data, chiplen); 1589 mt->m_len += chiplen; 1590 m_adj(x, chiplen); 1591 } 1592 1593 x = x->m_next; 1594 } 1595 } 1596 1597 } else { 1598 mt = m; 1599 1600 /* 1601 * allocate new mbuf x, and rearrange as below; 1602 * 1603 * align 8 * * * * * 1604 * +0123456789abcdef0123456789abcdef0 1605 * FROM m->m_data[____________abcdefghijklmnopq___] 1606 * 1607 * +0123456789abcdef0123456789abcdef0 1608 * TO x->m_data[________abcdefghijkl____________] 1609 * m->m_data[________________________mnopq___] 1610 * 1611 */ 1612 if (alignoff != 0) { 1613 /* at least ALIGNBYTE */ 1614 chiplen = ALIGNBYTE - alignoff + ALIGNBYTE; 1615 1616 MGET(x, M_DONTWAIT, m->m_type); 1617 if (x == NULL) { 1618 m_freem(m); 1619 return ENOBUFS; 1620 } 1621 MCLAIM(x, m->m_owner); 1622 if (m->m_flags & M_PKTHDR) 1623 M_MOVE_PKTHDR(x, m); 1624 x->m_data = ALIGN_PTR(x->m_data, ALIGNBYTE); 1625 memcpy(mtod(x, void *), mtod(m, void *), 1626 chiplen); 1627 x->m_len = chiplen; 1628 x->m_next = m; 1629 m_adj(m, chiplen); 1630 1631 if (p == NULL) 1632 m0 = x; 1633 else 1634 p->m_next = x; 1635 } 1636 } 1637 p = m; 1638 } 1639 *mp = m0; 1640 1641 return 0; 1642 } 1643 1644 static int 1645 enet_encap_txring(struct enet_softc *sc, struct mbuf **mp) 1646 { 1647 bus_dmamap_t map; 1648 struct mbuf *m; 1649 int csumflags, idx, i, error; 1650 uint32_t flags1, flags2; 1651 1652 idx = sc->sc_tx_prodidx; 1653 map = sc->sc_txsoft[idx].txs_dmamap; 1654 1655 /* align mbuf data for claim of ENET */ 1656 error = enet_encap_mbufalign(mp); 1657 if (error != 0) 1658 return error; 1659 1660 m = *mp; 1661 csumflags = m->m_pkthdr.csum_flags; 1662 1663 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1664 BUS_DMA_NOWAIT); 1665 if (error != 0) { 1666 device_printf(sc->sc_dev, 1667 "Error mapping mbuf into TX chain: error=%d\n", error); 1668 m_freem(m); 1669 return error; 1670 } 1671 1672 if (map->dm_nsegs > sc->sc_tx_free) { 1673 bus_dmamap_unload(sc->sc_dmat, map); 1674 device_printf(sc->sc_dev, 1675 "too many mbuf chain %d\n", map->dm_nsegs); 1676 m_freem(m); 1677 return ENOBUFS; 1678 } 1679 1680 /* fill protocol cksum zero beforehand */ 1681 if (csumflags & (M_CSUM_UDPv4 | M_CSUM_TCPv4 | 1682 M_CSUM_UDPv6 | M_CSUM_TCPv6)) { 1683 struct mbuf *m1; 1684 int ehlen, moff; 1685 uint16_t etype; 1686 1687 m_copydata(m, ETHER_ADDR_LEN * 2, sizeof(etype), &etype); 1688 switch (ntohs(etype)) { 1689 case ETHERTYPE_IP: 1690 case ETHERTYPE_IPV6: 1691 ehlen = ETHER_HDR_LEN; 1692 break; 1693 case ETHERTYPE_VLAN: 1694 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1695 break; 1696 default: 1697 ehlen = 0; 1698 break; 1699 } 1700 1701 if (ehlen) { 1702 m1 = m_getptr(m, ehlen + 1703 M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data) + 1704 M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data), 1705 &moff); 1706 if (m1 != NULL) 1707 *(uint16_t *)(mtod(m1, char *) + moff) = 0; 1708 } 1709 } 1710 1711 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1712 BUS_DMASYNC_PREWRITE); 1713 1714 for (i = 0; i < map->dm_nsegs; i++) { 1715 flags1 = TXFLAGS1_R; 1716 flags2 = 0; 1717 1718 if (i == 0) { 1719 flags1 |= TXFLAGS1_T1; /* mark as first segment */ 1720 sc->sc_txsoft[idx].txs_mbuf = m; 1721 } 1722 1723 /* checksum offloading */ 1724 if (csumflags & (M_CSUM_UDPv4 | M_CSUM_TCPv4 | 1725 M_CSUM_UDPv6 | M_CSUM_TCPv6)) 1726 flags2 |= TXFLAGS2_PINS; 1727 if (csumflags & (M_CSUM_IPv4)) 1728 flags2 |= TXFLAGS2_IINS; 1729 1730 if (i == map->dm_nsegs - 1) { 1731 /* mark last segment */ 1732 flags1 |= TXFLAGS1_L | TXFLAGS1_TC; 1733 flags2 |= TXFLAGS2_INT; 1734 } 1735 if (idx == ENET_TX_RING_CNT - 1) { 1736 /* mark end of ring */ 1737 flags1 |= TXFLAGS1_W; 1738 } 1739 1740 sc->sc_txdesc_ring[idx].tx_databuf = map->dm_segs[i].ds_addr; 1741 sc->sc_txdesc_ring[idx].tx_flags2 = flags2; 1742 sc->sc_txdesc_ring[idx].tx_flags3 = 0; 1743 TXDESC_WRITEOUT(idx); 1744 1745 sc->sc_txdesc_ring[idx].tx_flags1_len = 1746 flags1 | TXFLAGS1_LEN(map->dm_segs[i].ds_len); 1747 TXDESC_WRITEOUT(idx); 1748 1749 idx = ENET_TX_NEXTIDX(idx); 1750 sc->sc_tx_free--; 1751 } 1752 1753 sc->sc_tx_prodidx = idx; 1754 1755 return 0; 1756 } 1757 1758 /* 1759 * device initialize 1760 */ 1761 static int 1762 enet_init_regs(struct enet_softc *sc, int init) 1763 { 1764 struct mii_data *mii; 1765 struct ifmedia_entry *ife; 1766 paddr_t paddr; 1767 uint32_t val; 1768 int fulldup, ecr_speed, rcr_speed, flowctrl; 1769 1770 if (init) { 1771 fulldup = 1; 1772 ecr_speed = ENET_ECR_SPEED; 1773 rcr_speed = 0; 1774 flowctrl = 0; 1775 } else { 1776 mii = &sc->sc_mii; 1777 ife = mii->mii_media.ifm_cur; 1778 1779 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) 1780 fulldup = 1; 1781 else 1782 fulldup = 0; 1783 1784 switch (IFM_SUBTYPE(ife->ifm_media)) { 1785 case IFM_10_T: 1786 ecr_speed = 0; 1787 rcr_speed = ENET_RCR_RMII_10T; 1788 break; 1789 case IFM_100_TX: 1790 ecr_speed = 0; 1791 rcr_speed = 0; 1792 break; 1793 default: 1794 ecr_speed = ENET_ECR_SPEED; 1795 rcr_speed = 0; 1796 break; 1797 } 1798 1799 flowctrl = sc->sc_flowflags & IFM_FLOW; 1800 } 1801 1802 /* reset */ 1803 ENET_REG_WRITE(sc, ENET_ECR, ecr_speed | ENET_ECR_RESET); 1804 1805 /* mask and clear all interrupt */ 1806 ENET_REG_WRITE(sc, ENET_EIMR, 0); 1807 ENET_REG_WRITE(sc, ENET_EIR, 0xffffffff); 1808 1809 /* full duplex */ 1810 ENET_REG_WRITE(sc, ENET_TCR, fulldup ? ENET_TCR_FDEN : 0); 1811 1812 /* clear and enable MIB register */ 1813 ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR); 1814 ENET_REG_WRITE(sc, ENET_MIBC, 0); 1815 1816 /* MII speed setup. MDCclk(=2.5MHz) = ENET_PLL/((val+1)*2) */ 1817 val = ((sc->sc_pllclock) / 500000 - 1) / 10; 1818 ENET_REG_WRITE(sc, ENET_MSCR, val << 1); 1819 1820 /* Opcode/Pause Duration */ 1821 ENET_REG_WRITE(sc, ENET_OPD, 0x00010020); 1822 1823 /* Receive FIFO */ 1824 ENET_REG_WRITE(sc, ENET_RSFL, 16); /* RxFIFO Section Full */ 1825 ENET_REG_WRITE(sc, ENET_RSEM, 0x84); /* RxFIFO Section Empty */ 1826 ENET_REG_WRITE(sc, ENET_RAEM, 8); /* RxFIFO Almost Empty */ 1827 ENET_REG_WRITE(sc, ENET_RAFL, 8); /* RxFIFO Almost Full */ 1828 1829 /* Transmit FIFO */ 1830 ENET_REG_WRITE(sc, ENET_TFWR, ENET_TFWR_STRFWD | 1831 ENET_TFWR_FIFO(128)); /* TxFIFO Watermark */ 1832 ENET_REG_WRITE(sc, ENET_TSEM, 0); /* TxFIFO Section Empty */ 1833 ENET_REG_WRITE(sc, ENET_TAEM, 256); /* TxFIFO Almost Empty */ 1834 ENET_REG_WRITE(sc, ENET_TAFL, 8); /* TxFIFO Almost Full */ 1835 ENET_REG_WRITE(sc, ENET_TIPG, 12); /* Tx Inter-Packet Gap */ 1836 1837 /* hardware checksum is default off (override in TX descripter) */ 1838 ENET_REG_WRITE(sc, ENET_TACC, 0); 1839 1840 /* 1841 * align ethernet payload on 32bit, discard frames with MAC layer error, 1842 * and don't discard checksum error 1843 */ 1844 ENET_REG_WRITE(sc, ENET_RACC, ENET_RACC_SHIFT16 | ENET_RACC_LINEDIS); 1845 1846 /* maximum frame size */ 1847 val = ENET_DEFAULT_PKT_LEN; 1848 ENET_REG_WRITE(sc, ENET_FTRL, val); /* Frame Truncation Length */ 1849 ENET_REG_WRITE(sc, ENET_RCR, 1850 ENET_RCR_PADEN | /* RX frame padding remove */ 1851 ENET_RCR_RGMII_EN | /* use RGMII */ 1852 (flowctrl ? ENET_RCR_FCE : 0) | /* flow control enable */ 1853 rcr_speed | 1854 (fulldup ? 0 : ENET_RCR_DRT) | 1855 ENET_RCR_MAX_FL(val)); 1856 1857 /* Maximum Receive BufSize per one descriptor */ 1858 ENET_REG_WRITE(sc, ENET_MRBR, RXDESC_MAXBUFSIZE); 1859 1860 1861 /* TX/RX Descriptor Physical Address */ 1862 paddr = sc->sc_txdesc_dmamap->dm_segs[0].ds_addr; 1863 ENET_REG_WRITE(sc, ENET_TDSR, paddr); 1864 paddr = sc->sc_rxdesc_dmamap->dm_segs[0].ds_addr; 1865 ENET_REG_WRITE(sc, ENET_RDSR, paddr); 1866 /* sync cache */ 1867 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, 0, 1868 sc->sc_txdesc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1869 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, 0, 1870 sc->sc_rxdesc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1871 1872 /* enable interrupts */ 1873 val = ENET_EIMR|ENET_EIR_TXF|ENET_EIR_RXF|ENET_EIR_EBERR; 1874 if (sc->sc_imxtype == 7) 1875 val |= ENET_EIR_TXF2|ENET_EIR_RXF2|ENET_EIR_TXF1|ENET_EIR_RXF1; 1876 ENET_REG_WRITE(sc, ENET_EIMR, val); 1877 1878 /* enable ether */ 1879 ENET_REG_WRITE(sc, ENET_ECR, 1880 #if _BYTE_ORDER == _LITTLE_ENDIAN 1881 ENET_ECR_DBSWP | 1882 #endif 1883 ENET_ECR_SPEED | /* default 1000Mbps mode */ 1884 ENET_ECR_EN1588 | /* use enhanced TX/RX descriptor */ 1885 ENET_ECR_ETHEREN); /* Ethernet Enable */ 1886 1887 return 0; 1888 } 1889 1890 static int 1891 enet_alloc_dma(struct enet_softc *sc, size_t size, void **addrp, 1892 bus_dmamap_t *mapp) 1893 { 1894 bus_dma_segment_t seglist[1]; 1895 int nsegs, error; 1896 1897 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seglist, 1898 1, &nsegs, M_NOWAIT)) != 0) { 1899 device_printf(sc->sc_dev, 1900 "unable to allocate DMA buffer, error=%d\n", error); 1901 goto fail_alloc; 1902 } 1903 1904 if ((error = bus_dmamem_map(sc->sc_dmat, seglist, 1, size, addrp, 1905 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1906 device_printf(sc->sc_dev, 1907 "unable to map DMA buffer, error=%d\n", 1908 error); 1909 goto fail_map; 1910 } 1911 1912 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1913 BUS_DMA_NOWAIT, mapp)) != 0) { 1914 device_printf(sc->sc_dev, 1915 "unable to create DMA map, error=%d\n", error); 1916 goto fail_create; 1917 } 1918 1919 if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL, 1920 BUS_DMA_NOWAIT)) != 0) { 1921 aprint_error_dev(sc->sc_dev, 1922 "unable to load DMA map, error=%d\n", error); 1923 goto fail_load; 1924 } 1925 1926 return 0; 1927 1928 fail_load: 1929 bus_dmamap_destroy(sc->sc_dmat, *mapp); 1930 fail_create: 1931 bus_dmamem_unmap(sc->sc_dmat, *addrp, size); 1932 fail_map: 1933 bus_dmamem_free(sc->sc_dmat, seglist, 1); 1934 fail_alloc: 1935 return error; 1936 } 1937