1 /* $NetBSD: if_enet.c,v 1.29 2019/11/29 17:20:30 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * i.MX6,7 10/100/1000-Mbps ethernet MAC (ENET) 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.29 2019/11/29 17:20:30 ryo Exp $"); 35 36 #include "vlan.h" 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/mbuf.h> 41 #include <sys/device.h> 42 #include <sys/sockio.h> 43 #include <sys/kernel.h> 44 #include <sys/rndsource.h> 45 46 #include <lib/libkern/libkern.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_ether.h> 52 #include <net/bpf.h> 53 #include <net/if_vlanvar.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/ip.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <arm/imx/if_enetreg.h> 63 #include <arm/imx/if_enetvar.h> 64 65 #undef DEBUG_ENET 66 #undef ENET_EVENT_COUNTER 67 68 #define ENET_TICK hz 69 70 #ifdef DEBUG_ENET 71 int enet_debug = 0; 72 # define DEVICE_DPRINTF(args...) \ 73 do { if (enet_debug) device_printf(sc->sc_dev, args); } while (0) 74 #else 75 # define DEVICE_DPRINTF(args...) 76 #endif 77 78 79 #define RXDESC_MAXBUFSIZE 0x07f0 80 /* ENET does not work greather than 0x0800... */ 81 82 #undef ENET_SUPPORT_JUMBO /* JUMBO FRAME SUPPORT is unstable */ 83 #ifdef ENET_SUPPORT_JUMBO 84 # define ENET_MAX_PKT_LEN 4034 /* MAX FIFO LEN */ 85 #else 86 # define ENET_MAX_PKT_LEN 1522 87 #endif 88 #define ENET_DEFAULT_PKT_LEN 1522 /* including VLAN tag */ 89 #define MTU2FRAMESIZE(n) \ 90 ((n) + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN) 91 92 93 #define ENET_MAX_PKT_NSEGS 64 94 95 #define ENET_TX_NEXTIDX(idx) \ 96 (((idx) >= (ENET_TX_RING_CNT - 1)) ? 0 : ((idx) + 1)) 97 #define ENET_RX_NEXTIDX(idx) \ 98 (((idx) >= (ENET_RX_RING_CNT - 1)) ? 0 : ((idx) + 1)) 99 100 #define TXDESC_WRITEOUT(idx) \ 101 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \ 102 sizeof(struct enet_txdesc) * (idx), \ 103 sizeof(struct enet_txdesc), \ 104 BUS_DMASYNC_PREWRITE) 105 106 #define TXDESC_READIN(idx) \ 107 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \ 108 sizeof(struct enet_txdesc) * (idx), \ 109 sizeof(struct enet_txdesc), \ 110 BUS_DMASYNC_PREREAD) 111 112 #define RXDESC_WRITEOUT(idx) \ 113 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, \ 114 sizeof(struct enet_rxdesc) * (idx), \ 115 sizeof(struct enet_rxdesc), \ 116 BUS_DMASYNC_PREWRITE) 117 118 #define RXDESC_READIN(idx) \ 119 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, \ 120 sizeof(struct enet_rxdesc) * (idx), \ 121 sizeof(struct enet_rxdesc), \ 122 BUS_DMASYNC_PREREAD) 123 124 #define ENET_REG_READ(sc, reg) \ 125 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg) 126 127 #define ENET_REG_WRITE(sc, reg, value) \ 128 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, value) 129 130 #ifdef ENET_EVENT_COUNTER 131 static void enet_attach_evcnt(struct enet_softc *); 132 static void enet_update_evcnt(struct enet_softc *); 133 #endif 134 135 static void enet_tick(void *); 136 static int enet_tx_intr(void *); 137 static int enet_rx_intr(void *); 138 static void enet_rx_csum(struct enet_softc *, struct ifnet *, struct mbuf *, 139 int); 140 141 static void enet_start(struct ifnet *); 142 static int enet_ifflags_cb(struct ethercom *); 143 static int enet_ioctl(struct ifnet *, u_long, void *); 144 static int enet_init(struct ifnet *); 145 static void enet_stop(struct ifnet *, int); 146 static void enet_watchdog(struct ifnet *); 147 static void enet_mediastatus(struct ifnet *, struct ifmediareq *); 148 149 static int enet_miibus_readreg(device_t, int, int, uint16_t *); 150 static int enet_miibus_writereg(device_t, int, int, uint16_t); 151 static void enet_miibus_statchg(struct ifnet *); 152 153 static void enet_gethwaddr(struct enet_softc *, uint8_t *); 154 static void enet_sethwaddr(struct enet_softc *, uint8_t *); 155 static void enet_setmulti(struct enet_softc *); 156 static int enet_encap_mbufalign(struct mbuf **); 157 static int enet_encap_txring(struct enet_softc *, struct mbuf **); 158 static int enet_init_regs(struct enet_softc *, int); 159 static int enet_alloc_ring(struct enet_softc *); 160 static void enet_init_txring(struct enet_softc *); 161 static int enet_init_rxring(struct enet_softc *); 162 static void enet_reset_rxdesc(struct enet_softc *, int); 163 static int enet_alloc_rxbuf(struct enet_softc *, int); 164 static void enet_drain_txbuf(struct enet_softc *); 165 static void enet_drain_rxbuf(struct enet_softc *); 166 static int enet_alloc_dma(struct enet_softc *, size_t, void **, 167 bus_dmamap_t *); 168 169 int 170 enet_attach_common(device_t self) 171 { 172 struct enet_softc *sc = device_private(self); 173 struct ifnet *ifp; 174 struct mii_data * const mii = &sc->sc_mii; 175 176 /* allocate dma buffer */ 177 if (enet_alloc_ring(sc)) 178 return -1; 179 180 #define IS_ENADDR_ZERO(enaddr) \ 181 ((enaddr[0] | enaddr[1] | enaddr[2] | \ 182 enaddr[3] | enaddr[4] | enaddr[5]) == 0) 183 184 if (IS_ENADDR_ZERO(sc->sc_enaddr)) { 185 /* by any chance, mac-address is already set by bootloader? */ 186 enet_gethwaddr(sc, sc->sc_enaddr); 187 if (IS_ENADDR_ZERO(sc->sc_enaddr)) { 188 /* give up. set randomly */ 189 uint32_t eaddr = random(); 190 /* not multicast */ 191 sc->sc_enaddr[0] = (eaddr >> 24) & 0xfc; 192 sc->sc_enaddr[1] = eaddr >> 16; 193 sc->sc_enaddr[2] = eaddr >> 8; 194 sc->sc_enaddr[3] = eaddr; 195 eaddr = random(); 196 sc->sc_enaddr[4] = eaddr >> 8; 197 sc->sc_enaddr[5] = eaddr; 198 199 aprint_error_dev(self, 200 "cannot get mac address. set randomly\n"); 201 } 202 } 203 enet_sethwaddr(sc, sc->sc_enaddr); 204 205 aprint_normal_dev(self, "Ethernet address %s\n", 206 ether_sprintf(sc->sc_enaddr)); 207 208 enet_init_regs(sc, 1); 209 210 /* callout will be scheduled from enet_init() */ 211 callout_init(&sc->sc_tick_ch, 0); 212 callout_setfunc(&sc->sc_tick_ch, enet_tick, sc); 213 214 /* setup ifp */ 215 ifp = &sc->sc_ethercom.ec_if; 216 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 217 ifp->if_softc = sc; 218 ifp->if_mtu = ETHERMTU; 219 ifp->if_baudrate = IF_Gbps(1); 220 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 221 ifp->if_ioctl = enet_ioctl; 222 ifp->if_start = enet_start; 223 ifp->if_init = enet_init; 224 ifp->if_stop = enet_stop; 225 ifp->if_watchdog = enet_watchdog; 226 227 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 228 #ifdef ENET_SUPPORT_JUMBO 229 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 230 #endif 231 232 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 233 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 234 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 235 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx | 236 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 237 238 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(ENET_TX_RING_CNT, IFQ_MAXLEN)); 239 IFQ_SET_READY(&ifp->if_snd); 240 241 /* setup MII */ 242 sc->sc_ethercom.ec_mii = mii; 243 mii->mii_ifp = ifp; 244 mii->mii_readreg = enet_miibus_readreg; 245 mii->mii_writereg = enet_miibus_writereg; 246 mii->mii_statchg = enet_miibus_statchg; 247 ifmedia_init(&mii->mii_media, 0, ether_mediachange, enet_mediastatus); 248 249 /* try to attach PHY */ 250 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 251 if (LIST_FIRST(&mii->mii_phys) == NULL) { 252 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 253 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 254 } else { 255 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 256 } 257 258 if_attach(ifp); 259 ether_ifattach(ifp, sc->sc_enaddr); 260 ether_set_ifflags_cb(&sc->sc_ethercom, enet_ifflags_cb); 261 262 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 263 RND_TYPE_NET, RND_FLAG_DEFAULT); 264 265 #ifdef ENET_EVENT_COUNTER 266 enet_attach_evcnt(sc); 267 #endif 268 269 sc->sc_stopping = false; 270 271 return 0; 272 } 273 274 #ifdef ENET_EVENT_COUNTER 275 static void 276 enet_attach_evcnt(struct enet_softc *sc) 277 { 278 const char *xname; 279 280 xname = device_xname(sc->sc_dev); 281 282 #define ENET_EVCNT_ATTACH(name) \ 283 evcnt_attach_dynamic(&sc->sc_ev_ ## name, EVCNT_TYPE_MISC, \ 284 NULL, xname, #name); 285 286 ENET_EVCNT_ATTACH(t_drop); 287 ENET_EVCNT_ATTACH(t_packets); 288 ENET_EVCNT_ATTACH(t_bc_pkt); 289 ENET_EVCNT_ATTACH(t_mc_pkt); 290 ENET_EVCNT_ATTACH(t_crc_align); 291 ENET_EVCNT_ATTACH(t_undersize); 292 ENET_EVCNT_ATTACH(t_oversize); 293 ENET_EVCNT_ATTACH(t_frag); 294 ENET_EVCNT_ATTACH(t_jab); 295 ENET_EVCNT_ATTACH(t_col); 296 ENET_EVCNT_ATTACH(t_p64); 297 ENET_EVCNT_ATTACH(t_p65to127n); 298 ENET_EVCNT_ATTACH(t_p128to255n); 299 ENET_EVCNT_ATTACH(t_p256to511); 300 ENET_EVCNT_ATTACH(t_p512to1023); 301 ENET_EVCNT_ATTACH(t_p1024to2047); 302 ENET_EVCNT_ATTACH(t_p_gte2048); 303 ENET_EVCNT_ATTACH(t_octets); 304 ENET_EVCNT_ATTACH(r_packets); 305 ENET_EVCNT_ATTACH(r_bc_pkt); 306 ENET_EVCNT_ATTACH(r_mc_pkt); 307 ENET_EVCNT_ATTACH(r_crc_align); 308 ENET_EVCNT_ATTACH(r_undersize); 309 ENET_EVCNT_ATTACH(r_oversize); 310 ENET_EVCNT_ATTACH(r_frag); 311 ENET_EVCNT_ATTACH(r_jab); 312 ENET_EVCNT_ATTACH(r_p64); 313 ENET_EVCNT_ATTACH(r_p65to127); 314 ENET_EVCNT_ATTACH(r_p128to255); 315 ENET_EVCNT_ATTACH(r_p256to511); 316 ENET_EVCNT_ATTACH(r_p512to1023); 317 ENET_EVCNT_ATTACH(r_p1024to2047); 318 ENET_EVCNT_ATTACH(r_p_gte2048); 319 ENET_EVCNT_ATTACH(r_octets); 320 } 321 322 static void 323 enet_update_evcnt(struct enet_softc *sc) 324 { 325 sc->sc_ev_t_drop.ev_count += ENET_REG_READ(sc, ENET_RMON_T_DROP); 326 sc->sc_ev_t_packets.ev_count += ENET_REG_READ(sc, ENET_RMON_T_PACKETS); 327 sc->sc_ev_t_bc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_T_BC_PKT); 328 sc->sc_ev_t_mc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_T_MC_PKT); 329 sc->sc_ev_t_crc_align.ev_count += ENET_REG_READ(sc, ENET_RMON_T_CRC_ALIGN); 330 sc->sc_ev_t_undersize.ev_count += ENET_REG_READ(sc, ENET_RMON_T_UNDERSIZE); 331 sc->sc_ev_t_oversize.ev_count += ENET_REG_READ(sc, ENET_RMON_T_OVERSIZE); 332 sc->sc_ev_t_frag.ev_count += ENET_REG_READ(sc, ENET_RMON_T_FRAG); 333 sc->sc_ev_t_jab.ev_count += ENET_REG_READ(sc, ENET_RMON_T_JAB); 334 sc->sc_ev_t_col.ev_count += ENET_REG_READ(sc, ENET_RMON_T_COL); 335 sc->sc_ev_t_p64.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P64); 336 sc->sc_ev_t_p65to127n.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P65TO127N); 337 sc->sc_ev_t_p128to255n.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P128TO255N); 338 sc->sc_ev_t_p256to511.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P256TO511); 339 sc->sc_ev_t_p512to1023.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P512TO1023); 340 sc->sc_ev_t_p1024to2047.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P1024TO2047); 341 sc->sc_ev_t_p_gte2048.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P_GTE2048); 342 sc->sc_ev_t_octets.ev_count += ENET_REG_READ(sc, ENET_RMON_T_OCTETS); 343 sc->sc_ev_r_packets.ev_count += ENET_REG_READ(sc, ENET_RMON_R_PACKETS); 344 sc->sc_ev_r_bc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_R_BC_PKT); 345 sc->sc_ev_r_mc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_R_MC_PKT); 346 sc->sc_ev_r_crc_align.ev_count += ENET_REG_READ(sc, ENET_RMON_R_CRC_ALIGN); 347 sc->sc_ev_r_undersize.ev_count += ENET_REG_READ(sc, ENET_RMON_R_UNDERSIZE); 348 sc->sc_ev_r_oversize.ev_count += ENET_REG_READ(sc, ENET_RMON_R_OVERSIZE); 349 sc->sc_ev_r_frag.ev_count += ENET_REG_READ(sc, ENET_RMON_R_FRAG); 350 sc->sc_ev_r_jab.ev_count += ENET_REG_READ(sc, ENET_RMON_R_JAB); 351 sc->sc_ev_r_p64.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P64); 352 sc->sc_ev_r_p65to127.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P65TO127); 353 sc->sc_ev_r_p128to255.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P128TO255); 354 sc->sc_ev_r_p256to511.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P256TO511); 355 sc->sc_ev_r_p512to1023.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P512TO1023); 356 sc->sc_ev_r_p1024to2047.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P1024TO2047); 357 sc->sc_ev_r_p_gte2048.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P_GTE2048); 358 sc->sc_ev_r_octets.ev_count += ENET_REG_READ(sc, ENET_RMON_R_OCTETS); 359 } 360 #endif /* ENET_EVENT_COUNTER */ 361 362 static void 363 enet_tick(void *arg) 364 { 365 struct enet_softc *sc; 366 struct mii_data *mii; 367 struct ifnet *ifp; 368 int s; 369 370 sc = arg; 371 mii = &sc->sc_mii; 372 ifp = &sc->sc_ethercom.ec_if; 373 374 s = splnet(); 375 376 if (sc->sc_stopping) 377 goto out; 378 379 #ifdef ENET_EVENT_COUNTER 380 enet_update_evcnt(sc); 381 #endif 382 383 /* update counters */ 384 ifp->if_ierrors += ENET_REG_READ(sc, ENET_RMON_R_UNDERSIZE); 385 ifp->if_ierrors += ENET_REG_READ(sc, ENET_RMON_R_FRAG); 386 ifp->if_ierrors += ENET_REG_READ(sc, ENET_RMON_R_JAB); 387 388 /* clear counters */ 389 ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR); 390 ENET_REG_WRITE(sc, ENET_MIBC, 0); 391 392 mii_tick(mii); 393 out: 394 395 if (!sc->sc_stopping) 396 callout_schedule(&sc->sc_tick_ch, ENET_TICK); 397 398 splx(s); 399 } 400 401 int 402 enet_intr(void *arg) 403 { 404 struct enet_softc *sc; 405 struct ifnet *ifp; 406 uint32_t status; 407 408 sc = arg; 409 status = ENET_REG_READ(sc, ENET_EIR); 410 411 if (sc->sc_imxtype == 7) { 412 if (status & (ENET_EIR_TXF | ENET_EIR_TXF1 | ENET_EIR_TXF2)) 413 enet_tx_intr(arg); 414 if (status & (ENET_EIR_RXF | ENET_EIR_RXF1 | ENET_EIR_RXF2)) 415 enet_rx_intr(arg); 416 } else { 417 if (status & ENET_EIR_TXF) 418 enet_tx_intr(arg); 419 if (status & ENET_EIR_RXF) 420 enet_rx_intr(arg); 421 } 422 423 if (status & ENET_EIR_EBERR) { 424 device_printf(sc->sc_dev, "Ethernet Bus Error\n"); 425 ifp = &sc->sc_ethercom.ec_if; 426 enet_stop(ifp, 1); 427 enet_init(ifp); 428 } else { 429 ENET_REG_WRITE(sc, ENET_EIR, status); 430 } 431 432 rnd_add_uint32(&sc->sc_rnd_source, status); 433 434 return 1; 435 } 436 437 static int 438 enet_tx_intr(void *arg) 439 { 440 struct enet_softc *sc; 441 struct ifnet *ifp; 442 struct enet_txsoft *txs; 443 int idx; 444 445 sc = (struct enet_softc *)arg; 446 ifp = &sc->sc_ethercom.ec_if; 447 448 for (idx = sc->sc_tx_considx; idx != sc->sc_tx_prodidx; 449 idx = ENET_TX_NEXTIDX(idx)) { 450 451 txs = &sc->sc_txsoft[idx]; 452 453 TXDESC_READIN(idx); 454 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_R) { 455 /* This TX Descriptor has not been transmitted yet */ 456 break; 457 } 458 459 /* txsoft is available on first segment (TXFLAGS1_T1) */ 460 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_T1) { 461 bus_dmamap_unload(sc->sc_dmat, 462 txs->txs_dmamap); 463 m_freem(txs->txs_mbuf); 464 ifp->if_opackets++; 465 } 466 467 /* checking error */ 468 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_L) { 469 uint32_t flags2; 470 471 flags2 = sc->sc_txdesc_ring[idx].tx_flags2; 472 473 if (flags2 & (TXFLAGS2_TXE | 474 TXFLAGS2_UE | TXFLAGS2_EE | TXFLAGS2_FE | 475 TXFLAGS2_LCE | TXFLAGS2_OE | TXFLAGS2_TSE)) { 476 #ifdef DEBUG_ENET 477 if (enet_debug) { 478 char flagsbuf[128]; 479 480 snprintb(flagsbuf, sizeof(flagsbuf), 481 "\20" "\20TRANSMIT" "\16UNDERFLOW" 482 "\15COLLISION" "\14FRAME" 483 "\13LATECOLLISION" "\12OVERFLOW", 484 flags2); 485 486 device_printf(sc->sc_dev, 487 "txdesc[%d]: transmit error: " 488 "flags2=%s\n", idx, flagsbuf); 489 } 490 #endif /* DEBUG_ENET */ 491 ifp->if_oerrors++; 492 } 493 } 494 495 sc->sc_tx_free++; 496 } 497 sc->sc_tx_considx = idx; 498 499 if (sc->sc_tx_free > 0) 500 ifp->if_flags &= ~IFF_OACTIVE; 501 502 /* 503 * No more pending TX descriptor, 504 * cancel the watchdog timer. 505 */ 506 if (sc->sc_tx_free == ENET_TX_RING_CNT) 507 ifp->if_timer = 0; 508 509 return 1; 510 } 511 512 static int 513 enet_rx_intr(void *arg) 514 { 515 struct enet_softc *sc; 516 struct ifnet *ifp; 517 struct enet_rxsoft *rxs; 518 int idx, len, amount; 519 uint32_t flags1, flags2; 520 struct mbuf *m, *m0, *mprev; 521 522 sc = arg; 523 ifp = &sc->sc_ethercom.ec_if; 524 525 m0 = mprev = NULL; 526 amount = 0; 527 for (idx = sc->sc_rx_readidx; ; idx = ENET_RX_NEXTIDX(idx)) { 528 529 rxs = &sc->sc_rxsoft[idx]; 530 531 RXDESC_READIN(idx); 532 if (sc->sc_rxdesc_ring[idx].rx_flags1_len & RXFLAGS1_E) { 533 /* This RX Descriptor has not been received yet */ 534 break; 535 } 536 537 /* 538 * build mbuf from RX Descriptor if needed 539 */ 540 m = rxs->rxs_mbuf; 541 rxs->rxs_mbuf = NULL; 542 543 flags1 = sc->sc_rxdesc_ring[idx].rx_flags1_len; 544 len = RXFLAGS1_LEN(flags1); 545 546 #define RACC_SHIFT16 2 547 if (m0 == NULL) { 548 m0 = m; 549 m_adj(m0, RACC_SHIFT16); 550 len -= RACC_SHIFT16; 551 m->m_len = len; 552 amount = len; 553 } else { 554 if (flags1 & RXFLAGS1_L) 555 len = len - amount - RACC_SHIFT16; 556 557 m->m_len = len; 558 amount += len; 559 if (m->m_flags & M_PKTHDR) 560 m_remove_pkthdr(m); 561 mprev->m_next = m; 562 } 563 mprev = m; 564 565 flags2 = sc->sc_rxdesc_ring[idx].rx_flags2; 566 567 if (flags1 & RXFLAGS1_L) { 568 /* last buffer */ 569 if ((amount < ETHER_HDR_LEN) || 570 ((flags1 & (RXFLAGS1_LG | RXFLAGS1_NO | 571 RXFLAGS1_CR | RXFLAGS1_OV | RXFLAGS1_TR)) || 572 (flags2 & (RXFLAGS2_ME | RXFLAGS2_PE | 573 RXFLAGS2_CE)))) { 574 575 #ifdef DEBUG_ENET 576 if (enet_debug) { 577 char flags1buf[128], flags2buf[128]; 578 snprintb(flags1buf, sizeof(flags1buf), 579 "\20" "\31MISS" "\26LENGTHVIOLATION" 580 "\25NONOCTET" "\23CRC" "\22OVERRUN" 581 "\21TRUNCATED", flags1); 582 snprintb(flags2buf, sizeof(flags2buf), 583 "\20" "\40MAC" "\33PHY" 584 "\32COLLISION", flags2); 585 586 DEVICE_DPRINTF( 587 "rxdesc[%d]: receive error: " 588 "flags1=%s,flags2=%s,len=%d\n", 589 idx, flags1buf, flags2buf, amount); 590 } 591 #endif /* DEBUG_ENET */ 592 ifp->if_ierrors++; 593 m_freem(m0); 594 595 } else { 596 /* packet receive ok */ 597 m_set_rcvif(m0, ifp); 598 m0->m_pkthdr.len = amount; 599 600 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 601 rxs->rxs_dmamap->dm_mapsize, 602 BUS_DMASYNC_PREREAD); 603 604 if (ifp->if_csum_flags_rx & (M_CSUM_IPv4 | 605 M_CSUM_TCPv4 | M_CSUM_UDPv4 | 606 M_CSUM_TCPv6 | M_CSUM_UDPv6)) 607 enet_rx_csum(sc, ifp, m0, idx); 608 609 if_percpuq_enqueue(ifp->if_percpuq, m0); 610 } 611 612 m0 = NULL; 613 mprev = NULL; 614 amount = 0; 615 616 } else { 617 /* continued from previous buffer */ 618 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 619 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 620 } 621 622 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 623 if (enet_alloc_rxbuf(sc, idx) != 0) { 624 panic("enet_alloc_rxbuf NULL\n"); 625 } 626 } 627 sc->sc_rx_readidx = idx; 628 629 /* re-enable RX DMA to make sure */ 630 ENET_REG_WRITE(sc, ENET_RDAR, ENET_RDAR_ACTIVE); 631 632 return 1; 633 } 634 635 static void 636 enet_rx_csum(struct enet_softc *sc, struct ifnet *ifp, struct mbuf *m, int idx) 637 { 638 uint32_t flags2; 639 uint8_t proto; 640 641 flags2 = sc->sc_rxdesc_ring[idx].rx_flags2; 642 643 if (flags2 & RXFLAGS2_IPV6) { 644 proto = sc->sc_rxdesc_ring[idx].rx_proto; 645 646 /* RXFLAGS2_PCR is valid when IPv6 and TCP/UDP */ 647 if ((proto == IPPROTO_TCP) && 648 (ifp->if_csum_flags_rx & M_CSUM_TCPv6)) 649 m->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 650 else if ((proto == IPPROTO_UDP) && 651 (ifp->if_csum_flags_rx & M_CSUM_UDPv6)) 652 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 653 else 654 return; 655 656 /* IPv6 protocol checksum error */ 657 if (flags2 & RXFLAGS2_PCR) 658 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 659 660 } else { 661 struct ether_header *eh; 662 uint8_t *ip; 663 664 eh = mtod(m, struct ether_header *); 665 666 /* XXX: is an IPv4? */ 667 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 668 return; 669 ip = (uint8_t *)(eh + 1); 670 if ((ip[0] & 0xf0) == 0x40) 671 return; 672 673 proto = sc->sc_rxdesc_ring[idx].rx_proto; 674 if (flags2 & RXFLAGS2_ICE) { 675 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 676 m->m_pkthdr.csum_flags |= 677 M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 678 } 679 } else { 680 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 681 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 682 } 683 684 /* 685 * PCR is valid when 686 * ICE == 0 and FRAG == 0 687 */ 688 if (flags2 & RXFLAGS2_FRAG) 689 return; 690 691 /* 692 * PCR is valid when proto is TCP or UDP 693 */ 694 if ((proto == IPPROTO_TCP) && 695 (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 696 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 697 else if ((proto == IPPROTO_UDP) && 698 (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 699 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 700 else 701 return; 702 703 /* IPv4 protocol cksum error */ 704 if (flags2 & RXFLAGS2_PCR) 705 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 706 } 707 } 708 } 709 710 static void 711 enet_setmulti(struct enet_softc *sc) 712 { 713 struct ethercom *ec = &sc->sc_ethercom; 714 struct ifnet *ifp = &ec->ec_if; 715 struct ether_multi *enm; 716 struct ether_multistep step; 717 uint32_t crc, hashidx; 718 uint32_t gaddr[2]; 719 720 if (ifp->if_flags & IFF_PROMISC) { 721 /* receive all unicast packet */ 722 ENET_REG_WRITE(sc, ENET_IAUR, 0xffffffff); 723 ENET_REG_WRITE(sc, ENET_IALR, 0xffffffff); 724 /* receive all multicast packet */ 725 gaddr[0] = gaddr[1] = 0xffffffff; 726 } else { 727 gaddr[0] = gaddr[1] = 0; 728 729 ETHER_LOCK(ec); 730 ETHER_FIRST_MULTI(step, ec, enm); 731 while (enm != NULL) { 732 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 733 ETHER_ADDR_LEN)) { 734 /* 735 * if specified by range, give up setting hash, 736 * and fallback to allmulti. 737 */ 738 gaddr[0] = gaddr[1] = 0xffffffff; 739 break; 740 } 741 742 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 743 hashidx = __SHIFTOUT(crc, __BITS(30,26)); 744 gaddr[__SHIFTOUT(crc, __BIT(31))] |= __BIT(hashidx); 745 746 ETHER_NEXT_MULTI(step, enm); 747 } 748 ETHER_UNLOCK(ec); 749 750 /* dont't receive any unicast packet (except own address) */ 751 ENET_REG_WRITE(sc, ENET_IAUR, 0); 752 ENET_REG_WRITE(sc, ENET_IALR, 0); 753 } 754 755 if (gaddr[0] == 0xffffffff && gaddr[1] == 0xffffffff) 756 ifp->if_flags |= IFF_ALLMULTI; 757 else 758 ifp->if_flags &= ~IFF_ALLMULTI; 759 760 /* receive multicast packets according to multicast filter */ 761 ENET_REG_WRITE(sc, ENET_GAUR, gaddr[1]); 762 ENET_REG_WRITE(sc, ENET_GALR, gaddr[0]); 763 764 } 765 766 static void 767 enet_gethwaddr(struct enet_softc *sc, uint8_t *hwaddr) 768 { 769 uint32_t paddr; 770 771 paddr = ENET_REG_READ(sc, ENET_PALR); 772 hwaddr[0] = paddr >> 24; 773 hwaddr[1] = paddr >> 16; 774 hwaddr[2] = paddr >> 8; 775 hwaddr[3] = paddr; 776 777 paddr = ENET_REG_READ(sc, ENET_PAUR); 778 hwaddr[4] = paddr >> 24; 779 hwaddr[5] = paddr >> 16; 780 } 781 782 static void 783 enet_sethwaddr(struct enet_softc *sc, uint8_t *hwaddr) 784 { 785 uint32_t paddr; 786 787 paddr = (hwaddr[0] << 24) | (hwaddr[1] << 16) | (hwaddr[2] << 8) | 788 hwaddr[3]; 789 ENET_REG_WRITE(sc, ENET_PALR, paddr); 790 paddr = (hwaddr[4] << 24) | (hwaddr[5] << 16); 791 ENET_REG_WRITE(sc, ENET_PAUR, paddr); 792 } 793 794 /* 795 * ifnet interfaces 796 */ 797 static int 798 enet_init(struct ifnet *ifp) 799 { 800 struct enet_softc *sc; 801 int s, error; 802 803 sc = ifp->if_softc; 804 805 s = splnet(); 806 807 enet_init_regs(sc, 0); 808 enet_init_txring(sc); 809 error = enet_init_rxring(sc); 810 if (error != 0) { 811 enet_drain_rxbuf(sc); 812 device_printf(sc->sc_dev, "Cannot allocate mbuf cluster\n"); 813 goto init_failure; 814 } 815 816 /* reload mac address */ 817 memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 818 enet_sethwaddr(sc, sc->sc_enaddr); 819 820 /* program multicast address */ 821 enet_setmulti(sc); 822 823 /* update if_flags */ 824 ifp->if_flags |= IFF_RUNNING; 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 /* update local copy of if_flags */ 828 sc->sc_if_flags = ifp->if_flags; 829 830 /* mii */ 831 mii_mediachg(&sc->sc_mii); 832 833 /* enable RX DMA */ 834 ENET_REG_WRITE(sc, ENET_RDAR, ENET_RDAR_ACTIVE); 835 836 sc->sc_stopping = false; 837 callout_schedule(&sc->sc_tick_ch, ENET_TICK); 838 839 init_failure: 840 splx(s); 841 842 return error; 843 } 844 845 static void 846 enet_start(struct ifnet *ifp) 847 { 848 struct enet_softc *sc; 849 struct mbuf *m; 850 int npkt; 851 852 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 853 return; 854 855 sc = ifp->if_softc; 856 for (npkt = 0; ; npkt++) { 857 IFQ_POLL(&ifp->if_snd, m); 858 if (m == NULL) 859 break; 860 861 if (sc->sc_tx_free <= 0) { 862 /* no tx descriptor now... */ 863 ifp->if_flags |= IFF_OACTIVE; 864 DEVICE_DPRINTF("TX descriptor is full\n"); 865 break; 866 } 867 868 IFQ_DEQUEUE(&ifp->if_snd, m); 869 870 if (enet_encap_txring(sc, &m) != 0) { 871 /* too many mbuf chains? */ 872 ifp->if_flags |= IFF_OACTIVE; 873 DEVICE_DPRINTF( 874 "TX descriptor is full. dropping packet\n"); 875 m_freem(m); 876 ifp->if_oerrors++; 877 break; 878 } 879 880 /* Pass the packet to any BPF listeners */ 881 bpf_mtap(ifp, m, BPF_D_OUT); 882 } 883 884 if (npkt) { 885 /* enable TX DMA */ 886 ENET_REG_WRITE(sc, ENET_TDAR, ENET_TDAR_ACTIVE); 887 888 ifp->if_timer = 5; 889 } 890 } 891 892 static void 893 enet_stop(struct ifnet *ifp, int disable) 894 { 895 struct enet_softc *sc; 896 int s; 897 uint32_t v; 898 899 sc = ifp->if_softc; 900 901 s = splnet(); 902 903 sc->sc_stopping = true; 904 callout_stop(&sc->sc_tick_ch); 905 906 /* clear ENET_ECR[ETHEREN] to abort receive and transmit */ 907 v = ENET_REG_READ(sc, ENET_ECR); 908 ENET_REG_WRITE(sc, ENET_ECR, v & ~ENET_ECR_ETHEREN); 909 910 /* Mark the interface as down and cancel the watchdog timer. */ 911 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 912 ifp->if_timer = 0; 913 914 if (disable) { 915 enet_drain_txbuf(sc); 916 enet_drain_rxbuf(sc); 917 } 918 919 splx(s); 920 } 921 922 static void 923 enet_watchdog(struct ifnet *ifp) 924 { 925 struct enet_softc *sc; 926 int s; 927 928 sc = ifp->if_softc; 929 s = splnet(); 930 931 device_printf(sc->sc_dev, "watchdog timeout\n"); 932 ifp->if_oerrors++; 933 934 /* salvage packets left in descriptors */ 935 enet_tx_intr(sc); 936 enet_rx_intr(sc); 937 938 /* reset */ 939 enet_stop(ifp, 1); 940 enet_init(ifp); 941 942 splx(s); 943 } 944 945 static void 946 enet_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 947 { 948 struct enet_softc *sc = ifp->if_softc; 949 950 ether_mediastatus(ifp, ifmr); 951 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 952 | sc->sc_flowflags; 953 } 954 955 static int 956 enet_ifflags_cb(struct ethercom *ec) 957 { 958 struct ifnet *ifp = &ec->ec_if; 959 struct enet_softc *sc = ifp->if_softc; 960 u_short change = ifp->if_flags ^ sc->sc_if_flags; 961 962 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 963 return ENETRESET; 964 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 965 return 0; 966 967 enet_setmulti(sc); 968 969 sc->sc_if_flags = ifp->if_flags; 970 return 0; 971 } 972 973 static int 974 enet_ioctl(struct ifnet *ifp, u_long command, void *data) 975 { 976 struct enet_softc *sc; 977 struct ifreq *ifr; 978 int s, error; 979 uint32_t v; 980 981 sc = ifp->if_softc; 982 ifr = data; 983 984 error = 0; 985 986 s = splnet(); 987 988 switch (command) { 989 case SIOCSIFMTU: 990 if (MTU2FRAMESIZE(ifr->ifr_mtu) > ENET_MAX_PKT_LEN) { 991 error = EINVAL; 992 } else { 993 ifp->if_mtu = ifr->ifr_mtu; 994 995 /* set maximum frame length */ 996 v = MTU2FRAMESIZE(ifr->ifr_mtu); 997 ENET_REG_WRITE(sc, ENET_FTRL, v); 998 v = ENET_REG_READ(sc, ENET_RCR); 999 v &= ~ENET_RCR_MAX_FL(0x3fff); 1000 v |= ENET_RCR_MAX_FL(ifp->if_mtu + ETHER_HDR_LEN + 1001 ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 1002 ENET_REG_WRITE(sc, ENET_RCR, v); 1003 } 1004 break; 1005 case SIOCSIFMEDIA: 1006 /* Flow control requires full-duplex mode. */ 1007 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1008 (ifr->ifr_media & IFM_FDX) == 0) 1009 ifr->ifr_media &= ~IFM_ETH_FMASK; 1010 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1011 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1012 /* We can do both TXPAUSE and RXPAUSE. */ 1013 ifr->ifr_media |= 1014 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1015 } 1016 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1017 } 1018 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1019 break; 1020 default: 1021 error = ether_ioctl(ifp, command, data); 1022 if (error != ENETRESET) 1023 break; 1024 1025 /* post-process */ 1026 error = 0; 1027 switch (command) { 1028 case SIOCSIFCAP: 1029 error = (*ifp->if_init)(ifp); 1030 break; 1031 case SIOCADDMULTI: 1032 case SIOCDELMULTI: 1033 if (ifp->if_flags & IFF_RUNNING) 1034 enet_setmulti(sc); 1035 break; 1036 } 1037 break; 1038 } 1039 1040 splx(s); 1041 1042 return error; 1043 } 1044 1045 /* 1046 * for MII 1047 */ 1048 static int 1049 enet_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1050 { 1051 struct enet_softc *sc; 1052 int timeout; 1053 uint32_t status; 1054 1055 sc = device_private(dev); 1056 1057 /* clear MII update */ 1058 ENET_REG_WRITE(sc, ENET_EIR, ENET_EIR_MII); 1059 1060 /* read command */ 1061 ENET_REG_WRITE(sc, ENET_MMFR, 1062 ENET_MMFR_ST | ENET_MMFR_OP_READ | ENET_MMFR_TA | 1063 ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy)); 1064 1065 /* check MII update */ 1066 for (timeout = 5000; timeout > 0; --timeout) { 1067 status = ENET_REG_READ(sc, ENET_EIR); 1068 if (status & ENET_EIR_MII) 1069 break; 1070 } 1071 if (timeout <= 0) { 1072 DEVICE_DPRINTF("MII read timeout: reg=0x%02x\n", 1073 reg); 1074 return ETIMEDOUT; 1075 } else 1076 *val = ENET_REG_READ(sc, ENET_MMFR) & ENET_MMFR_DATAMASK; 1077 1078 return 0; 1079 } 1080 1081 static int 1082 enet_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1083 { 1084 struct enet_softc *sc; 1085 int timeout; 1086 1087 sc = device_private(dev); 1088 1089 /* clear MII update */ 1090 ENET_REG_WRITE(sc, ENET_EIR, ENET_EIR_MII); 1091 1092 /* write command */ 1093 ENET_REG_WRITE(sc, ENET_MMFR, 1094 ENET_MMFR_ST | ENET_MMFR_OP_WRITE | ENET_MMFR_TA | 1095 ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy) | 1096 (ENET_MMFR_DATAMASK & val)); 1097 1098 /* check MII update */ 1099 for (timeout = 5000; timeout > 0; --timeout) { 1100 if (ENET_REG_READ(sc, ENET_EIR) & ENET_EIR_MII) 1101 break; 1102 } 1103 if (timeout <= 0) { 1104 DEVICE_DPRINTF("MII write timeout: reg=0x%02x\n", reg); 1105 return ETIMEDOUT; 1106 } 1107 1108 return 0; 1109 } 1110 1111 static void 1112 enet_miibus_statchg(struct ifnet *ifp) 1113 { 1114 struct enet_softc *sc; 1115 struct mii_data *mii; 1116 struct ifmedia_entry *ife; 1117 uint32_t ecr, ecr0; 1118 uint32_t rcr, rcr0; 1119 uint32_t tcr, tcr0; 1120 1121 sc = ifp->if_softc; 1122 mii = &sc->sc_mii; 1123 ife = mii->mii_media.ifm_cur; 1124 1125 /* get current status */ 1126 ecr0 = ecr = ENET_REG_READ(sc, ENET_ECR) & ~ENET_ECR_RESET; 1127 rcr0 = rcr = ENET_REG_READ(sc, ENET_RCR); 1128 tcr0 = tcr = ENET_REG_READ(sc, ENET_TCR); 1129 1130 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1131 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 1132 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1133 mii->mii_media_active &= ~IFM_ETH_FMASK; 1134 } 1135 1136 if ((ife->ifm_media & IFM_FDX) != 0) { 1137 tcr |= ENET_TCR_FDEN; /* full duplex */ 1138 rcr &= ~ENET_RCR_DRT;; /* enable receive on transmit */ 1139 } else { 1140 tcr &= ~ENET_TCR_FDEN; /* half duplex */ 1141 rcr |= ENET_RCR_DRT; /* disable receive on transmit */ 1142 } 1143 1144 if ((tcr ^ tcr0) & ENET_TCR_FDEN) { 1145 /* 1146 * need to reset because 1147 * FDEN can change when ECR[ETHEREN] is 0 1148 */ 1149 enet_init_regs(sc, 0); 1150 return; 1151 } 1152 1153 switch (IFM_SUBTYPE(ife->ifm_media)) { 1154 case IFM_AUTO: 1155 case IFM_1000_T: 1156 ecr |= ENET_ECR_SPEED; /* 1000Mbps mode */ 1157 rcr &= ~ENET_RCR_RMII_10T; 1158 break; 1159 case IFM_100_TX: 1160 ecr &= ~ENET_ECR_SPEED; /* 100Mbps mode */ 1161 rcr &= ~ENET_RCR_RMII_10T; /* 100Mbps mode */ 1162 break; 1163 case IFM_10_T: 1164 ecr &= ~ENET_ECR_SPEED; /* 10Mbps mode */ 1165 rcr |= ENET_RCR_RMII_10T; /* 10Mbps mode */ 1166 break; 1167 default: 1168 ecr = ecr0; 1169 rcr = rcr0; 1170 tcr = tcr0; 1171 break; 1172 } 1173 1174 if (sc->sc_rgmii == 0) 1175 ecr &= ~ENET_ECR_SPEED; 1176 1177 if (sc->sc_flowflags & IFM_FLOW) 1178 rcr |= ENET_RCR_FCE; 1179 else 1180 rcr &= ~ENET_RCR_FCE; 1181 1182 /* update registers if need change */ 1183 if (ecr != ecr0) 1184 ENET_REG_WRITE(sc, ENET_ECR, ecr); 1185 if (rcr != rcr0) 1186 ENET_REG_WRITE(sc, ENET_RCR, rcr); 1187 if (tcr != tcr0) 1188 ENET_REG_WRITE(sc, ENET_TCR, tcr); 1189 } 1190 1191 /* 1192 * handling descriptors 1193 */ 1194 static void 1195 enet_init_txring(struct enet_softc *sc) 1196 { 1197 int i; 1198 1199 /* build TX ring */ 1200 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1201 sc->sc_txdesc_ring[i].tx_flags1_len = 1202 ((i == (ENET_TX_RING_CNT - 1)) ? TXFLAGS1_W : 0); 1203 sc->sc_txdesc_ring[i].tx_databuf = 0; 1204 sc->sc_txdesc_ring[i].tx_flags2 = TXFLAGS2_INT; 1205 sc->sc_txdesc_ring[i].tx__reserved1 = 0; 1206 sc->sc_txdesc_ring[i].tx_flags3 = 0; 1207 sc->sc_txdesc_ring[i].tx_1588timestamp = 0; 1208 sc->sc_txdesc_ring[i].tx__reserved2 = 0; 1209 sc->sc_txdesc_ring[i].tx__reserved3 = 0; 1210 1211 TXDESC_WRITEOUT(i); 1212 } 1213 1214 sc->sc_tx_free = ENET_TX_RING_CNT; 1215 sc->sc_tx_considx = 0; 1216 sc->sc_tx_prodidx = 0; 1217 } 1218 1219 static int 1220 enet_init_rxring(struct enet_softc *sc) 1221 { 1222 int i, error; 1223 1224 /* build RX ring */ 1225 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1226 error = enet_alloc_rxbuf(sc, i); 1227 if (error != 0) 1228 return error; 1229 } 1230 1231 sc->sc_rx_readidx = 0; 1232 1233 return 0; 1234 } 1235 1236 static int 1237 enet_alloc_rxbuf(struct enet_softc *sc, int idx) 1238 { 1239 struct mbuf *m; 1240 int error; 1241 1242 KASSERT((idx >= 0) && (idx < ENET_RX_RING_CNT)); 1243 1244 /* free mbuf if already allocated */ 1245 if (sc->sc_rxsoft[idx].rxs_mbuf != NULL) { 1246 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap); 1247 m_freem(sc->sc_rxsoft[idx].rxs_mbuf); 1248 sc->sc_rxsoft[idx].rxs_mbuf = NULL; 1249 } 1250 1251 /* allocate new mbuf cluster */ 1252 MGETHDR(m, M_DONTWAIT, MT_DATA); 1253 if (m == NULL) 1254 return ENOBUFS; 1255 MCLGET(m, M_DONTWAIT); 1256 if (!(m->m_flags & M_EXT)) { 1257 m_freem(m); 1258 return ENOBUFS; 1259 } 1260 m->m_len = MCLBYTES; 1261 m->m_next = NULL; 1262 1263 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 1264 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1265 BUS_DMA_READ | BUS_DMA_NOWAIT); 1266 if (error) { 1267 m_freem(m); 1268 return error; 1269 } 1270 1271 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 0, 1272 sc->sc_rxsoft[idx].rxs_dmamap->dm_mapsize, 1273 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1274 1275 sc->sc_rxsoft[idx].rxs_mbuf = m; 1276 enet_reset_rxdesc(sc, idx); 1277 return 0; 1278 } 1279 1280 static void 1281 enet_reset_rxdesc(struct enet_softc *sc, int idx) 1282 { 1283 uint32_t paddr; 1284 1285 paddr = sc->sc_rxsoft[idx].rxs_dmamap->dm_segs[0].ds_addr; 1286 1287 sc->sc_rxdesc_ring[idx].rx_flags1_len = 1288 RXFLAGS1_E | 1289 ((idx == (ENET_RX_RING_CNT - 1)) ? RXFLAGS1_W : 0); 1290 sc->sc_rxdesc_ring[idx].rx_databuf = paddr; 1291 sc->sc_rxdesc_ring[idx].rx_flags2 = 1292 RXFLAGS2_INT; 1293 sc->sc_rxdesc_ring[idx].rx_hl = 0; 1294 sc->sc_rxdesc_ring[idx].rx_proto = 0; 1295 sc->sc_rxdesc_ring[idx].rx_cksum = 0; 1296 sc->sc_rxdesc_ring[idx].rx_flags3 = 0; 1297 sc->sc_rxdesc_ring[idx].rx_1588timestamp = 0; 1298 sc->sc_rxdesc_ring[idx].rx__reserved2 = 0; 1299 sc->sc_rxdesc_ring[idx].rx__reserved3 = 0; 1300 1301 RXDESC_WRITEOUT(idx); 1302 } 1303 1304 static void 1305 enet_drain_txbuf(struct enet_softc *sc) 1306 { 1307 int idx; 1308 struct enet_txsoft *txs; 1309 struct ifnet *ifp; 1310 1311 ifp = &sc->sc_ethercom.ec_if; 1312 1313 for (idx = sc->sc_tx_considx; idx != sc->sc_tx_prodidx; 1314 idx = ENET_TX_NEXTIDX(idx)) { 1315 1316 /* txsoft[] is used only first segment */ 1317 txs = &sc->sc_txsoft[idx]; 1318 TXDESC_READIN(idx); 1319 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_T1) { 1320 sc->sc_txdesc_ring[idx].tx_flags1_len = 0; 1321 bus_dmamap_unload(sc->sc_dmat, 1322 txs->txs_dmamap); 1323 m_freem(txs->txs_mbuf); 1324 1325 ifp->if_oerrors++; 1326 } 1327 sc->sc_tx_free++; 1328 } 1329 } 1330 1331 static void 1332 enet_drain_rxbuf(struct enet_softc *sc) 1333 { 1334 int i; 1335 1336 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1337 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) { 1338 sc->sc_rxdesc_ring[i].rx_flags1_len = 0; 1339 bus_dmamap_unload(sc->sc_dmat, 1340 sc->sc_rxsoft[i].rxs_dmamap); 1341 m_freem(sc->sc_rxsoft[i].rxs_mbuf); 1342 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1343 } 1344 } 1345 } 1346 1347 static int 1348 enet_alloc_ring(struct enet_softc *sc) 1349 { 1350 int i, error; 1351 1352 /* 1353 * build DMA maps for TX. 1354 * TX descriptor must be able to contain mbuf chains, 1355 * so, make up ENET_MAX_PKT_NSEGS dmamap. 1356 */ 1357 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1358 error = bus_dmamap_create(sc->sc_dmat, ENET_MAX_PKT_LEN, 1359 ENET_MAX_PKT_NSEGS, ENET_MAX_PKT_LEN, 0, BUS_DMA_NOWAIT, 1360 &sc->sc_txsoft[i].txs_dmamap); 1361 1362 if (error) { 1363 aprint_error_dev(sc->sc_dev, 1364 "can't create DMA map for TX descs\n"); 1365 goto fail_1; 1366 } 1367 } 1368 1369 /* 1370 * build DMA maps for RX. 1371 * RX descripter contains An mbuf cluster, 1372 * and make up a dmamap. 1373 */ 1374 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1375 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1376 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1377 &sc->sc_rxsoft[i].rxs_dmamap); 1378 if (error) { 1379 aprint_error_dev(sc->sc_dev, 1380 "can't create DMA map for RX descs\n"); 1381 goto fail_2; 1382 } 1383 } 1384 1385 if (enet_alloc_dma(sc, sizeof(struct enet_txdesc) * ENET_TX_RING_CNT, 1386 (void **)&(sc->sc_txdesc_ring), &(sc->sc_txdesc_dmamap)) != 0) 1387 return -1; 1388 memset(sc->sc_txdesc_ring, 0, 1389 sizeof(struct enet_txdesc) * ENET_TX_RING_CNT); 1390 1391 if (enet_alloc_dma(sc, sizeof(struct enet_rxdesc) * ENET_RX_RING_CNT, 1392 (void **)&(sc->sc_rxdesc_ring), &(sc->sc_rxdesc_dmamap)) != 0) 1393 return -1; 1394 memset(sc->sc_rxdesc_ring, 0, 1395 sizeof(struct enet_rxdesc) * ENET_RX_RING_CNT); 1396 1397 return 0; 1398 1399 fail_2: 1400 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1401 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1402 bus_dmamap_destroy(sc->sc_dmat, 1403 sc->sc_rxsoft[i].rxs_dmamap); 1404 } 1405 fail_1: 1406 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1407 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1408 bus_dmamap_destroy(sc->sc_dmat, 1409 sc->sc_txsoft[i].txs_dmamap); 1410 } 1411 return error; 1412 } 1413 1414 static int 1415 enet_encap_mbufalign(struct mbuf **mp) 1416 { 1417 struct mbuf *m, *m0, *mt, *p, *x; 1418 void *ap; 1419 uint32_t alignoff, chiplen; 1420 1421 /* 1422 * iMX6 SoC ethernet controller requires 1423 * address of buffer must aligned 8, and 1424 * length of buffer must be greater than 10 (first fragment only?) 1425 */ 1426 #define ALIGNBYTE 8 1427 #define MINBUFSIZE 10 1428 #define ALIGN_PTR(p, align) \ 1429 (void *)(((uintptr_t)(p) + ((align) - 1)) & -(align)) 1430 1431 m0 = *mp; 1432 mt = p = NULL; 1433 for (m = m0; m != NULL; m = m->m_next) { 1434 alignoff = (uintptr_t)m->m_data & (ALIGNBYTE - 1); 1435 if (m->m_len < (ALIGNBYTE * 2)) { 1436 /* 1437 * rearrange mbuf data aligned 1438 * 1439 * align 8 * * * * * 1440 * +0123456789abcdef0123456789abcdef0 1441 * FROM m->m_data[___________abcdefghijklmn_______] 1442 * 1443 * +0123456789abcdef0123456789abcdef0 1444 * TO m->m_data[________abcdefghijklm___________] or 1445 * m->m_data[________________abcdefghijklmn__] 1446 */ 1447 if ((alignoff != 0) && (m->m_len != 0)) { 1448 chiplen = ALIGNBYTE - alignoff; 1449 if (M_LEADINGSPACE(m) >= alignoff) { 1450 ap = m->m_data - alignoff; 1451 memmove(ap, m->m_data, m->m_len); 1452 m->m_data = ap; 1453 } else if (M_TRAILINGSPACE(m) >= chiplen) { 1454 ap = m->m_data + chiplen; 1455 memmove(ap, m->m_data, m->m_len); 1456 m->m_data = ap; 1457 } else { 1458 /* 1459 * no space to align data. (M_READONLY?) 1460 * allocate new mbuf aligned, 1461 * and copy to it. 1462 */ 1463 MGET(x, M_DONTWAIT, m->m_type); 1464 if (x == NULL) { 1465 m_freem(m); 1466 return ENOBUFS; 1467 } 1468 MCLAIM(x, m->m_owner); 1469 if (m->m_flags & M_PKTHDR) 1470 m_move_pkthdr(x, m); 1471 x->m_len = m->m_len; 1472 x->m_data = ALIGN_PTR(x->m_data, 1473 ALIGNBYTE); 1474 memcpy(mtod(x, void *), mtod(m, void *), 1475 m->m_len); 1476 p->m_next = x; 1477 x->m_next = m_free(m); 1478 m = x; 1479 } 1480 } 1481 1482 /* 1483 * fill 1st mbuf at least 10byte 1484 * 1485 * align 8 * * * * * 1486 * +0123456789abcdef0123456789abcdef0 1487 * FROM m->m_data[________abcde___________________] 1488 * m->m_data[__fg____________________________] 1489 * m->m_data[_________________hi_____________] 1490 * m->m_data[__________jk____________________] 1491 * m->m_data[____l___________________________] 1492 * 1493 * +0123456789abcdef0123456789abcdef0 1494 * TO m->m_data[________abcdefghij______________] 1495 * m->m_data[________________________________] 1496 * m->m_data[________________________________] 1497 * m->m_data[___________k____________________] 1498 * m->m_data[____l___________________________] 1499 */ 1500 if (mt == NULL) { 1501 mt = m; 1502 while (mt->m_len == 0) { 1503 mt = mt->m_next; 1504 if (mt == NULL) { 1505 m_freem(m); 1506 return ENOBUFS; 1507 } 1508 } 1509 1510 /* mt = 1st mbuf, x = 2nd mbuf */ 1511 x = mt->m_next; 1512 while (mt->m_len < MINBUFSIZE) { 1513 if (x == NULL) { 1514 m_freem(m); 1515 return ENOBUFS; 1516 } 1517 1518 alignoff = (uintptr_t)x->m_data & 1519 (ALIGNBYTE - 1); 1520 chiplen = ALIGNBYTE - alignoff; 1521 if (chiplen > x->m_len) { 1522 chiplen = x->m_len; 1523 } else if ((mt->m_len + chiplen) < 1524 MINBUFSIZE) { 1525 /* 1526 * next mbuf should be greater 1527 * than ALIGNBYTE? 1528 */ 1529 if (x->m_len >= (chiplen + 1530 ALIGNBYTE * 2)) 1531 chiplen += ALIGNBYTE; 1532 else 1533 chiplen = x->m_len; 1534 } 1535 1536 if (chiplen && 1537 (M_TRAILINGSPACE(mt) < chiplen)) { 1538 /* 1539 * move data to the begining of 1540 * m_dat[] (aligned) to en- 1541 * large trailingspace 1542 */ 1543 ap = M_BUFADDR(mt); 1544 ap = ALIGN_PTR(ap, ALIGNBYTE); 1545 memcpy(ap, mt->m_data, 1546 mt->m_len); 1547 mt->m_data = ap; 1548 } 1549 1550 if (chiplen && 1551 (M_TRAILINGSPACE(mt) >= chiplen)) { 1552 memcpy(mt->m_data + mt->m_len, 1553 x->m_data, chiplen); 1554 mt->m_len += chiplen; 1555 m_adj(x, chiplen); 1556 } 1557 1558 x = x->m_next; 1559 } 1560 } 1561 1562 } else { 1563 mt = m; 1564 1565 /* 1566 * allocate new mbuf x, and rearrange as below; 1567 * 1568 * align 8 * * * * * 1569 * +0123456789abcdef0123456789abcdef0 1570 * FROM m->m_data[____________abcdefghijklmnopq___] 1571 * 1572 * +0123456789abcdef0123456789abcdef0 1573 * TO x->m_data[________abcdefghijkl____________] 1574 * m->m_data[________________________mnopq___] 1575 * 1576 */ 1577 if (alignoff != 0) { 1578 /* at least ALIGNBYTE */ 1579 chiplen = ALIGNBYTE - alignoff + ALIGNBYTE; 1580 1581 MGET(x, M_DONTWAIT, m->m_type); 1582 if (x == NULL) { 1583 m_freem(m); 1584 return ENOBUFS; 1585 } 1586 MCLAIM(x, m->m_owner); 1587 if (m->m_flags & M_PKTHDR) 1588 m_move_pkthdr(x, m); 1589 x->m_data = ALIGN_PTR(x->m_data, ALIGNBYTE); 1590 memcpy(mtod(x, void *), mtod(m, void *), 1591 chiplen); 1592 x->m_len = chiplen; 1593 x->m_next = m; 1594 m_adj(m, chiplen); 1595 1596 if (p == NULL) 1597 m0 = x; 1598 else 1599 p->m_next = x; 1600 } 1601 } 1602 p = m; 1603 } 1604 *mp = m0; 1605 1606 return 0; 1607 } 1608 1609 static int 1610 enet_encap_txring(struct enet_softc *sc, struct mbuf **mp) 1611 { 1612 bus_dmamap_t map; 1613 struct mbuf *m; 1614 int csumflags, idx, i, error; 1615 uint32_t flags1, flags2; 1616 1617 idx = sc->sc_tx_prodidx; 1618 map = sc->sc_txsoft[idx].txs_dmamap; 1619 1620 /* align mbuf data for claim of ENET */ 1621 error = enet_encap_mbufalign(mp); 1622 if (error != 0) 1623 return error; 1624 1625 m = *mp; 1626 csumflags = m->m_pkthdr.csum_flags; 1627 1628 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1629 BUS_DMA_NOWAIT); 1630 if (error != 0) { 1631 device_printf(sc->sc_dev, 1632 "Error mapping mbuf into TX chain: error=%d\n", error); 1633 m_freem(m); 1634 return error; 1635 } 1636 1637 if (map->dm_nsegs > sc->sc_tx_free) { 1638 bus_dmamap_unload(sc->sc_dmat, map); 1639 device_printf(sc->sc_dev, 1640 "too many mbuf chain %d\n", map->dm_nsegs); 1641 m_freem(m); 1642 return ENOBUFS; 1643 } 1644 1645 /* fill protocol cksum zero beforehand */ 1646 if (csumflags & (M_CSUM_UDPv4 | M_CSUM_TCPv4 | 1647 M_CSUM_UDPv6 | M_CSUM_TCPv6)) { 1648 int ehlen; 1649 uint16_t etype; 1650 1651 m_copydata(m, ETHER_ADDR_LEN * 2, sizeof(etype), &etype); 1652 switch (ntohs(etype)) { 1653 case ETHERTYPE_IP: 1654 case ETHERTYPE_IPV6: 1655 ehlen = ETHER_HDR_LEN; 1656 break; 1657 case ETHERTYPE_VLAN: 1658 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1659 break; 1660 default: 1661 ehlen = 0; 1662 break; 1663 } 1664 1665 if (ehlen) { 1666 const int off = 1667 M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data) + 1668 M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data); 1669 if (m->m_pkthdr.len >= ehlen + off + sizeof(uint16_t)) { 1670 uint16_t zero = 0; 1671 m_copyback(m, ehlen + off, sizeof(zero), &zero); 1672 } 1673 } 1674 } 1675 1676 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1677 BUS_DMASYNC_PREWRITE); 1678 1679 for (i = 0; i < map->dm_nsegs; i++) { 1680 flags1 = TXFLAGS1_R; 1681 flags2 = 0; 1682 1683 if (i == 0) { 1684 flags1 |= TXFLAGS1_T1; /* mark as first segment */ 1685 sc->sc_txsoft[idx].txs_mbuf = m; 1686 } 1687 1688 /* checksum offloading */ 1689 if (csumflags & (M_CSUM_UDPv4 | M_CSUM_TCPv4 | 1690 M_CSUM_UDPv6 | M_CSUM_TCPv6)) 1691 flags2 |= TXFLAGS2_PINS; 1692 if (csumflags & (M_CSUM_IPv4)) 1693 flags2 |= TXFLAGS2_IINS; 1694 1695 if (i == map->dm_nsegs - 1) { 1696 /* mark last segment */ 1697 flags1 |= TXFLAGS1_L | TXFLAGS1_TC; 1698 flags2 |= TXFLAGS2_INT; 1699 } 1700 if (idx == ENET_TX_RING_CNT - 1) { 1701 /* mark end of ring */ 1702 flags1 |= TXFLAGS1_W; 1703 } 1704 1705 sc->sc_txdesc_ring[idx].tx_databuf = map->dm_segs[i].ds_addr; 1706 sc->sc_txdesc_ring[idx].tx_flags2 = flags2; 1707 sc->sc_txdesc_ring[idx].tx_flags3 = 0; 1708 TXDESC_WRITEOUT(idx); 1709 1710 sc->sc_txdesc_ring[idx].tx_flags1_len = 1711 flags1 | TXFLAGS1_LEN(map->dm_segs[i].ds_len); 1712 TXDESC_WRITEOUT(idx); 1713 1714 idx = ENET_TX_NEXTIDX(idx); 1715 sc->sc_tx_free--; 1716 } 1717 1718 sc->sc_tx_prodidx = idx; 1719 1720 return 0; 1721 } 1722 1723 /* 1724 * device initialize 1725 */ 1726 static int 1727 enet_init_regs(struct enet_softc *sc, int init) 1728 { 1729 struct mii_data *mii; 1730 struct ifmedia_entry *ife; 1731 paddr_t paddr; 1732 uint32_t val; 1733 int miimode, fulldup, ecr_speed, rcr_speed, flowctrl; 1734 1735 if (init) { 1736 fulldup = 1; 1737 ecr_speed = ENET_ECR_SPEED; 1738 rcr_speed = 0; 1739 flowctrl = 0; 1740 } else { 1741 mii = &sc->sc_mii; 1742 ife = mii->mii_media.ifm_cur; 1743 1744 if ((ife->ifm_media & IFM_FDX) != 0) 1745 fulldup = 1; 1746 else 1747 fulldup = 0; 1748 1749 switch (IFM_SUBTYPE(ife->ifm_media)) { 1750 case IFM_10_T: 1751 ecr_speed = 0; 1752 rcr_speed = ENET_RCR_RMII_10T; 1753 break; 1754 case IFM_100_TX: 1755 ecr_speed = 0; 1756 rcr_speed = 0; 1757 break; 1758 default: 1759 ecr_speed = ENET_ECR_SPEED; 1760 rcr_speed = 0; 1761 break; 1762 } 1763 1764 flowctrl = sc->sc_flowflags & IFM_FLOW; 1765 } 1766 1767 if (sc->sc_rgmii == 0) 1768 ecr_speed = 0; 1769 1770 /* reset */ 1771 ENET_REG_WRITE(sc, ENET_ECR, ecr_speed | ENET_ECR_RESET); 1772 1773 /* mask and clear all interrupt */ 1774 ENET_REG_WRITE(sc, ENET_EIMR, 0); 1775 ENET_REG_WRITE(sc, ENET_EIR, 0xffffffff); 1776 1777 /* full duplex */ 1778 ENET_REG_WRITE(sc, ENET_TCR, fulldup ? ENET_TCR_FDEN : 0); 1779 1780 /* clear and enable MIB register */ 1781 ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR); 1782 ENET_REG_WRITE(sc, ENET_MIBC, 0); 1783 1784 /* MII speed setup. MDCclk(=2.5MHz) = (internal module clock)/((val+1)*2) */ 1785 val = (sc->sc_clock + (5000000 - 1)) / 5000000 - 1; 1786 ENET_REG_WRITE(sc, ENET_MSCR, __SHIFTIN(val, ENET_MSCR_MII_SPEED)); 1787 1788 /* Opcode/Pause Duration */ 1789 ENET_REG_WRITE(sc, ENET_OPD, 0x00010020); 1790 1791 /* Receive FIFO */ 1792 ENET_REG_WRITE(sc, ENET_RSFL, 16); /* RxFIFO Section Full */ 1793 ENET_REG_WRITE(sc, ENET_RSEM, 0x84); /* RxFIFO Section Empty */ 1794 ENET_REG_WRITE(sc, ENET_RAEM, 8); /* RxFIFO Almost Empty */ 1795 ENET_REG_WRITE(sc, ENET_RAFL, 8); /* RxFIFO Almost Full */ 1796 1797 /* Transmit FIFO */ 1798 ENET_REG_WRITE(sc, ENET_TFWR, ENET_TFWR_STRFWD | 1799 ENET_TFWR_FIFO(128)); /* TxFIFO Watermark */ 1800 ENET_REG_WRITE(sc, ENET_TSEM, 0); /* TxFIFO Section Empty */ 1801 ENET_REG_WRITE(sc, ENET_TAEM, 256); /* TxFIFO Almost Empty */ 1802 ENET_REG_WRITE(sc, ENET_TAFL, 8); /* TxFIFO Almost Full */ 1803 ENET_REG_WRITE(sc, ENET_TIPG, 12); /* Tx Inter-Packet Gap */ 1804 1805 /* hardware checksum is default off (override in TX descripter) */ 1806 ENET_REG_WRITE(sc, ENET_TACC, 0); 1807 1808 /* 1809 * align ethernet payload on 32bit, discard frames with MAC layer error, 1810 * and don't discard checksum error 1811 */ 1812 ENET_REG_WRITE(sc, ENET_RACC, ENET_RACC_SHIFT16 | ENET_RACC_LINEDIS); 1813 1814 /* maximum frame size */ 1815 val = ENET_DEFAULT_PKT_LEN; 1816 ENET_REG_WRITE(sc, ENET_FTRL, val); /* Frame Truncation Length */ 1817 1818 if (sc->sc_rgmii == 0) 1819 miimode = ENET_RCR_RMII_MODE | ENET_RCR_MII_MODE; 1820 else 1821 miimode = ENET_RCR_RGMII_EN; 1822 ENET_REG_WRITE(sc, ENET_RCR, 1823 ENET_RCR_PADEN | /* RX frame padding remove */ 1824 miimode | 1825 (flowctrl ? ENET_RCR_FCE : 0) | /* flow control enable */ 1826 rcr_speed | 1827 (fulldup ? 0 : ENET_RCR_DRT) | 1828 ENET_RCR_MAX_FL(val)); 1829 1830 /* Maximum Receive BufSize per one descriptor */ 1831 ENET_REG_WRITE(sc, ENET_MRBR, RXDESC_MAXBUFSIZE); 1832 1833 1834 /* TX/RX Descriptor Physical Address */ 1835 paddr = sc->sc_txdesc_dmamap->dm_segs[0].ds_addr; 1836 ENET_REG_WRITE(sc, ENET_TDSR, paddr); 1837 paddr = sc->sc_rxdesc_dmamap->dm_segs[0].ds_addr; 1838 ENET_REG_WRITE(sc, ENET_RDSR, paddr); 1839 /* sync cache */ 1840 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, 0, 1841 sc->sc_txdesc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1842 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, 0, 1843 sc->sc_rxdesc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1844 1845 /* enable interrupts */ 1846 val = ENET_EIMR | ENET_EIR_TXF | ENET_EIR_RXF | ENET_EIR_EBERR; 1847 if (sc->sc_imxtype == 7) 1848 val |= ENET_EIR_TXF2 | ENET_EIR_RXF2 | ENET_EIR_TXF1 | 1849 ENET_EIR_RXF1; 1850 ENET_REG_WRITE(sc, ENET_EIMR, val); 1851 1852 /* enable ether */ 1853 ENET_REG_WRITE(sc, ENET_ECR, 1854 #if _BYTE_ORDER == _LITTLE_ENDIAN 1855 ENET_ECR_DBSWP | 1856 #endif 1857 ecr_speed | 1858 ENET_ECR_EN1588 | /* use enhanced TX/RX descriptor */ 1859 ENET_ECR_ETHEREN); /* Ethernet Enable */ 1860 1861 return 0; 1862 } 1863 1864 static int 1865 enet_alloc_dma(struct enet_softc *sc, size_t size, void **addrp, 1866 bus_dmamap_t *mapp) 1867 { 1868 bus_dma_segment_t seglist[1]; 1869 int nsegs, error; 1870 1871 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seglist, 1872 1, &nsegs, M_NOWAIT)) != 0) { 1873 device_printf(sc->sc_dev, 1874 "unable to allocate DMA buffer, error=%d\n", error); 1875 goto fail_alloc; 1876 } 1877 1878 if ((error = bus_dmamem_map(sc->sc_dmat, seglist, 1, size, addrp, 1879 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1880 device_printf(sc->sc_dev, 1881 "unable to map DMA buffer, error=%d\n", 1882 error); 1883 goto fail_map; 1884 } 1885 1886 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1887 BUS_DMA_NOWAIT, mapp)) != 0) { 1888 device_printf(sc->sc_dev, 1889 "unable to create DMA map, error=%d\n", error); 1890 goto fail_create; 1891 } 1892 1893 if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL, 1894 BUS_DMA_NOWAIT)) != 0) { 1895 aprint_error_dev(sc->sc_dev, 1896 "unable to load DMA map, error=%d\n", error); 1897 goto fail_load; 1898 } 1899 1900 return 0; 1901 1902 fail_load: 1903 bus_dmamap_destroy(sc->sc_dmat, *mapp); 1904 fail_create: 1905 bus_dmamem_unmap(sc->sc_dmat, *addrp, size); 1906 fail_map: 1907 bus_dmamem_free(sc->sc_dmat, seglist, 1); 1908 fail_alloc: 1909 return error; 1910 } 1911