1 /* $NetBSD: gemini_pci.c,v 1.14 2012/10/27 17:17:38 chs Exp $ */ 2 3 /* adapted from: 4 * NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp 5 */ 6 7 /* 8 * Copyright (c) 2001 Wasabi Systems, Inc. 9 * All rights reserved. 10 * 11 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed for the NetBSD Project by 24 * Wasabi Systems, Inc. 25 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 26 * or promote products derived from this software without specific prior 27 * written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * PCI configuration support for i80312 Companion I/O chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.14 2012/10/27 17:17:38 chs Exp $"); 48 49 #include <sys/cdefs.h> 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <sys/bus.h> 60 #include <machine/intr.h> 61 62 #include <arm/pic/picvar.h> 63 64 #include <arm/gemini/gemini_reg.h> 65 #include <arm/gemini/gemini_pcivar.h> 66 #include <arm/gemini/gemini_obiovar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciconf.h> 71 72 #include <machine/pci_machdep.h> 73 74 #include "opt_gemini.h" 75 #include "opt_pci.h" 76 #include "pci.h" 77 78 void gemini_pci_attach_hook(device_t, device_t, 79 struct pcibus_attach_args *); 80 int gemini_pci_bus_maxdevs(void *, int); 81 pcitag_t gemini_pci_make_tag(void *, int, int, int); 82 void gemini_pci_decompose_tag(void *, pcitag_t, int *, int *, 83 int *); 84 pcireg_t gemini_pci_conf_read(void *, pcitag_t, int); 85 void gemini_pci_conf_write(void *, pcitag_t, int, pcireg_t); 86 int gemini_pci_conf_hook(void *, int, int, int, pcireg_t); 87 void gemini_pci_conf_interrupt(void *, int, int, int, int, int *); 88 89 int gemini_pci_intr_map(const struct pci_attach_args *, 90 pci_intr_handle_t *); 91 const char *gemini_pci_intr_string(void *, pci_intr_handle_t); 92 const struct evcnt *gemini_pci_intr_evcnt(void *, pci_intr_handle_t); 93 void *gemini_pci_intr_establish(void *, pci_intr_handle_t, 94 int, int (*)(void *), void *); 95 void gemini_pci_intr_disestablish(void *, void *); 96 int gemini_pci_intr_handler(void *v); 97 98 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 99 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 100 101 struct gemini_pci_intrq { 102 SIMPLEQ_ENTRY(gemini_pci_intrq) iq_q; 103 int (*iq_func)(void *); 104 void *iq_arg; 105 void *iq_ih; 106 }; 107 108 static SIMPLEQ_HEAD(, gemini_pci_intrq) gemini_pci_intrq = 109 SIMPLEQ_HEAD_INITIALIZER(gemini_pci_intrq); 110 111 static inline int 112 gemini_pci_intrq_empty(void) 113 { 114 return SIMPLEQ_EMPTY(&gemini_pci_intrq); 115 } 116 117 static inline void * 118 gemini_pci_intrq_insert(void *ih, int (*func)(void *), void *arg) 119 { 120 struct gemini_pci_intrq *iqp; 121 122 iqp = malloc(sizeof(*iqp), M_DEVBUF, M_NOWAIT|M_ZERO); 123 if (iqp == NULL) { 124 printf("gemini_pci_intrq_insert: malloc failed\n"); 125 return NULL; 126 } 127 128 iqp->iq_func = func; 129 iqp->iq_arg = arg; 130 iqp->iq_ih = ih; 131 SIMPLEQ_INSERT_TAIL(&gemini_pci_intrq, iqp, iq_q); 132 133 return (void *)iqp; 134 } 135 136 static inline void 137 gemini_pci_intrq_remove(void *cookie) 138 { 139 struct gemini_pci_intrq *iqp; 140 141 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 142 if ((void *)iqp == cookie) { 143 SIMPLEQ_REMOVE(&gemini_pci_intrq, 144 iqp, gemini_pci_intrq, iq_q); 145 free(iqp, M_DEVBUF); 146 return; 147 } 148 } 149 } 150 151 static inline int 152 gemini_pci_intrq_dispatch(void) 153 { 154 struct gemini_pci_intrq *iqp; 155 156 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 157 (*iqp->iq_func)(iqp->iq_arg); 158 } 159 160 return 1; 161 } 162 163 void 164 gemini_pci_init(pci_chipset_tag_t pc, void *cookie) 165 { 166 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 167 struct obio_softc *sc = cookie; 168 struct extent *ioext, *memext; 169 #endif 170 171 pc->pc_conf_v = cookie; 172 pc->pc_attach_hook = gemini_pci_attach_hook; 173 pc->pc_bus_maxdevs = gemini_pci_bus_maxdevs; 174 pc->pc_make_tag = gemini_pci_make_tag; 175 pc->pc_decompose_tag = gemini_pci_decompose_tag; 176 pc->pc_conf_read = gemini_pci_conf_read; 177 pc->pc_conf_write = gemini_pci_conf_write; 178 179 pc->pc_intr_v = cookie; 180 pc->pc_intr_map = gemini_pci_intr_map; 181 pc->pc_intr_string = gemini_pci_intr_string; 182 pc->pc_intr_evcnt = gemini_pci_intr_evcnt; 183 pc->pc_intr_establish = gemini_pci_intr_establish; 184 pc->pc_intr_disestablish = gemini_pci_intr_disestablish; 185 186 pc->pc_conf_hook = gemini_pci_conf_hook; 187 pc->pc_conf_interrupt = gemini_pci_conf_interrupt; 188 189 /* 190 * initialize copy of CFG_CMD 191 */ 192 sc->sc_pci_chipset.pc_cfg_cmd = 193 gemini_pci_conf_read(sc, 0, GEMINI_PCI_CFG_CMD); 194 195 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 196 /* 197 * Configure the PCI bus. 198 * 199 * XXX We need to revisit this. We only configure the Secondary 200 * bus (and its children). The bus configure code needs changes 201 * to support how the busses are arranged on this chip. We also 202 * need to only configure devices in the private device space on 203 * the Secondary bus. 204 */ 205 206 aprint_normal("%s: configuring Secondary PCI bus\n", 207 device_xname(sc->sc_dev)); 208 209 /* 210 * XXX PCI IO addr should be inherited ? 211 */ 212 ioext = extent_create("pciio", 213 GEMINI_PCIIO_BASE, 214 GEMINI_PCIIO_BASE + GEMINI_PCIIO_SIZE - 1, 215 NULL, 0, EX_NOWAIT); 216 217 /* 218 * XXX PCI mem addr should be inherited ? 219 */ 220 memext = extent_create("pcimem", 221 GEMINI_PCIMEM_BASE, 222 GEMINI_PCIMEM_BASE + GEMINI_PCIMEM_SIZE - 1, 223 NULL, 0, EX_NOWAIT); 224 225 pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align); 226 227 gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1, 228 PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024))) 229 | gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024)); 230 231 extent_destroy(ioext); 232 extent_destroy(memext); 233 #endif 234 } 235 236 void 237 gemini_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 238 { 239 } 240 241 int 242 gemini_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id) 243 { 244 int rv; 245 246 rv = PCI_CONF_ALL; 247 248 return rv; 249 } 250 251 void 252 gemini_pci_attach_hook(device_t parent, device_t self, 253 struct pcibus_attach_args *pba) 254 { 255 /* Nothing to do. */ 256 } 257 258 int 259 gemini_pci_bus_maxdevs(void *v, int busno) 260 { 261 return (32); 262 } 263 264 pcitag_t 265 gemini_pci_make_tag(void *v, int b, int d, int f) 266 { 267 return ((b << 16) | (d << 11) | (f << 8)); 268 } 269 270 void 271 gemini_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 272 { 273 if (bp != NULL) 274 *bp = (tag >> 16) & 0xff; 275 if (dp != NULL) 276 *dp = (tag >> 11) & 0x1f; 277 if (fp != NULL) 278 *fp = (tag >> 8) & 0x7; 279 } 280 281 struct pciconf_state { 282 uint32_t ps_addr_val; 283 int ps_b, ps_d, ps_f; 284 }; 285 286 static int 287 gemini_pci_conf_setup(struct obio_softc *sc, pcitag_t tag, int offset, 288 struct pciconf_state *ps) 289 { 290 gemini_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 291 292 ps->ps_addr_val = 293 PCI_CFG_CMD_ENB 294 | PCI_CFG_CMD_BUSn(ps->ps_b) 295 | PCI_CFG_CMD_DEVn(ps->ps_d) 296 | PCI_CFG_CMD_FUNCn(ps->ps_f) 297 | PCI_CFG_CMD_REGn(offset); 298 299 return (0); 300 } 301 302 pcireg_t 303 gemini_pci_conf_read(void *v, pcitag_t tag, int offset) 304 { 305 struct obio_softc *sc = v; 306 struct pciconf_state ps; 307 vaddr_t va; 308 pcireg_t rv; 309 u_int s; 310 311 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 312 return ((pcireg_t) -1); 313 314 PCI_CONF_LOCK(s); 315 316 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 317 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 318 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 319 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 320 } 321 322 va = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_pcicfg_ioh); 323 if (badaddr_read((void *) (va + GEMINI_PCI_CFG_DATA), sizeof(rv), &rv)) { 324 /* 325 * XXX Clear the Master Abort 326 */ 327 #if 1 328 printf("conf_read: %d/%d/%d bad address\n", 329 ps.ps_b, ps.ps_d, ps.ps_f); 330 #endif 331 rv = (pcireg_t) -1; 332 } 333 334 PCI_CONF_UNLOCK(s); 335 336 return (rv); 337 } 338 339 void 340 gemini_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 341 { 342 struct obio_softc *sc = v; 343 struct pciconf_state ps; 344 u_int s; 345 346 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 347 return; 348 349 PCI_CONF_LOCK(s); 350 351 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 352 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 353 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 354 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 355 } 356 357 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 358 GEMINI_PCI_CFG_DATA, val); 359 360 PCI_CONF_UNLOCK(s); 361 } 362 363 int 364 gemini_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 365 { 366 int irq; 367 368 irq = 8; 369 370 *ihp = irq; 371 return 0; 372 } 373 374 const char * 375 gemini_pci_intr_string(void *v, pci_intr_handle_t ih) 376 { 377 const char *name = "pci"; 378 379 return (name); 380 } 381 382 const struct evcnt * 383 gemini_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 384 { 385 return NULL; 386 } 387 388 void * 389 gemini_pci_intr_establish(void *v, pci_intr_handle_t pci_ih, int ipl, 390 int (*func)(void *), void *arg) 391 { 392 pcireg_t r; 393 void *ih=NULL; 394 int irq; 395 void *cookie; 396 397 irq = (int)pci_ih; 398 399 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 400 r |= CFG_REG_CTL2_INTMASK_INT_ABCD; 401 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 402 403 if (gemini_pci_intrq_empty()) 404 ih = intr_establish(irq, ipl, IST_LEVEL_HIGH, 405 gemini_pci_intr_handler, v); 406 407 cookie = gemini_pci_intrq_insert(ih, func, arg); 408 if (cookie == NULL) { 409 if (gemini_pci_intrq_empty()) 410 intr_disestablish(ih); 411 } 412 413 return cookie; 414 } 415 416 void 417 gemini_pci_intr_disestablish(void *v, void *cookie) 418 { 419 pcireg_t r; 420 struct gemini_pci_intrq *iqp = (struct gemini_pci_intrq *)cookie; 421 void *ih = iqp->iq_ih; 422 423 gemini_pci_intrq_remove(cookie); 424 if (gemini_pci_intrq_empty()) { 425 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 426 r &= ~CFG_REG_CTL2_INTMASK_INT_ABCD; 427 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 428 intr_disestablish(ih); 429 } 430 } 431 432 int 433 gemini_pci_intr_handler(void *v) 434 { 435 pcireg_t r; 436 int rv; 437 438 /* 439 * dispatch PCI device interrupt handlers 440 */ 441 rv = gemini_pci_intrq_dispatch(); 442 443 /* 444 * ack Gemini PCI interrupts 445 */ 446 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 447 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 448 449 return rv; 450 } 451