1 /* $NetBSD: gemini_pci.c,v 1.8 2010/01/05 13:14:56 mbalmer Exp $ */ 2 3 /* adapted from: 4 * NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp 5 */ 6 7 /* 8 * Copyright (c) 2001 Wasabi Systems, Inc. 9 * All rights reserved. 10 * 11 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed for the NetBSD Project by 24 * Wasabi Systems, Inc. 25 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 26 * or promote products derived from this software without specific prior 27 * written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * PCI configuration support for i80312 Companion I/O chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.8 2010/01/05 13:14:56 mbalmer Exp $"); 48 49 #include <sys/cdefs.h> 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <machine/bus.h> 60 #include <machine/intr.h> 61 62 #include <arm/pic/picvar.h> 63 64 #include <arm/gemini/gemini_reg.h> 65 #include <arm/gemini/gemini_pcivar.h> 66 #include <arm/gemini/gemini_obiovar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciconf.h> 71 72 #include <machine/pci_machdep.h> 73 74 #include "opt_gemini.h" 75 #include "opt_pci.h" 76 #include "pci.h" 77 78 void gemini_pci_attach_hook(struct device *, struct device *, 79 struct pcibus_attach_args *); 80 int gemini_pci_bus_maxdevs(void *, int); 81 pcitag_t gemini_pci_make_tag(void *, int, int, int); 82 void gemini_pci_decompose_tag(void *, pcitag_t, int *, int *, 83 int *); 84 pcireg_t gemini_pci_conf_read(void *, pcitag_t, int); 85 void gemini_pci_conf_write(void *, pcitag_t, int, pcireg_t); 86 int gemini_pci_conf_hook(pci_chipset_tag_t, int, int, int, 87 pcireg_t); 88 89 int gemini_pci_intr_map(struct pci_attach_args *, 90 pci_intr_handle_t *); 91 const char *gemini_pci_intr_string(void *, pci_intr_handle_t); 92 const struct evcnt *gemini_pci_intr_evcnt(void *, pci_intr_handle_t); 93 void *gemini_pci_intr_establish(void *, pci_intr_handle_t, 94 int, int (*)(void *), void *); 95 void gemini_pci_intr_disestablish(void *, void *); 96 int gemini_pci_intr_handler(void *v); 97 98 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 99 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 100 101 struct gemini_pci_intrq { 102 SIMPLEQ_ENTRY(gemini_pci_intrq) iq_q; 103 int (*iq_func)(void *); 104 void *iq_arg; 105 void *iq_ih; 106 }; 107 108 static SIMPLEQ_HEAD(, gemini_pci_intrq) gemini_pci_intrq = 109 SIMPLEQ_HEAD_INITIALIZER(gemini_pci_intrq); 110 111 static inline int 112 gemini_pci_intrq_empty(void) 113 { 114 return SIMPLEQ_EMPTY(&gemini_pci_intrq); 115 } 116 117 static inline void * 118 gemini_pci_intrq_insert(void *ih, int (*func)(void *), void *arg) 119 { 120 struct gemini_pci_intrq *iqp; 121 122 iqp = malloc(sizeof(*iqp), M_DEVBUF, M_NOWAIT|M_ZERO); 123 if (iqp == NULL) { 124 printf("gemini_pci_intrq_insert: malloc failed\n"); 125 return NULL; 126 } 127 128 iqp->iq_func = func; 129 iqp->iq_arg = arg; 130 iqp->iq_ih = ih; 131 SIMPLEQ_INSERT_TAIL(&gemini_pci_intrq, iqp, iq_q); 132 133 return (void *)iqp; 134 } 135 136 static inline void 137 gemini_pci_intrq_remove(void *cookie) 138 { 139 struct gemini_pci_intrq *iqp; 140 141 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 142 if ((void *)iqp == cookie) { 143 SIMPLEQ_REMOVE(&gemini_pci_intrq, 144 iqp, gemini_pci_intrq, iq_q); 145 free(iqp, M_DEVBUF); 146 return; 147 } 148 } 149 } 150 151 static inline int 152 gemini_pci_intrq_dispatch(void) 153 { 154 struct gemini_pci_intrq *iqp; 155 156 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 157 (*iqp->iq_func)(iqp->iq_arg); 158 } 159 160 return 1; 161 } 162 163 void 164 gemini_pci_init(pci_chipset_tag_t pc, void *cookie) 165 { 166 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 167 struct obio_softc *sc = cookie; 168 struct extent *ioext, *memext; 169 #endif 170 171 pc->pc_conf_v = cookie; 172 pc->pc_attach_hook = gemini_pci_attach_hook; 173 pc->pc_bus_maxdevs = gemini_pci_bus_maxdevs; 174 pc->pc_make_tag = gemini_pci_make_tag; 175 pc->pc_decompose_tag = gemini_pci_decompose_tag; 176 pc->pc_conf_read = gemini_pci_conf_read; 177 pc->pc_conf_write = gemini_pci_conf_write; 178 179 pc->pc_intr_v = cookie; 180 pc->pc_intr_map = gemini_pci_intr_map; 181 pc->pc_intr_string = gemini_pci_intr_string; 182 pc->pc_intr_evcnt = gemini_pci_intr_evcnt; 183 pc->pc_intr_establish = gemini_pci_intr_establish; 184 pc->pc_intr_disestablish = gemini_pci_intr_disestablish; 185 186 pc->pc_conf_hook = gemini_pci_conf_hook; 187 188 /* 189 * initialize copy of CFG_CMD 190 */ 191 sc->sc_pci_chipset.pc_cfg_cmd = 192 gemini_pci_conf_read(sc, 0, GEMINI_PCI_CFG_CMD); 193 194 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 195 /* 196 * Configure the PCI bus. 197 * 198 * XXX We need to revisit this. We only configure the Secondary 199 * bus (and its children). The bus configure code needs changes 200 * to support how the busses are arranged on this chip. We also 201 * need to only configure devices in the private device space on 202 * the Secondary bus. 203 */ 204 205 aprint_normal("%s: configuring Secondary PCI bus\n", 206 device_xname(sc->sc_dev)); 207 208 /* 209 * XXX PCI IO addr should be inherited ? 210 */ 211 ioext = extent_create("pciio", 212 GEMINI_PCIIO_BASE, 213 GEMINI_PCIIO_BASE + GEMINI_PCIIO_SIZE - 1, 214 M_DEVBUF, NULL, 0, EX_NOWAIT); 215 216 /* 217 * XXX PCI mem addr should be inherited ? 218 */ 219 memext = extent_create("pcimem", 220 GEMINI_PCIMEM_BASE, 221 GEMINI_PCIMEM_BASE + GEMINI_PCIMEM_SIZE - 1, 222 M_DEVBUF, NULL, 0, EX_NOWAIT); 223 224 pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align); 225 226 gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1, 227 PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024))) 228 | gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024)); 229 230 extent_destroy(ioext); 231 extent_destroy(memext); 232 #endif 233 } 234 235 void 236 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 237 { 238 } 239 240 int 241 gemini_pci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function, pcireg_t id) 242 { 243 int rv; 244 245 rv = PCI_CONF_ALL; 246 247 return rv; 248 } 249 250 void 251 gemini_pci_attach_hook(struct device *parent, struct device *self, 252 struct pcibus_attach_args *pba) 253 { 254 /* Nothing to do. */ 255 } 256 257 int 258 gemini_pci_bus_maxdevs(void *v, int busno) 259 { 260 return (32); 261 } 262 263 pcitag_t 264 gemini_pci_make_tag(void *v, int b, int d, int f) 265 { 266 return ((b << 16) | (d << 11) | (f << 8)); 267 } 268 269 void 270 gemini_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 271 { 272 if (bp != NULL) 273 *bp = (tag >> 16) & 0xff; 274 if (dp != NULL) 275 *dp = (tag >> 11) & 0x1f; 276 if (fp != NULL) 277 *fp = (tag >> 8) & 0x7; 278 } 279 280 struct pciconf_state { 281 uint32_t ps_addr_val; 282 int ps_b, ps_d, ps_f; 283 }; 284 285 static int 286 gemini_pci_conf_setup(struct obio_softc *sc, pcitag_t tag, int offset, 287 struct pciconf_state *ps) 288 { 289 gemini_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 290 291 ps->ps_addr_val = 292 PCI_CFG_CMD_ENB 293 | PCI_CFG_CMD_BUSn(ps->ps_b) 294 | PCI_CFG_CMD_DEVn(ps->ps_d) 295 | PCI_CFG_CMD_FUNCn(ps->ps_f) 296 | PCI_CFG_CMD_REGn(offset); 297 298 return (0); 299 } 300 301 pcireg_t 302 gemini_pci_conf_read(void *v, pcitag_t tag, int offset) 303 { 304 struct obio_softc *sc = v; 305 struct pciconf_state ps; 306 vaddr_t va; 307 pcireg_t rv; 308 u_int s; 309 310 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 311 return ((pcireg_t) -1); 312 313 PCI_CONF_LOCK(s); 314 315 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 316 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 317 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 318 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 319 } 320 321 va = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_pcicfg_ioh); 322 if (badaddr_read((void *) (va + GEMINI_PCI_CFG_DATA), sizeof(rv), &rv)) { 323 /* 324 * XXX Clear the Master Abort 325 */ 326 #if 1 327 printf("conf_read: %d/%d/%d bad address\n", 328 ps.ps_b, ps.ps_d, ps.ps_f); 329 #endif 330 rv = (pcireg_t) -1; 331 } 332 333 PCI_CONF_UNLOCK(s); 334 335 return (rv); 336 } 337 338 void 339 gemini_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 340 { 341 struct obio_softc *sc = v; 342 struct pciconf_state ps; 343 u_int s; 344 345 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 346 return; 347 348 PCI_CONF_LOCK(s); 349 350 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 351 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 352 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 353 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 354 } 355 356 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 357 GEMINI_PCI_CFG_DATA, val); 358 359 PCI_CONF_UNLOCK(s); 360 } 361 362 int 363 gemini_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 364 { 365 int irq; 366 367 irq = 8; 368 369 *ihp = irq; 370 return 0; 371 } 372 373 const char * 374 gemini_pci_intr_string(void *v, pci_intr_handle_t ih) 375 { 376 const char *name = "pci"; 377 378 return (name); 379 } 380 381 const struct evcnt * 382 gemini_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 383 { 384 return NULL; 385 } 386 387 void * 388 gemini_pci_intr_establish(void *v, pci_intr_handle_t pci_ih, int ipl, 389 int (*func)(void *), void *arg) 390 { 391 pcireg_t r; 392 void *ih=NULL; 393 int irq; 394 void *cookie; 395 396 irq = (int)pci_ih; 397 398 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 399 r |= CFG_REG_CTL2_INTMASK_INT_ABCD; 400 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 401 402 if (gemini_pci_intrq_empty()) 403 ih = intr_establish(irq, ipl, IST_LEVEL_HIGH, 404 gemini_pci_intr_handler, v); 405 406 cookie = gemini_pci_intrq_insert(ih, func, arg); 407 if (cookie == NULL) { 408 if (gemini_pci_intrq_empty()) 409 intr_disestablish(ih); 410 } 411 412 return cookie; 413 } 414 415 void 416 gemini_pci_intr_disestablish(void *v, void *cookie) 417 { 418 pcireg_t r; 419 struct gemini_pci_intrq *iqp = (struct gemini_pci_intrq *)cookie; 420 void *ih = iqp->iq_ih; 421 422 gemini_pci_intrq_remove(cookie); 423 if (gemini_pci_intrq_empty()) { 424 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 425 r &= ~CFG_REG_CTL2_INTMASK_INT_ABCD; 426 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 427 intr_disestablish(ih); 428 } 429 } 430 431 int 432 gemini_pci_intr_handler(void *v) 433 { 434 pcireg_t r; 435 int rv; 436 437 /* 438 * dispatch PCI device interrupt handlers 439 */ 440 rv = gemini_pci_intrq_dispatch(); 441 442 /* 443 * ack Gemini PCI interrupts 444 */ 445 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 446 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 447 448 return rv; 449 } 450 451