1 /* $NetBSD: gemini_pci.c,v 1.20 2019/11/10 21:16:23 chs Exp $ */ 2 3 /* adapted from: 4 * NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp 5 */ 6 7 /* 8 * Copyright (c) 2001 Wasabi Systems, Inc. 9 * All rights reserved. 10 * 11 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed for the NetBSD Project by 24 * Wasabi Systems, Inc. 25 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 26 * or promote products derived from this software without specific prior 27 * written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * PCI configuration support for i80312 Companion I/O chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.20 2019/11/10 21:16:23 chs Exp $"); 48 49 #include "opt_gemini.h" 50 #include "opt_pci.h" 51 #include "pci.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/extent.h> 57 #include <sys/malloc.h> 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 #include <dev/pci/pciconf.h> 66 67 #include <arm/locore.h> 68 69 #include <arm/pic/picvar.h> 70 71 #include <arm/gemini/gemini_reg.h> 72 #include <arm/gemini/gemini_pcivar.h> 73 #include <arm/gemini/gemini_obiovar.h> 74 75 void gemini_pci_attach_hook(device_t, device_t, 76 struct pcibus_attach_args *); 77 int gemini_pci_bus_maxdevs(void *, int); 78 pcitag_t gemini_pci_make_tag(void *, int, int, int); 79 void gemini_pci_decompose_tag(void *, pcitag_t, int *, int *, 80 int *); 81 pcireg_t gemini_pci_conf_read(void *, pcitag_t, int); 82 void gemini_pci_conf_write(void *, pcitag_t, int, pcireg_t); 83 int gemini_pci_conf_hook(void *, int, int, int, pcireg_t); 84 void gemini_pci_conf_interrupt(void *, int, int, int, int, int *); 85 86 int gemini_pci_intr_map(const struct pci_attach_args *, 87 pci_intr_handle_t *); 88 const char *gemini_pci_intr_string(void *, pci_intr_handle_t, 89 char *, size_t); 90 const struct evcnt *gemini_pci_intr_evcnt(void *, pci_intr_handle_t); 91 void *gemini_pci_intr_establish(void *, pci_intr_handle_t, 92 int, int (*)(void *), void *, const char *); 93 void gemini_pci_intr_disestablish(void *, void *); 94 int gemini_pci_intr_handler(void *v); 95 96 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 97 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 98 99 struct gemini_pci_intrq { 100 SIMPLEQ_ENTRY(gemini_pci_intrq) iq_q; 101 int (*iq_func)(void *); 102 void *iq_arg; 103 void *iq_ih; 104 }; 105 106 static SIMPLEQ_HEAD(, gemini_pci_intrq) gemini_pci_intrq = 107 SIMPLEQ_HEAD_INITIALIZER(gemini_pci_intrq); 108 109 static inline int 110 gemini_pci_intrq_empty(void) 111 { 112 return SIMPLEQ_EMPTY(&gemini_pci_intrq); 113 } 114 115 static inline void * 116 gemini_pci_intrq_insert(void *ih, int (*func)(void *), void *arg) 117 { 118 struct gemini_pci_intrq *iqp; 119 120 iqp = malloc(sizeof(*iqp), M_DEVBUF, M_WAITOK|M_ZERO); 121 iqp->iq_func = func; 122 iqp->iq_arg = arg; 123 iqp->iq_ih = ih; 124 SIMPLEQ_INSERT_TAIL(&gemini_pci_intrq, iqp, iq_q); 125 126 return (void *)iqp; 127 } 128 129 static inline void 130 gemini_pci_intrq_remove(void *cookie) 131 { 132 struct gemini_pci_intrq *iqp; 133 134 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 135 if ((void *)iqp == cookie) { 136 SIMPLEQ_REMOVE(&gemini_pci_intrq, 137 iqp, gemini_pci_intrq, iq_q); 138 free(iqp, M_DEVBUF); 139 return; 140 } 141 } 142 } 143 144 static inline int 145 gemini_pci_intrq_dispatch(void) 146 { 147 struct gemini_pci_intrq *iqp; 148 149 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 150 (*iqp->iq_func)(iqp->iq_arg); 151 } 152 153 return 1; 154 } 155 156 void 157 gemini_pci_init(pci_chipset_tag_t pc, void *cookie) 158 { 159 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 160 struct obio_softc *sc = cookie; 161 struct extent *ioext, *memext; 162 #endif 163 164 pc->pc_conf_v = cookie; 165 pc->pc_attach_hook = gemini_pci_attach_hook; 166 pc->pc_bus_maxdevs = gemini_pci_bus_maxdevs; 167 pc->pc_make_tag = gemini_pci_make_tag; 168 pc->pc_decompose_tag = gemini_pci_decompose_tag; 169 pc->pc_conf_read = gemini_pci_conf_read; 170 pc->pc_conf_write = gemini_pci_conf_write; 171 172 pc->pc_intr_v = cookie; 173 pc->pc_intr_map = gemini_pci_intr_map; 174 pc->pc_intr_string = gemini_pci_intr_string; 175 pc->pc_intr_evcnt = gemini_pci_intr_evcnt; 176 pc->pc_intr_establish = gemini_pci_intr_establish; 177 pc->pc_intr_disestablish = gemini_pci_intr_disestablish; 178 179 pc->pc_conf_hook = gemini_pci_conf_hook; 180 pc->pc_conf_interrupt = gemini_pci_conf_interrupt; 181 182 /* 183 * initialize copy of CFG_CMD 184 */ 185 sc->sc_pci_chipset.pc_cfg_cmd = 186 gemini_pci_conf_read(sc, 0, GEMINI_PCI_CFG_CMD); 187 188 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 189 /* 190 * Configure the PCI bus. 191 * 192 * XXX We need to revisit this. We only configure the Secondary 193 * bus (and its children). The bus configure code needs changes 194 * to support how the busses are arranged on this chip. We also 195 * need to only configure devices in the private device space on 196 * the Secondary bus. 197 */ 198 199 aprint_normal("%s: configuring Secondary PCI bus\n", 200 device_xname(sc->sc_dev)); 201 202 /* 203 * XXX PCI IO addr should be inherited ? 204 */ 205 ioext = extent_create("pciio", 206 GEMINI_PCIIO_BASE, 207 GEMINI_PCIIO_BASE + GEMINI_PCIIO_SIZE - 1, 208 NULL, 0, EX_NOWAIT); 209 210 /* 211 * XXX PCI mem addr should be inherited ? 212 */ 213 memext = extent_create("pcimem", 214 GEMINI_PCIMEM_BASE, 215 GEMINI_PCIMEM_BASE + GEMINI_PCIMEM_SIZE - 1, 216 NULL, 0, EX_NOWAIT); 217 218 pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align); 219 220 gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1, 221 PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024))) 222 | gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024)); 223 224 extent_destroy(ioext); 225 extent_destroy(memext); 226 #endif 227 } 228 229 void 230 gemini_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 231 { 232 } 233 234 int 235 gemini_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id) 236 { 237 int rv; 238 239 rv = PCI_CONF_ALL; 240 241 return rv; 242 } 243 244 void 245 gemini_pci_attach_hook(device_t parent, device_t self, 246 struct pcibus_attach_args *pba) 247 { 248 /* Nothing to do. */ 249 } 250 251 int 252 gemini_pci_bus_maxdevs(void *v, int busno) 253 { 254 return (32); 255 } 256 257 pcitag_t 258 gemini_pci_make_tag(void *v, int b, int d, int f) 259 { 260 return ((b << 16) | (d << 11) | (f << 8)); 261 } 262 263 void 264 gemini_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 265 { 266 if (bp != NULL) 267 *bp = (tag >> 16) & 0xff; 268 if (dp != NULL) 269 *dp = (tag >> 11) & 0x1f; 270 if (fp != NULL) 271 *fp = (tag >> 8) & 0x7; 272 } 273 274 struct pciconf_state { 275 uint32_t ps_addr_val; 276 int ps_b, ps_d, ps_f; 277 }; 278 279 static int 280 gemini_pci_conf_setup(struct obio_softc *sc, pcitag_t tag, int offset, 281 struct pciconf_state *ps) 282 { 283 284 if ((unsigned int)offset >= PCI_CONF_SIZE) 285 return (1); 286 287 gemini_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 288 289 ps->ps_addr_val = 290 PCI_CFG_CMD_ENB 291 | PCI_CFG_CMD_BUSn(ps->ps_b) 292 | PCI_CFG_CMD_DEVn(ps->ps_d) 293 | PCI_CFG_CMD_FUNCn(ps->ps_f) 294 | PCI_CFG_CMD_REGn(offset); 295 296 return (0); 297 } 298 299 pcireg_t 300 gemini_pci_conf_read(void *v, pcitag_t tag, int offset) 301 { 302 struct obio_softc *sc = v; 303 struct pciconf_state ps; 304 vaddr_t va; 305 pcireg_t rv; 306 u_int s; 307 308 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 309 return ((pcireg_t) -1); 310 311 PCI_CONF_LOCK(s); 312 313 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 314 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 315 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 316 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 317 } 318 319 va = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_pcicfg_ioh); 320 if (badaddr_read((void *) (va + GEMINI_PCI_CFG_DATA), sizeof(rv), &rv)) { 321 /* 322 * XXX Clear the Master Abort 323 */ 324 #if 1 325 printf("conf_read: %d/%d/%d bad address\n", 326 ps.ps_b, ps.ps_d, ps.ps_f); 327 #endif 328 rv = (pcireg_t) -1; 329 } 330 331 PCI_CONF_UNLOCK(s); 332 333 return (rv); 334 } 335 336 void 337 gemini_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 338 { 339 struct obio_softc *sc = v; 340 struct pciconf_state ps; 341 u_int s; 342 343 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 344 return; 345 346 PCI_CONF_LOCK(s); 347 348 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 349 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 350 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 351 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 352 } 353 354 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 355 GEMINI_PCI_CFG_DATA, val); 356 357 PCI_CONF_UNLOCK(s); 358 } 359 360 int 361 gemini_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 362 { 363 int irq; 364 365 irq = 8; 366 367 *ihp = irq; 368 return 0; 369 } 370 371 const char * 372 gemini_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 373 { 374 strlcpy(buf, "pci", len); 375 return buf; 376 } 377 378 const struct evcnt * 379 gemini_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 380 { 381 return NULL; 382 } 383 384 void * 385 gemini_pci_intr_establish(void *v, pci_intr_handle_t pci_ih, int ipl, 386 int (*func)(void *), void *arg, const char *xname) 387 { 388 pcireg_t r; 389 void *ih=NULL; 390 int irq; 391 void *cookie; 392 393 irq = (int)pci_ih; 394 395 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 396 r |= CFG_REG_CTL2_INTMASK_INT_ABCD; 397 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 398 399 if (gemini_pci_intrq_empty()) 400 ih = intr_establish_xname(irq, ipl, IST_LEVEL_HIGH, 401 gemini_pci_intr_handler, v, xname); 402 403 cookie = gemini_pci_intrq_insert(ih, func, arg); 404 return cookie; 405 } 406 407 void 408 gemini_pci_intr_disestablish(void *v, void *cookie) 409 { 410 pcireg_t r; 411 struct gemini_pci_intrq *iqp = (struct gemini_pci_intrq *)cookie; 412 void *ih = iqp->iq_ih; 413 414 gemini_pci_intrq_remove(cookie); 415 if (gemini_pci_intrq_empty()) { 416 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 417 r &= ~CFG_REG_CTL2_INTMASK_INT_ABCD; 418 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 419 intr_disestablish(ih); 420 } 421 } 422 423 int 424 gemini_pci_intr_handler(void *v) 425 { 426 pcireg_t r; 427 int rv; 428 429 /* 430 * dispatch PCI device interrupt handlers 431 */ 432 rv = gemini_pci_intrq_dispatch(); 433 434 /* 435 * ack Gemini PCI interrupts 436 */ 437 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 438 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 439 440 return rv; 441 } 442